JPS62195797A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve a read margin by providing the second load MOSFET selectively supplying a part of the read current for a selected memory cell in parallel connection with a load MOSFET to supply the said read current, so as to lift an operational ceiling voltage. CONSTITUTION:When a selected memory cell is in a high threshold voltage (logic '0') in comparison with the selection level of a word line, the output voltage Vs of an initial-stage amplifier circuit is determined solely according to the conductances ratios of a MOSFETQ12, an amplifying MOSFETQ11, a Y-gate MOSFET and the memory cell Q1 because the conductance of a MOSFETQ13 is small since it acts as a constant-current power source. As a power source voltage Vcc rises, the selection level of a word line comes higher than a comparatively high threshold voltage, by allowing the memory cell Q1 to be turned ON. Accordingly, the enhancing in conductance of the load MOSFETQ12 is limited. Therefore, the large drop of an output voltage V0 is compensated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and for example, uses FAMO3 (floating gate avalanche injection MOS) as a memory element (memory cell).
The present invention relates to a technology effective for use in fF and FROM (Electrically Programmable Read Only Memory).

[Conventional technology]

EPR that uses a semiconductor element like FAMO3 as a memory element
OM is known, for example, from Japanese Patent Laid-Open No. 152933/1983.

The FAMOS transistor has a logic "1" in its normal state where writing is not performed, and has a threshold voltage lower than the selection level of the word line to which its gate is coupled. Further, the written state is set to logic "O", and the gate has a threshold voltage higher than the selection level of the word line to which it is coupled. however,
As the operating power supply voltage Vcc rises, the selection level of the word line also rises, and when the level exceeds the high threshold voltage, the FAMoS transistor switches from the off state to the on state.

[Problem that the invention seeks to solve]

Figure 3 shows the EPR developed earlier by the present inventors.
A readout circuit including an OM sense amplifier is shown. In this EFROM, memory cell Q1 of memory array M-ARY to be read is selected by word line W1 and YG MOSFET Q7. The read operation of the memory cell Q1 is performed using a gate-grounded amplifying MOS whose gate is supplied with a gate bias voltage by an output signal of an inverter circuit N1 which receives a read voltage according to the on/off state of the memory cell Q1.
FETQI 1 and the load M provided on its drain
This is performed by the first stage amplifier circuit consisting of OSFETQ12. That is, the output voltage of the first stage amplifier circuit is
The level is set according to the conductance ratio of FETQI2. This read voltage Vs has dependence on the operating power supply voltage as shown in FIG. That is, in a voltage range where the potential of the operating power supply voltage Vcc is lower than the relatively high threshold voltage of the memory cell, the memory cell Q1 is in an off state, so that the read high level vO increases as the operating power supply voltage Vcc rises. . On the other hand, the read level V1 of a memory cell with a relatively low threshold voltage is
Since its conductance is made sufficiently large for FET QI 1, it is kept approximately constant. Such high level read voltage vO and low level read voltage V
1 is determined by the logic threshold voltage V1t of the CMOS inverter circuit acting as the sense amplifier SA.

The inventors have discovered that such an EFROM readout circuit has the following problems. That is, when the power supply voltage Vcc rises and the selection level of the word line becomes higher than the relatively high threshold voltage of the memory cell, the memory cell Q1 is turned on, and the power supply voltage Vcc
As the value increases, its conductance also increases. As a result, the high-level read voltage vO decreases as the power supply voltage cc rises. In this case, the load MO
SFETQ12 is operated in a non-saturation region because its gate is connected to the ground potential of the circuit, and as the readout voltage vO decreases, the voltage between the source and drain also increases, and the readout voltage vO increases. It acts to promote the decline.

Therefore, this read voltage 0 is the logic threshold voltage vl of the CMOS inverter circuit of the sense amplifier SA.
When the voltage reaches t, the specified operating upper limit voltage decreases. Therefore, in order to increase the above operating upper limit voltage,
The present inventors have considered suppressing the drop in the read voltage vO, as shown by the dotted line in FIG. 3, by increasing the size of the load MOSFET Q12 and increasing its conductance. However, in this way negative 1
When the conductance of M05FET12 is increased,
Conversely, when reading a memory cell with a relatively low threshold voltage, the low level output 11 voltage V1 determined by its conductance ratio increases as shown by the dotted line in Figure 3, so the low level side The read margin becomes small.

Note that the above-mentioned EFROM device is often used with a high operating voltage Vcc in order to increase write efficiency, etc., and when the above-mentioned upper limit voltage for operation is low, it enters verify mode (read check of written information). becomes impossible. In other words, efficient writing using a relatively high voltage becomes impossible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device in which the upper limit voltage for operation is increased and the read margin is improved.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
By receiving an appropriate bias voltage on its gate in parallel with a load MOSFET that supplies read current to the selected memory cell, and operating in the saturation region of its characteristics,
a second load MOSFE' for selectively supplying a portion of the read current to the selected memory cell;
1".

[For production]

According to the above means, during a read operation of a memory cell with a relatively high threshold voltage (logic "O"), the first and second load MOSFETs supply a read current in parallel, so that the load High power supply voltage Vc without increasing the conductance of the entire MOSFET
It is possible to supply the necessary read current up to c.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a memory array and its peripheral portion when the present invention is applied to an EFROM. Although not particularly limited, each circuit element in the figure is
The well-known CMO3 (complementary MO3) integrated circuit fabrication technique is formed on a single semiconductor substrate, such as single crystal silicon. In the same figure, the MOS FET with an arrow added to the channel (back gate) part is a P-channel type, and the N-channel MOSFET with no arrow added.
Distinguished from SFET.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
FETs are made of polysilicon formed on the surface of such a semiconductor substrate, including a source region, a drain region, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source and drain regions. It consists of a gate electrode. The P-channel MOS FET is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region has a P well formed thereon.
Configures the substrate gate of the channel MOSFET. The substrate gate of the P-channel MOSFET, ie, the N-type well region, is coupled to the power supply terminal Vcc of FIG.

In the EFROM of this embodiment, an address buffer XADB receives X address signals AXO-AXi and Y address signals AYO-AYj supplied from external terminals.
A complementary address signal is formed by YADB and YADB, and is supplied to address decoders XDCR and YDCR.

In the figure, the address buffer and address decoder are included in one circuit block XADB-DcR9YADB-DcR.
are shown respectively. Although not particularly limited, the address buffers XADB and YADB are activated by an internal timing signal co, take in an address signal supplied to an external terminal, and output an internal address signal having the same phase as the address signal and an internal address signal having the opposite phase. A complementary address signal consisting of:

The address decoder XDCR is the X address buffer XA.
The complementary address signal supplied from the DH is decoded to form a selection signal for the word line of the memory array M-ARY. Further, the address decoder YDCR decodes the complementary address signal supplied from the Y address buffer YADB, forms a selection signal for the data line of the memory array M-ARY, and supplies it to the Y gate YG.

In the EPROM of this embodiment, data is written or read in units of 8 pins, and FIG. 1 shows the memory array M-ARY, data buffer sofa DIB, data output buffer DOB, etc. for 1 bit. has been done. The memory array M-ARY is composed of a plurality of representative FAMO3I-transistors (non-volatile memory elements Q1 to Q6), word lines w1 to Wn, and data lines D1 to Dn. In the memory array M-ARY, the control gates of the FAMOS transistors Q1 to Q3 and Q4 to Q6 arranged in the same row are connected to the corresponding word lines Wl and W2, respectively, and the control gates of the FAMOS transistors Q1 and Q4 arranged in the same column are connected to the corresponding word lines Wl and W2, respectively. The drains of Q3 and Q6 are connected to the corresponding data lines D1 to Dn, respectively. The common source line C8 of the FAMOS transistors is grounded via a depletion type MOSFET QIO which receives the write internal timing signal we, although this is not particularly limited. During writing, the conductance of MOSFET QIO is made relatively small by the low level of the internal timing signal Wτ. As a result, the potential of the common source line C3 becomes a relatively high potential, and the potential of the common source line C3 becomes relatively high.
The threshold voltage of the MO3 transistor is made relatively high.

Therefore, even if a high write voltage is supplied to the data line during a write operation, the leakage current flowing through the FAMOS transistor connected to the non-selected word line can be reduced.

As a result, the write current supplied from the external terminal is selected and supplied only to the nine FAMO3l- transistors, so that an efficient write operation can be performed. Note that during the read operation, the conductance of the MOSFET QIO is made relatively large due to the high level of the internal timing signal W1, so that the read operation is performed at high speed.

Each of the data lines D1 to Dn is connected to the address decoder Y.
(Y game) receiving the selection signal formed by the DCR
It is connected to the common data line CD via G switch MOSFETs Q7 to Q9.

The common data line CD is connected to an output terminal of a data driver sofa DIB that receives a write signal input from an external terminal DO. The data driver DIB receives an internal timing signal w supplied from the timing control circuit CTL.
activated in the write operation mode by e;
Write data input from the external terminal DO is set to a predetermined write level and is supplied to the common data line CD.

Timing control circuit CTL is connected to external terminal CE.

Upon receiving the chip enable signal σ ball supplied to OE, PGM and vpp, the output enable signal of 1, the program signal PGM and the high voltage VPfl for writing, the operation mode is identified and the internal timing signals ce, we
, oe, etc., and a read low voltage Vcc selectively supplied to the address decoder and data input cover sofa DIR.
/A high voltage for writing (Vl)P, etc. is formed. for example,
If the chip enable signal CB is at a low level, the output enable signal σ1 is at a high level, and the program signal 71 is at a low level, the write operation (program) mode is identified, and the internal timing signals ce and we are set at a high level, inverted signal 11 of we and O
e is set to low level. Further, a high voltage Vpp for writing is supplied to the address decoder circuits XDCR, YDCR and the data input buffer sofa DIH.

On the other hand, if the chip enable signal CB is at a low level, the output enable signal OE is at a low level, the program signal PGM is at a high level, and vpp is a high voltage for writing, the verify mode is identified, and the internal timing signals C6, oe, and we are The inverted signal W1 is set to high level. In this verify mode, XDCR, YD
The operating voltage of CR and DIR is the above-mentioned high voltage vp.
p is switched to a relatively high power supply voltage Vcc and supplied.

Furthermore, when the chip enable signal σ1 is at low level,
When the output enable signal CI is at a low level, the program signal "σ" is at a high level, and VPP is a low voltage for reading (same level as Vcc), the read mode is entered, and the inverted signal 71 of the internal timing signals ce, oe, and we is set. is raised to a high level.

The common data line CD is further provided with a read circuit including a sense amplifier SA, which will be described next, and a data output buffer DOB. That is, the common data line CD
is a gate-grounded N-channel amplification MOSFET.
Coupled to the source of QI 1. This amplification MOSFET
The output voltage of the inverter circuit N1 receiving the voltage of the common data line CD is supplied as a bias voltage to the gate of QI 1 in order to perform a level limiter operation for the common data line CD and the selected data line. Thereby, even though there is a capacitance such as a stray capacitance that limits the signal change speed in the common data line CD, etc., it is possible to speed up the read operation. MO5FETQI for the above amplification
The drain output signal Vs of 1 is transmitted to the input terminal of a sense amplifier SA formed by a CMOS inverter circuit.

Data output buffer DOB is timing control circuit CTL
It is put into an operating state by an internal timing signal Oe supplied from the sense amplifier SA, and outputs the output signal of the sense amplifier SA to an external terminal DO.

In this embodiment, in order to enable a read operation up to a high power supply voltage Vcc, a P-channel type first load MOSFET QI2 is provided between the drain of the amplification MOSFET Qll and the power supply voltage Vcc. Further, a P-channel type second load MOSFETQ13 is provided in parallel with this MOSFETQ12. M.O.
By connecting the gate of SFETQI2 to the ground potential of the circuit, MOSFETQ12 is operated in a non-saturation region. On the other hand, the gate of MOSFETQI3 has P
Channel MO5FETQ14 and N channel M.

A divided voltage formed by a series circuit consisting of 5FETs Q15 to Q17 is supplied. This divided voltage is applied to the MOSFET
It is set at an appropriate level so that Q13 operates in the saturation region. Thereby, MOSFETQ13 operates as a constant current source. In addition, the MO5FE of the voltage divider circuit
The above timing control circuit CT is connected to the gate of TQI 7.
An internal timing signal ce supplied from L is supplied. This prevents meaningless direct current from being consumed in the voltage divider circuit in the chip non-selected state.

Next, an example of a read operation in the EPROM of this embodiment will be explained.

The memory cells selected by address decoders X-DCR and Y-DCR are made to have a threshold voltage higher or lower than the word line selection level according to write data. During a read operation of a memory cell, if the selected memory cell has a higher threshold voltage (logic "0") than the word line selection level, the output voltage Va of the first stage amplifier circuit is
13 operates as a constant current source, its conductance is small, and it is mainly connected to MOSFETQ12 and amplification MOS.
FETQI 1. It is determined according to the conductance ratio of Y-gate MOSFET and memory cell Q1. When the selection level of the word line is raised higher than the relatively high threshold voltage as the power supply voltage Vcc increases, the memory cell Q1 is turned on. At this time, the current flowing through the memory cell Q1 is caused by the load MO serving as the constant current source.
Also supplied by SFETQI 3. This limits the increase in the current flowing through the load MOSFET QI2, or in other words, the increase in the conductance of the load MOSFETQ12, which compensates for the drop in the high-level output voltage vO, as shown by the dotted line in Figure 3. be done.

As described above, even if the conductance of the load MOSFET QI 2 is made relatively small, it is possible to compensate for the drop in the high-level output voltage vo due to the rise in the power supply voltage Vcc.

This acts to improve read level margin from memory cells designed to have relatively low threshold voltages.

That is, since the conductance of the load MOSFET QI 2 can be made relatively small, if the selected memory cell has a low threshold voltage compared to the word line selection level, the load MOSFET QI 2 can be made relatively small compared to the conductance of the selected memory cell.
Since the conductance of O3FIETQ12 can be made sufficiently small, the low level output voltage v1 is equal to the power supply voltage Vc.
The low level remains almost constant as c increases.

As shown in the above embodiment, this invention can be applied to FAMO
When applied to an EPROM using S transistors as memory cells, the following effects can be obtained. That is, (1) A first load MOSFET that supplies a read current to a selected memory cell, and an appropriate bias voltage applied to its gate in parallel with this first load MOSFET. a second load MOS that operates in the saturation m region and supplies part of the read current to the memory cell;
By providing the FET, it is possible to compensate for the drop in high-level output voltage due to an increase in the power supply voltage Vcc, and to reduce the low-level output in the read operation of a memory cell with a relatively low threshold voltage (logic "L"). A rise in voltage can be prevented. This provides the effect of ensuring a read low level margin while increasing the operating upper limit voltage.

(2) Paragraph (1) above enables writing and reading (verification) at a high power supply voltage;
The effect is that efficient write operations can be performed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, any circuit may be used to form the bias voltage for operating the load MOSFET Q13 in the saturation region. The sense amplifier SA may utilize a differential circuit or the like that receives a reference voltage that changes as the power supply voltage increases, such as the logic threshold voltage of a CMOS inverter circuit.

In the above explanation, the invention made by the present inventor was mainly applied to a reading circuit of an EPROM using FAMO3 as a memory cell, which is the field of application in which the invention was made, but the invention is not limited to this, and for example, The present invention can also be applied to semiconductor memory devices such as mask ROMs and EEFROMs using memory elements such as MNOS (metal nitride oxide semiconductor). The present invention is applicable to at least a semiconductor memory device using a memory element having a relatively high or low threshold voltage according to stored information.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, by applying an appropriate bias voltage to the gates of the first load MOSFET that supplies read current to the selected memory cell and the first load MOSFET, the first load MOSFET operates in the saturation region of its characteristics. However, by providing a second load MOSFET that supplies part of the read current to the memory cell, it is possible to increase the upper limit of operation voltage and secure a margin for the low-level read signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an EFROM memory array and its peripheral circuit to which the present invention is applied; FIG. 2 is a circuit diagram showing a readout circuit including a sense amplifier in a conventional EPROM; The figure is a voltage characteristic diagram of the read voltage Vs with respect to the power supply voltage Vcc in the EFROM of FIGS. 1 and 2. XADB-DCR...X address buffer/decoder, YADB-DCR...Y address buffer/decoder, YG...Y gate, M-ARY...memory array, SA...sense amplifier, DIB...data input Cover sofa, DOB...Dear cover sofa, CTL...timing control circuit. Q1~Q6...FAMOS memory cell, Q7~Q9...
Qll・Q15~Q17...N channel MOSFE
T, Ql 2~Q14...P channel MOSFET
, Ql O...Depression type N-channel MO
SFET, Nl...Inverter circuit. Figure 1 “ρ Figure 2 Figure 3

Claims (1)

[Claims] 1. Storage elements are arranged in a matrix to have a threshold voltage higher or lower than the selected level of the word line coupled to the gate according to storage information. a common data line coupled to the data line of the memory array via a column selection circuit; a source thereof coupled to the common data line;
A common gate amplifying MOSFET whose drain is provided with a first load MOSFET that operates in a non-saturation region and a second load MOSFET that operates in a saturation region.
A semiconductor memory device comprising: ET. 2. The memory elements constituting the memory array are FAMO
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an S transistor.