JPS62192495U - - Google Patents
Info
- Publication number
- JPS62192495U JPS62192495U JP7689186U JP7689186U JPS62192495U JP S62192495 U JPS62192495 U JP S62192495U JP 7689186 U JP7689186 U JP 7689186U JP 7689186 U JP7689186 U JP 7689186U JP S62192495 U JPS62192495 U JP S62192495U
- Authority
- JP
- Japan
- Prior art keywords
- down counter
- comparator
- detection circuit
- physical quantity
- clock input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000007423 decrease Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の基本構成を示すブ
ロツク図、第２図はガスクロマトグラフに適用し
た場合の具体的構成例を示す回路図、第３図はク
ロツク制御回路の他の構成例を示す回路図である
。
１……検出回路、２……比較器、３……アツプ
ダウンカウンタ、４……デイジタル―アナログ変
換器、５……クロツク制御回路。
Figure 1 is a block diagram showing the basic configuration of one embodiment of the present invention, Figure 2 is a circuit diagram showing a specific example of the configuration when applied to a gas chromatograph, and Figure 3 is another example of the configuration of the clock control circuit. FIG. 1...Detection circuit, 2...Comparator, 3...Up-down counter, 4...Digital-to-analog converter, 5...Clock control circuit.
Claims (1)
し被測定物理量に対応した電気信号を送出する検
出回路と、この検出回路の出力値を零値と比較す
る比較器と、この比較器の出力に応じてクロツク
入力の計数値を増減するアツプダウンカウンタと
、このカウンタの計数値をアナログ信号に変換し
、変換素子の零調整用信号として検出回路に送出
するデイジタル―アナログ変換器と、上記アツプ
ダウンカウンタのフルカウントを検知して当該ア
ツプダウンカウンタへのクロツク入力を禁止する
クロツク制御回路とを備えたことを特徴とするフ
イールド装置。 A detection circuit that has a conversion element that converts a predetermined physical quantity into an electrical quantity and sends out an electrical signal corresponding to the physical quantity to be measured, a comparator that compares the output value of this detection circuit with a zero value, and an output of this comparator. an up-down counter that increases or decreases the counted value of the clock input in accordance with 1. A field device comprising: a clock control circuit that detects a full count of a down counter and prohibits clock input to the up/down counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7689186U JPS62192495U (en) | 1986-05-23 | 1986-05-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7689186U JPS62192495U (en) | 1986-05-23 | 1986-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62192495U true JPS62192495U (en) | 1987-12-07 |
Family
ID=30924388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7689186U Pending JPS62192495U (en) | 1986-05-23 | 1986-05-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62192495U (en) |
-
1986
- 1986-05-23 JP JP7689186U patent/JPS62192495U/ja active Pending