JPS6214503U - - Google Patents
Info
- Publication number
- JPS6214503U JPS6214503U JP10169685U JP10169685U JPS6214503U JP S6214503 U JPS6214503 U JP S6214503U JP 10169685 U JP10169685 U JP 10169685U JP 10169685 U JP10169685 U JP 10169685U JP S6214503 U JPS6214503 U JP S6214503U
- Authority
- JP
- Japan
- Prior art keywords
- analog signal
- analog
- state
- switch
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Description
第１図は本考案の構成図、第２図は本考案の一
実施例としての入力信号の処理装置を示す回路図
、第３図は第２図の装置におけるＡ／Ｄ変換器の
入力電圧Ｖと温度Ｔとの関係を示す図、第４図は
第２図の装置におけるマイクロコンピユータの処
理を表わすフローチヤート、第５図は第２図の装
置の変形例を示す回路図、第６図は第５図の装置
におけるＡ／Ｄ変換器の入力電圧Ｖと温度Ｔとの
関係を示す図、第７図は第５図の装置におけるマ
イクロコンピユータの処理を表わすフローチヤー
ト、である。
１０…サーミスタ、１１，１２…スイツチ、２
０…制御ユニツト、２１，２２…コネクタ（端子
）、２３…分圧用抵抗、２５…Ａ／Ｄ変換器、３
０…マイクロコンピユータ。
Fig. 1 is a block diagram of the present invention, Fig. 2 is a circuit diagram showing an input signal processing device as an embodiment of the present invention, and Fig. 3 is the input voltage of the A/D converter in the device of Fig. 2. 4 is a flowchart showing the processing of the microcomputer in the device shown in FIG. 2, FIG. 5 is a circuit diagram showing a modification of the device shown in FIG. 2, and FIG. 6 is a diagram showing the relationship between V and temperature T. 7 is a diagram showing the relationship between the input voltage V of the A/D converter and the temperature T in the device shown in FIG. 5, and FIG. 7 is a flowchart showing the processing of the microcomputer in the device shown in FIG. 10...Thermistor, 11,12...Switch, 2
0...Control unit, 21, 22...Connector (terminal), 23...Resistance for voltage division, 25...A/D converter, 3
0...Microcomputer.
Claims (1)
に設けられ、所定の外的条件においてそのオンオ
フが切り換わる少なくとも１個のスイツチ、 前記アナログ信号をデイジタル変換するアナロ
グ・デイジタル変換器、 該アナログ・デイジタル変換器からのデイジタ
ル変換値を、前記スイツチがオン状態およびオフ
状態にある場合の該デイジタル変換値のそれぞれ
の値の中間に設定された所定値と比較する手段、
および、 該比較の結果に基づいて前記スイツチのオンオ
フ状態の判別と前記デイジタル化されたアナログ
信号の検出を行う手段、 を具備することを特徴とする入力信号の処理装置
。[Claims for Utility Model Registration] Means for providing an analog signal; at least one switch provided in a signal input circuit common to the analog signal providing means and turned on and off under predetermined external conditions; the analog signal; an analog-to-digital converter that digitally converts the digital conversion value from the analog-to-digital converter to a predetermined value set between the respective values of the digital conversion value when the switch is in the on state and the off state. means of comparing with the value,
and means for determining the on/off state of the switch and detecting the digitized analog signal based on the result of the comparison.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10169685U JPS6214503U (en) | 1985-07-05 | 1985-07-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10169685U JPS6214503U (en) | 1985-07-05 | 1985-07-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6214503U true JPS6214503U (en) | 1987-01-28 |
Family
ID=30972661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10169685U Pending JPS6214503U (en) | 1985-07-05 | 1985-07-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214503U (en) |
-
1985
- 1985-07-05 JP JP10169685U patent/JPS6214503U/ja active Pending