JPS62191958A - Controller for direct memory access - Google Patents

Abstract

PURPOSE:To execute continuously a direct memory access to an address space accompanying the change of higher order address information by comparing the successively stepping address information sent to an external memory device with the prescribed address information set beforehand and sending coincident information to the external part. CONSTITUTION:A DMA controller 1 has an address counter 2 to store the lower order 16 bits of a transferring starting address and step, thereafter, only at the number of times of transfer, an adding part to step an address counter 2 besides a register to store the number of times of the transfer, and a higher order 8 bit (b) of the address counter 2 is transferred to a buffer 3 and outputted as an immediate order 8 bit (d) of the address information to an external part. On the other hand, a lower order 8 bit (a) of the address counter 2 is transferred to a buffer 4 and outputted as the lower order 8 bit of the address information to the external part. Further, the DMA controller has an all 1 detecting circuit 5 as a comparing means, and the detecting circuit 5, when the higher order 8 bit (b) and the lower order 8 bit (a) come to be all 1, outputs a carry (e) to the external part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a controller for direct memory access, and in particular, the present invention relates to a controller for direct memory access, and in particular, it is possible to expand the controllable address space of the controller, and even when the address space of the transfer destination is [Prior art] In microcomputer systems, direct memory transfers data directly from input/output IT to a memory device without going through a microprocessor. access(
Some microcomputer systems employ a DMA (hereinafter referred to as DMA) method.In a microcomputer system that fully adopts such a DMA method, the DMA controller controls all data transfer, but the amount of data processed by the microcomputer system is limited. Once the address space is expanded,
There are cases in which an address space is set beyond the address space that can be controlled by a DMA controller.One example is a microcomputer system equipped with a DMA controller address expansion circuit, as shown in Figures 4 and 5. In Figure 4, 201.202,
203, 204, 205゜206U microprocessor, memory device, input/output device [(hereinafter referred to as Ilo), 1
The 6-bit address space DMA controller, 4-bit latch circuit, and 8-bit latch circuit are each shown, and 20-bit address nodes (AO to A19) and 8-bit data nodes are placed at 211, 212, and 213. Work control bus (memory read, memory write, I1
0 read, 10 write) are shown. Kof
'To LK, 214, 215, 216, 217°21
8.219 is a hold response signal, a hold fee request signal, l
) MA request decoding, DMA address input number 11, DM
A address strobe 1 signal, DMA response (g signal each signal i' (r indicates 0 where memory f21i1202
Address space 30000 to 33 FFFH l10
The operation of performing DMA transfer from 203 will be explained with full reference to the timing chart of FIG. Memory device 2
02fl Although it is a 20-bit address space, DM
Since the A controller 204 can only control a 16-bit address space, the microprocessor supplies the upper 4 bits (for example, 3H) of the transfer start address to the 4-bit latch circuit 205 in advance before starting a DMA transfer, and then the DMA controller 204 The lower 16 bits of the transfer start address and the number of transfers? Send, what are the lower 16 bits and the number of transfers? rDMA controller 204. Here, from l10203 to DMA controller 2
The DMA request signal 1fij 216 for 04 becomes high level (time signal), and based on the DMA request signal, the PDMA controller 204 shifts to the high level of the ninth hold request signal -215t, which determines the use of the bus ( time,
). When the microprocessor 201 shifts the hold response signal line 214' to high level in response to the hold request No. 1g (time ts), the %DMA controller 20
4, the DMA address enable 1g line 217 and the DMA address strobe [no. 8
218, all of which are shifted to high level, and the lower 8 bits of the transfer start address? The transfer start address is sent to the address bus 211 and the middle 8-bit digitizer bus 212, respectively. The 8-bit latch circuit 206 latches the middle 8 bits of the transfer start address based on the transition of the DMA address strobe polarization line 207 to high level (time t4).
4-bit latch circuit 205 and 8-bit latch circuit 206
means the upper 4 bits, middle 8 bits, and '? of the transfer start address. n based on DMA address enable No. 16.
Send to address bus 2]1. Therefore, the data transfer destination of the memory 1 Jit 202 is specified together with the lower 8 bits sent from the %DMA controller 204 to the address bus 211. After this, the DMA controller 204
The MA response signal line 219 is shifted to low level (time signal), and the control bus 2 of the microprocessor 201 is
13? When the I10 read decoding and memory write signals are respectively shifted to low level through I10203, a memo! The data is transferred to the J device 202 (time t6) and written to the address specified by the 20-bit address signal (time t7). In this way, the DMA controller 204 advances the lower 8 bits of the address by seven steps while
When controlling the MA transfer and a carry from the lower 8 bits occurs, the MA controller 204 outputs the DMA address strobe decoding again, and the data bus? The 8-bit latch circuit 206 is rewritten through the 8-bit latch circuit 206.

In this way, VO20 is transferred for the preset number of transfers.
When data is transferred from 3 to the memory device 202,
The DMA transfer is complete.

[Problems that the invention attempts to solve]

However, in the case of a nine-microcomputer system using the conventional 4-bit latch circuit 205, the DMA
Transfer destination address is 3FFOOH to 40 OFF'H
When the upper 4 bits of the address change, such as an address, the DMA transfer 13FF'oo to 3FFFF) i and 4
0000 to 40OFF) divided into two transfers with i,
In addition, the microprocessor 201 had to rewrite 4HK from gi3n in the memory of the 4-bit latch circuit 205, which caused the problem that the software of the computer system became complicated.

[Means for Solving the Problems 1. Effects and Effects] The direct memory access controller according to the present invention transfers data from the transfer start address to an external storage device based on the transfer start address and the number of transfers supplied from the outside. Address information that is sequentially incremented by the number of times is supplied to all external storage devices, and all direct memory accesses to the external storage devices are controlled. The sequential address information sent to the external storage device is compared with predetermined address information set in advance by a comparing means, and when they match, matching information is sent to the outside. Therefore, when expanding the address space that can be specified by a direct memory access controller, all matching information sent from the direct memory access controller is used as carry information, and upper address information that is incremented by the carry information is added. In particular, it has the advantage that expansion can be easily carried out, and direct memory access to the address space can be carried out continuously without changing the upper address information. 1 is a block diagram showing one embodiment of the invention,
In addition to the register that stores the number of transfers, the DMA controller 1 has an address counter 2 that stores all of the lower 16 bits of the transfer start address and then increments by the number of transfers, and an address counter 2 that increments the address counter 2 by seven steps. , the upper 8 bits of the address counter 2) are transferred to the bH buffer 3, and output to the outside as the middle 8 bits d of address information. On the other hand, the lower 8 bits of the address counter 2 are transferred to the aid buffer 4 and output to the outside as the lower 8 bits of address information.

The DMA controller of this embodiment further includes an all-1 detection circuit 5 as a comparison means, and this detection circuit 5
When the upper 8 bits)b and the lower 8 bits a are all "1", the carry e'z is output to the outside. Note that in this embodiment, since the all-1 detection circuit 5 is used as a comparison means, the address counter 2 is rl, 1 .・・・・・・、
1. It becomes IJ and a carry e occurs, but the values to be compared with the address color/ri2 are not limited to all 1s.

[1 It goes without saying that the DMA controller 1 shown in FIG. 1 outputs control signals such as a DMA address strobe signal.Next, a microfumpiator system using the DMA controller 1 shown in FIG. 1 is shown in FIG. 0. Note that in FIG. 2, the same reference numerals as those in the conventional example shown in FIG. Second
In the figure, 6 indicates a 4-bit counter, and the counter 6 is set to the upper 4 bits of the transfer start address in the microprocessor 201 prior to the start of HDDMA transfer, and every time carry e is output from the DMA controller 1. advance to

Next, the DMA transfer address is 3FFOO~400FFH
The case will be explained below.

As in the case of performing seven DMA transfers to the memory 30000 to 33FFFH, the microprocessor 201
The upper 4 transfer start addresses are displayed in EX 4-bit counter 6.
bit 3H% DMA controller 1 lower 16 bits)F
FOOH% Number of transfers 40OFF-3FFOOH=
Set all IFFH settings.

As in the nine microcomputer systems described above using the conventional DMA controller, a DMA cycle is initiated f'L and a DMA transfer is performed.

When the DMA transfer address reaches address 3FFFFH, carry e is output as shown in FIG. And that D
When the MA cycle is completed and the next DMA cycle begins, carry e becomes inactive. The 4-bit counter 6 is counted up at the trailing edge of this carry (time kn). Then the next cycle is 131tKU4
The output of bit counter 6 changes from 3H to 4H, and the DMA
The address is 40000I (and continues to be address 4)
DMA transfer is performed at 0OFFH2.

As shown above, when using one DMA controller of the present invention, the DMA transfer address is 3FFOOH to 4FFOOH.
Top 4 results of address expansion like 0OFFH
Even if the bits increase from 3H to 4H during DMA transfer, the same procedure as in the case where the upper 4 bits do not increase during DMA transfer can be performed without interrupting the entire MA transfer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. Figure 2 is a block diagram of the combinator system including the DMA controller in Figure 1, Figure 3 is a timing chart of the system in Figure 2, Figure 4 is a block diagram showing the entire conventional computer system, and Figure 5 is a block diagram of the combinator system including the DMA controller in Figure 1. 5 is a timing chart 1 of the system of FIG. 4. FIG. 1...DMA controller, 5...Comparison means. e...-Number information. Agent: Susumu Uchihara, Patent Attorney
1 figure

Claims (1)

[Claims] In a direct memory access controller that sequentially increments from a transfer start address by the number of transfers and supplies address information to an external storage device based on a transfer start address and a number of transfers supplied from the outside, an address supplied to the external storage device. For direct memory access, further comprising comparison means for sequentially comparing the information with predetermined address information set in advance and transmitting matching information to the outside when the address information supplied to the external storage device matches the predetermined address information. controller.