JPS62190846A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a high density, high speed and low power consumption semiconductor device having small mutual action between elements, in which its parasitic capacity is reduced by forming a mask for an ion implantation on a portion to become the transistor region of the surface of a semiconductor substrate, implanting oxygen or nitrogen ions, and heat treating it. CONSTITUTION:Since the lateral spread of oxygen ions is necessary in a later heat treatment, an oxygen ion-rich implanted layer 4 is formed by increasing the implanting amount in an SIMOX method. The upper surface of the layer 4 is anisotropically etched to separate between elements to form a hole 5. A silicon oxide film (II) 6 and a silicon nitride film (II) 7 are so formed on the entire semiconductor substrate as not to allow the excessively implanted ions in the heat treating step from escaping at heat treating time. Then, a heat treatment of 1,100 deg.C or higher is performed to form a buried insulating layer 8 of a silicon oxide film on a region in which oxygen ions are diffused from the oxygen ion-rich implanted layer. A separation between elements is completed by the parts of the films 6 and 7 by flattening.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that enables high density, high speed, and low power consumption.

2. Description of the Related Art Semiconductor integrated circuits are becoming more dense, faster, and consume less power, but one problem with such devices is parasitic capacitance. For example, there is a parasitic capacitance that occurs between the collector and the substrate in a bipolar element, and a parasitic capacitance that occurs between the source/drain and the substrate in an MO8 element. If this parasitic capacitance can be reduced, it is possible to form a semiconductor element with higher speed and lower power consumption. on the other hand,
As density increases, problems such as adverse effects of interaction between elements are also occurring, and many attempts have been made to solve these problems by separating each element from the semiconductor substrate with an insulator.

For example, SOS (SiliconOn 5
A method called SI appphire) is used, and a method called SI method, in which a high concentration oxygen ion implantation region is provided in a silicon substrate and a buried oxide film formed by high temperature annealing is used to separate the surface silicon layer and the substrate silicon, is used as an insulating film. M.O.
X (Separation by Implant
There is a method called ed()cygen).

FIG. 2 is a sectional view showing an example of the manufacturing process of a semiconductor device by the SIMOX method disclosed in Japanese Patent Application Laid-Open No. 66-62333, and the specific manufacturing process will be described below. First, prior to device formation, a silicon oxide film 11 with a thickness of 1 μm or more is formed on the surface of the SL substrate 1o by the CVD method.Next, a resist film 12 with a window is provided in the memory cell array area by lithography technology. A window is opened in the oxide film 11 using C0. At this time, the opening end of the oxide film 11 is sloped by, for example, about 460 degrees as shown in the figure. This slope can be obtained by, for example, diffusing phosphorus or the like into the surface of the oxide film 11, and setting a difference in the etching rate in the thickness direction of the oxide film 11 with respect to an NH4F solution as an etching solution. .

Oxygen ions are implanted using the oxide film 11 with the opening end sloped as an ion implantation mask.The ion implantation conditions are, for example, 150 KeV.

It is assumed to be 1×10 18 crII-2. As a result, the oxide film 1
In the part where there is no oxide film 11, the depth is about 38oO, and the oxide film 11
An ion-implanted layer is formed at the end of the opening, the ion implantation layer becoming shallower as the thickness changes. And after this, 11oo''C
By performing the above heat treatment, the ion-implanted layer is converted into a buried insulating layer 13 with a thickness of about 20 mm, thereby obtaining a structure in which the substrate 102 of the memory cell section is reliably separated from the substrate 101 of the peripheral circuit section. Various problems have been pointed out with these methods (for example, Y, N15hiand H
, Hara @Physics and Devi
ces Technology of 5ilicon
on 5apphire” Proceedings on 9th Conference on Lid State Devices 27
f 9th Conference on 5olid
5tate Devices27) (197 completed) and M
, 1 , Kim et, al @5urfacere
Storation of oxygen Impla
nted 5illion' Journal Applied Physics (J.

Appl, Phys) Vol 54 No, 4199
1 (1983)).

Problems to be Solved by the Invention The SO8 method has the excellent feature of reducing parasitic capacitance, but (1) it is expensive because it uses single-crystal sapphire as the substrate; There are drawbacks such as distortion and crystal defects in the silicon vapor phase grown layer during cooling after vapor phase growth due to differences in thermal expansion coefficients.

In addition, in the SIMOX method, the separated surface silicon layer is made of a single-crystal bulk substrate, but because high-density and high-energy oxygen ions pass through it, crystal defects may be generated or, depending on the implantation amount and energy, 1o AtomA
Oxygen ions with a higher concentration remain and are distributed near the surface,
There is a problem with its crystallinity, and although it is being improved, S
Due to these drawbacks, the OS-8 IMOX method has not been widely used to date.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a mask for ion implantation on the surface of the semiconductor substrate in the area that will become the transistor region, implants oxygen or nitrogen ions, and then By utilizing the lateral spread of ions during heat treatment, a buried insulator region is formed while eliminating the effects of crystal defects and residual ions in the transistor region.

By using the above-mentioned methods, a single crystal bulk substrate with good crystallinity through which oxygen or nitrogen ions do not pass can be used as a transistor region, and the transistor region can be separated from the bulk substrate by an insulating layer to reduce parasitic capacitance. - It is possible to reduce interaction between elements and manufacture semiconductor integrated circuits with high density, high speed, and low power consumption.

Embodiment FIG. 1 is a process sectional view showing an embodiment of the present invention. In Figure 1a, 1 is a P-type silicon 1oo substrate, and the specific resistance is 0.5.
~1Ω·α, 2 is a thermal oxide film (I), and 3 is an oxidation-resistant ion implantation mask material, such as a silicon nitride film σ). The thermal oxide film and the silicon nitride film cover the portion that will become the transistor region (width of 0.26 μm in this case) and prevent implanted ions from passing through the transistor region. The oxygen ion implantation conditions for the implanted ions are, for example, 15oKe.
V.

5 x 1018 cm-1. Since it is necessary for the oxygen ions to spread laterally in the subsequent heat treatment, the amount of implantation is greater than that in the SIMOX method described above, depending on the pattern, to form an oxygen-rich ion implantation layer. Since it is necessary to form an oxygen-rich ion implantation layer, in order to prevent heat diffusion to unnecessary areas during implantation (diffusion to damaged areas in the ion passage area is large at room temperature), implantation is performed at liquid He temperature. Alternatively, it is carried out at the temperature of liquid He. As a result, an ion-implanted layer 4 is formed to a depth of about 4,000 mm, and anisotropic etching is performed to the top of the ion-implanted layer to increase the lateral diffusion distance of oxygen and to isolate devices, and an opening 5 is formed. form (Fig. 1b). Reduced pressure CV to prevent excessively implanted ions from escaping during heat treatment.
A silicon oxide film (■) 6 and a silicon nitride film (■) 7 are formed on the entire surface of the semiconductor substrate by the D or ECR method (FIG. 1C).

Next, by performing heat treatment at 1100''C or more, a buried insulating layer 8 of silicon oxide film is formed by reaction between the implanted ions and silicon in the region where oxygen ions/ions have been diffused from the oxygen-rich ion implanted layer. (FIG. 1d). In this way, a transistor formation region 11 consisting of a part of the substrate 1 is formed. After that, a silicon oxide film 2 covering the upper surface of the transistor formation region 11 formed separately from the substrate 1 is formed. .6 and the silicon nitride films 3 and 7 are removed and planarized by plasma etching, and isolation between elements is completed using a part of the silicon oxide film 6 and a part 9 of the silicon nitride film 7 (FIG. 1e). Although not described in detail here, it is also possible to reduce the ion implantation energy by reversing the order of the ion implantation step and the anisotropic etching step.The subsequent steps will be omitted, but can be done using a known method. forming a semiconductor device;

As described in detail, according to the present invention, a semiconductor substrate with good crystallinity can be used in a transistor region without deteriorating its crystallinity, and a high-density structure with reduced parasitic capacitance and small interaction between elements can be realized.・High-speed, low-power consumption semiconductor devices can be formed. This is a manufacturing technology for semiconductor devices that has extremely high industrial value and has characteristics that will be desired in the future.

[Brief explanation of drawings]

FIGS. 1a-e are process cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2a-e are
e is a process sectional view for explaining the conventional SIMOX method. 1...P-type silicon substrate, 2 and 6...
・Silicon oxide film, 3 and 7... Silicon nitride film, 4... Ion implantation layer, 6... Inter-element isolation opening, 8... Buried Insulating layer, 9...
. . . Inter-element isolation insulator, 11 . . . Transistor formation region.

Claims (4)

[Claims] (1) A step of providing a mask material for ion implantation on the portion of the surface of the semiconductor substrate that will become the transistor region, a step of implanting oxygen or nitrogen ions into the semiconductor substrate, and a heat treatment to form a buried insulating layer to the bottom of the transistor region. A method for manufacturing a semiconductor device, comprising the steps of: (2) After implanting ions using the ion implantation resistant mask material as a mask, an opening is formed in the semiconductor substrate using the ion implantation resistant mask material as a mask, and an oxidation resistant or nitriding resistant film is formed on the entire surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 1. (3) After forming an opening in the semiconductor substrate using the ion implantation resistant mask material as a mask and forming an oxidation resistant or nitriding resistant film on the entire surface of the semiconductor substrate, ions are implanted using the ion implantation resistant mask material as a mask. A method for manufacturing a semiconductor device according to claim 1. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is cooled to liquid nitrogen temperature or liquid helium temperature when ions are implanted using an ion implantation-resistant mask as a mask.