JPS62189981A - Driving circuit of ultrasonic motor - Google Patents

Abstract

PURPOSE:To decrease the probability of variation of the duty ratio of an applied pulse and prevent uneven rotation by intermittently conducting a feedback control for fixing a phase difference of a signal to a driving electrode. CONSTITUTION:A pulse from VCO5 is frequency-divided by a frequency divider circuit 19 and applied to an electrode 1-1 through an amplifier 7 and a coil 9. From a multiplexer 21, an output pulse of a register 20, that is, a pulse 90 deg. deviated from the pulse of the frequency divider circuit 19 is applied to an electrode 1-2 through an amplifier 8 and a coil 11. In case of a 90 deg. phase difference control of voltage applied to the electrodes 1-1, 1-2, an output of a comparator 24 is transmitted to a counter 22 through a thinning circuit 23. According to an output of this counter 22, an output of a shift register 20 is selected by the multiplexer 21 and outputted to the amplifier 8.

Description

[Detailed Description of the Invention] <Industry> Second Field of Application The present invention generates progressive vibration waves using an electro-mechanical energy conversion element such as an electrostrictive element or a magnetostrictive element, and drives a rotor with the vibration waves. This invention relates to a drive circuit for an ultrasonic motor.

<Prior art> In the ultrasonic motor (hereinafter referred to as SSM),
Frequency voltages of different phases are applied to electrostrictive elements placed at different positions on the stator to generate progressive vibration waves on the stator surface, and the vibration waves cause a moving body to come into frictional contact with the stator. It's driving. When applying the above-mentioned frequency voltage to the electrostrictive element of the SSM, it is necessary to arrange drive electrodes and apply frequency voltages of different phases (90° phase difference) to each electrode. Even if each supply signal at the signal source that supplies the frequency voltage to the
°There is no guarantee that phase-shifted voltages will be applied.

Figure 1 shows the drive electrode 1-1 for the stator I''2 of the SSM.
,1. -2 and the common electrode ]-4; FIG. 2 shows a circuit for applying voltage to the electrodes 1-1 and 1-2; As is clear from Fig. 2 (SS
M drive electrode 1-1. , ], , -, , -2, the two frequency voltages are applied to the electrodes 1 to 1 via the amplifier 7 and the coil 1o, and the amplifier 8 and the coil 21 are A frequency voltage is applied to the electrodes 1-2 through the electrodes 1-2. Here, even if the frequency voltages supplied to the amplifier 7.8 have a phase difference of 90' from each other, the amplifier 7.8, the coil 10. I], electrode l-1° electrode 1
-2. Electrode 1 due to variations in electrical characteristics of electrodes 1-4, etc.
There is no guarantee that a frequency voltage with a phase difference of 90' will be applied to -1 and 1-2. For this reason, it is conceivable to detect the voltage waveforms of the electrodes], -1 and 1-2 and perform feedback control so that the relationship between these positions becomes 90[deg.].

According to this method, a 900 phase difference signal can be applied to the electrodes J-1 and 1-2, but in reality, the electrodes ]-1 and 1
The phase difference between the voltages applied to -2 and 9oo causes a signal that goes back and forth around 9oo to be repeatedly applied, which may cause uneven rotation of the SSM.

That is, although ideally the relationship between the stator and the movable body that makes frictional contact is uniform, as a practical matter, the positional relationship between the movable body and the stator differs depending on the rotational position. Therefore, electrode 1-
] and the electrical characteristics between electrode 1-4 and electrode ]-2 and electrode 1-
The electrical characteristics between /I will change depending on the rotational position of the moving body. In this way, since the characteristics between electrode 1-1 and electrode 1-4 and the characteristics between electrode 1-2 and electrode 1-4 differ depending on the position of the moving body with respect to the stator during rotation, the feedback control described in -1. According to this method, the phase difference relationship is always adjusted according to the displacement of the moving body.

FIG. 3 is a waveform diagram showing the phase difference relationship between the frequency voltages applied to electrodes 1, -1 and 1-2.

Now, it is assumed that amplifiers 7 and 8 and coils IO and 11 have the same electrical characteristics. In this case, the rotational position of the moving body with respect to the stator is electrodes 1 to 1 and 1-4, electrode]-2 and 1-4.
When the electrodes are at the same position due to the electrical characteristics of the electrodes]-1, 1- 2 are applied with frequency voltages having a phase difference of 90°. On the other hand, when the rotational position of the moving body is at a position where the electrical characteristics between electrodes 1-1 and 1-4 are different from those between electrodes 1-2 and 1-4, the input signal to amplifiers 7 and 8 is Figure 3 (a)
.

Even if the signals of the relationship ■ to ■ in (b) are applied, the electrode 1-
Frequency voltages having a phase difference of 900 will not be applied to 1 and 1-2. Therefore, in this case, if the Hokkaido feedback control is performed, the phase difference of the signal input to the amplifier 7.8 is changed by 900 degrees, and as a result, the signal applied to the electrodes 1-1 and 1-2 during this period is The frequency voltage is controlled to shift to a 90° phase difference.

That is, ``electrodes]-1 and 1-4 depending on the position of the moving body,
Electrodes during the period (■ ~ in Figure 3) when the electrical characteristics between electrodes 1-2 and 1-4 were different] -1 and 1-
The feedback control described above is performed in accordance with the deviation of the phase difference between the two with respect to 90°. Now, period 2 (■～■ in Figure 3)
By advancing the phase of the voltage applied to the amplifier 8 with respect to the voltage applied to the amplifier 7 by ΔT with respect to the normal 900 phase difference, the frequency voltage between electrodes 1-1 and 1-2 is set to 90°. Assuming that the phase difference relationship can be maintained, the voltage applied to the amplifier 7°8 during this period (■ to ■ in Figure 3) is as shown in (a) in Figure 3.
The feedback control described above is performed so that the state at time 0 to 0 in (b) is achieved. -JZ The duty and period of the signal applied to the amplifier 8 during periods ■ to ■ are 50% and 'r, whereas the duty and period during periods ■ to ■ are 'r. The above feedback control was performed in this way. In the case of 90', when performing phase difference control, signals having different duty and period as described above depending on the position of the moving body are repeatedly supplied to the amplifier 8 from time to time by the rotation of the moving body.
-2 is applied with signals having different levels and frequencies from time to time, which causes uneven rotation of the SSM.

<Purpose> The present invention has been made in view of the above-mentioned matters, and includes an electrical-mechanical Nerky conversion element disposed on a first structure, and frequency voltages having mutually different phases are applied to the conversion element to generate a progressive vibration wave. In a drive circuit for an ultrasonic motor that generates a vibration wave and causes relative movement between a second structure and a first structure in contact with the first structure, the frequency voltage applied to the conversion element is A feedback control circuit that detects and performs feedback control to keep the phase difference between the frequency voltages constant, and a thinning circuit that intermittently performs feedback control operation by the feedback control circuit are installed. The present invention aims to provide a driving circuit for an ultrasonic motor that has less rotational unevenness than a circuit that performs phase difference control intermittently (by performing this phase difference control continuously).

-One Embodiment> FIG. 4 is a configuration diagram showing the electrode shape of the stator of the ultrasonic motor according to the present invention, and has the same configuration as the configuration shown in FIG. 1. Note that 1-3 indicates a monitor electrode for detecting the resonance state of the stator, and the common voltage is 1-4.
-1, ], -2, and 1-3 are connected to electrodes opposite to each other.

FIG. 5 is a circuit diagram showing an embodiment of a drive circuit for an ultrasonic motor (hereinafter referred to as SSM) according to the present invention.

In the figure, 1 is a stator on which an electrostrictive element is arranged;
1-], , ]1-2, ], -3 are electrodes shown in the fourth figure, 10°]] are coils, and 7 and 8 are amplifiers.

116.17 are electrodes 1-2, respectively. ]-1, and is a comparator that transforms the sine wave of the electrode into a 1-8 form and converts it into a logic level pulse. Further, 2 is a comparator that converts the output waveform (sine wave) of the monitor electrode into a logic 1 novel pulse. 12 is a face comparator 1 noter (phase comparison circuit) whose one input terminal is connected to the output of the comparator 2, and the input terminal of the other output is connected to the input terminal 18, for example, USP42.
9] No. 27, No. 1, etc., and its detailed explanation will be omitted, or it detects the phase difference of human input signals and generates an output when the phase difference exists.

The circuit diagram and manual output characteristics of the comparator 12 are as shown in FIGS. 6 and 7, and the input pulse (rising signal) to the input terminal R is earlier than the rising signal to the input terminal S. , the output i;t, Vcc (high level signal station - 1" H
It is called. ), and when a rising signal is input to the 1-input terminal S, the output becomes an open state (high impedance state).

Also, the input pulse (rising) to the input terminal S is input to the input terminal R.
If the rising signal is input before the rising signal, the output during the rising signal period will be at ground level (referred to as below low level).
becomes.

Further, the circuit is in an open state except when the output indicates H or L. Therefore, when the phase difference is zero, the output remains open.

4 is a low-pass filter that smoothes the output of the comparator 12. 5 is a voltage controlled oscillator (VCO) that outputs a signal with a duty ratio of 50% at a frequency corresponding to the input voltage.
Its input is connected to the output of the low-pass filter 4.

19 is a frequency dividing circuit that divides the output of the VCO 5 by 32, and the output of the frequency dividing circuit is sent to the electrodes via the amplifier 7 and the coil 10.
1. Further, the output of the frequency dividing circuit 19 is connected to the 1] input terminal of a 16-stage shift I register 20. The output of the VCO 5 is inputted to the clock terminal of the register 20 as a clock pulse. Frequency dividing circuit 19
Since the frequency of the VCO 5 is 32 times higher than the output pulse of the shift 1 register 20, the relationship between the D input to the register 20 and the clock pulse is also 32 times the frequency of the shift 1 register 20.
The output Q I-Q 16 is a pulse that is shifted (delayed) by 1.1.25° from 0° to 180' with respect to the D input signal. The oscillation frequency of the VCO5 is set to 32 times the resonant frequency of the SSM.

2I is a multiplexer that selects one of the outputs 01 to QI6 of the 1-no-sister 20 based on the output of the counter 22, and the output of the multiplexer 21 is sent to the electrodes 1-2 via the amplifier 8 and the coil 11. is applied to Reference numeral 25 denotes an 8-stage shift register, and the output of the comparator 17 is input to the input terminal of this register, and the output of the VCO5 is input to the clock input, so that from the output terminal Q8 I] A pulse delayed by 90° with respect to the input signal to the input terminal is output. That is, since the output pulse of the frequency dividing circuit 19 and the output pulse of the comparator 17 are pulses having the same phase relationship, the pulse is inputted as the D input, and the output pulse of the shift register 25 is inputted as the clock. Stage output Q
8 is a pulse delayed by 90° with respect to the D input signal, that is, the signal of electrode 1-1.

24 is a phase comparator, and the comparator 2
Figure 8 shows the block configuration and input/output characteristics of 4.

As shown in Figure 9, the pulse to the input terminal R is the pulse to the input terminal S.
If the pulse rises before the input terminal S
0UTI is kept low until the pulse to rises. Furthermore, if the pulse to the input terminal S rises earlier than the pulse to the input terminal R, 0UT2 remains low until the pulse to the input terminal R rises.

The input end S of the comparator 24 is connected to the output end of the comparator 16, and the input end R is connected to the register 25.
It is connected to the output terminal Q8 of.

” The pulse from the output Q8 of the register 25 is the waveform of the electrode 1-1 (the output of the comparator 17 (the 10th
The pulse delayed by 90° with respect to the pulse (Fig. 10 (a))
C)), which is input to the R input terminal of the comparator 24, and the electrode 1- to the S input terminal of the comparator 24.
A pulse with the same phase as the waveform of electrode 2 (output of comparator 16 (Fig. 10 (1))) is input. Therefore, if the waveforms of electrodes 1-1 and 1-2 are out of phase by 900, Since pulses of the same phase are input as the R and S inputs of 24, the comparator 24 (7) output O
U i” I, OUT T2 outputs both r−r. Also, as shown by the dotted line in Fig. 0 (l) (↑■ pole 1
-2 waveforms, i.e. comparator 16 pulses or electrode 1-
1 waveform, that is, when the phase relationship with respect to the pulse of the comparator 17 is within 900, the rising pulse to the S input terminal of the comparator 24 is earlier than the rising pulse to the R input terminal. Therefore, the comparator 24 sets the output terminal OU'F2 to L. Conversely, if the phase relationship between the pulses of the comparator 16 and the pulses of the comparator 17 is 90° or more, the output terminal 0UTI of the comparator 24 becomes 7.

24 is an up/down counter that performs one-step up and down operations in response to falling signals to the up input and town input terminals. The up input terminal of the counter 22 is connected to a comparator 24 via a thinning circuit 23, which will be described later.
Since the down input terminal is also connected to the output terminal OUTI through the thinning circuit 23, the phase relationship between the waveforms of electrodes], -] and 1-2 is within 90°. When this happens, the counter 22 counts up, and conversely, when it reaches 90° or more, it counts down. Output of the counter 22 (4 hits)
is connected to the multiplexer, and the multiplexer 21 is configured to select the output of the subsequent bit of the register 20 as the count value of the counter increases. These comparators 24, counters 22,
In the configuration of multiplexer 21, electrodes 1-1 and 1-2
When the phase relationship between the waveforms becomes within 90°, the counter 22 counts up and the output from the register 20 is selected, so that the waveform applied to the electrode 1-2 lags behind the electrode 1-1. The phase relationship of the waveforms 1-2 is shifted in the 90° direction. Conversely, when the phase relationship between the waveforms of electrodes 1-1 and 1-2 exceeds 90°, a countdown is performed and the phase relationship is shifted toward 90° in order to advance the phase of the waveform applied to electrode 1-2. Therefore, the phase relationship between the waveforms of electrodes ]-1 and 1-2 is always controlled to be 90°.

23 is a thinning circuit that changes the response of the counter 22 to the outputs 0UTi and 0UT2 of the comparator 24 to Z;
When the counter 22 is sent out, the counter 22 is caused to perform an up or down count operation, and the response sensitivity of the counter 22 is reduced.

It is assumed that the positional relationship between the electrode 1-1 and the electrode 13 is shifted by 90 degrees. Next, the operation of the embodiment shown in FIG. 5 will be explained.

By turning on the power (not shown), the power-up cellar I
- The circuit 26 is activated and an initial value (for example, 0111) is set in the counter 22. In this state, the multiplexer
It is assumed that 21 selects the output terminal Q8 of the register 20.

” Output end of register 20 like two series Q + −Q s
is 11. for that D input signal. , 25°, the pulse at the output terminal Q8 is delayed by il, 25X8=90° with respect to the pulse at the D input terminal.

On the other hand, since VCO5 starts operating when the power is turned on, the corresponding V
The pulse from CO5 is input to the frequency divider circuit 19, and the frequency divider circuit I9 outputs a pulse obtained by dividing the pulse of VCO5 by 32, and sends the pulse to the electrode I-1 via the amplifier 7 and the coil 10.
to be applied.

On the other hand, as described in -1- (from the multiplexer 21, the pulse of the Q8 output of the register 20, that is, the pulse of the frequency divider) 9, the pulse shifted by 90 degrees with respect to the pulse of the amplifier 8 and the coil 11 is sent to the electrode 1. -2.By the action of coils 10 and 11 and electrodes 1-1., 1., . 1-1..1-2, this generates a progressive vibration wave on the surface of the stator 1, the moving body in frictional contact with the stator surface rotates, and the SSM operates. .The electrode 1
-1.1. -2 waveforms are respectively comparator 16.
The pulse of the comparator 16 is converted into a pulse at 17 and applied to the S input terminal of the comparator 24.

On the other hand, the pulse of comparator 17 is I Fujistar 25
Since this register is operated using the pulse of VCO5 as a clock, a pulse whose phase is delayed by 90 degrees with respect to the output of comparator 17, that is, the waveform of electrode 1-1, is output from output terminal Q8. is output, and this is input to the R input terminal of the comparator 24. Now, electrode 1-
Assuming that the waveform of electrode 1-2 is delayed by 90 degrees with respect to the waveform of electrode 1-1, the pulse from the output terminal Qt+ of register 25 is delayed by 90 degrees with respect to the waveform of electrode 1-1.
Pulses of the same phase are input to the R and S input terminals of the comparator 24. Therefore, in this state, register 2
The SSM continues to be driven with the pulse from the zero output terminal Q8 being selected.

- When driving as described in item 8, even if the output terminal 8 of the register 20 is selected and a pulse with a phase of 900 is input to the amplifier 7.
, -1 and 1-2 do not maintain a 90' phase difference relationship, the counting direction of the counter 22 is determined in accordance with the phase shift direction with respect to the 90 degree phase difference relationship. That is, when the phase difference between the waveforms of the second electrodes 1-1 and 1-2 is within 90 degrees,
When the phase relationship shown by the dotted line in FIG. , 0UT2 are sent out twice, so that the counter 22 counts up by one, and the multiplexer 21 selects the output end of the register by switching from Q8 to Q9. The pulse at the output end Q9 is relative to the pulse at the output end Q8]1. ．． Since the pulse has a phase delayed by 25°, the phase difference between the pulse applied to amplifier 7 and the pulse applied to amplifier 8 is from 90° to 101°2.
Move to 5°. Therefore, the phase of the waveform applied to electrode 1-2 is delayed, and the phase difference between the waveforms applied to electrodes 1-1 and 1-2 is shifted in the 90° direction. Conversely, if the phase difference between the electrodes 1-1 and 1-2 is 90 degrees or more while the phase difference between the pulses applied to the amplifiers 7 and 8 is maintained at 90 degrees, the counter 22 counts down by 1. be done. As a result, the multiplexer 21 selects the output terminal Q7 of the register 20 instead of the output terminal Q8. Therefore, the phase difference between the pulse applied to amplifier 8 and the pulse applied to amplifier 7 is 90
Electrode 1 from 78.75° which is 11°25° from
The waveform applied to -2 also advances to the electrode] -1 and 1. The phase difference of the waveform with -2 is shifted in the 90° direction.

As described above, the phase difference relationship between the waveforms applied to the electrodes 1-1 and 1-2 is controlled to always be 90°.

As mentioned above, assuming that the electrical characteristics between electrode]-1 and electrode 1-4 and the electrical characteristics between electrode 1-2 and electrode 1-4 change depending on the rotational position of the moving body, electrode 1 ~1 and 1-
The phase difference between the applied signals between the two will change in a short period of time. Therefore, in extreme cases, when the comparator 24 performs the comparison operation during the 90° phase difference control described in 2, the output of the comparator 24 changes from 0UTI or 0UT2 every cycle of the voltage applied to the electrodes 1-2. However, since the output of the comparator 24 is transmitted to the counter 22 via the thinning circuit 23 as described above, the counter 22 receives the output 0UTI or 0UT2 of the comparator 24 twice. Every time 7 is sent out, a count-up or town operation is performed.

Therefore, the change operation of the pulse applied to the amplifier 8 under 90° phase difference control is Z when there is no thinning circuit, and 9
When the pulses to the amplifier 8 are changed in a short period during 0° phase difference control, it is possible to reduce the rotational irregularities of the SSM compared to when the pulses are changed directly to the amplifier 8 without using a thinning circuit. Become.

Through the following operations, the phase difference between the waveforms at electrodes 1-1 and 1-2 is controlled to be kept constant, and in this embodiment, the SSM is always driven at the resonant frequency. frequency control is performed.

The frequency control operation will be explained below.

In order to drive the SSM at the resonant frequency, drive electrode],
-] or 1-2 drive voltage waveform and monitor electrode 1
It is sufficient to maintain a constant phase difference relationship with the monitor waveform representing the driving state of the SSM at -3. That is, if the waveform relationship between the electrodes 1-1 and 1-3 is maintained at the same phase difference relationship as the positional relationship between the drive electrode 1-1 and the monitor electrode 1-3, the electrodes 1-1 and 1-3 can be driven in a resonant state. Become. Since the gold electrode 1-1 and the electrode ]-3 are arranged with a 90° deviation, resonant driving can be achieved by controlling the waveforms of the electrodes 1-1 and 1-3 to also be 90° apart.

As mentioned above, the output of the output terminal Q8 of the Lenstar 25 is the 10th
As shown in figure (C), if the waveform of electrode l-1 is λ1 and the phase is 90
°The pulse is delayed. The pulse is inverted by the inverter 18 to produce the pulse of FIG. 10 (Q), that is, the electrode 1.
Comparator 1 as a 900-advanced pulse for the −1 waveform
It is transmitted to the S input terminal of the notor 12.

On the other hand, the waveform of the electrodes 1-3 is converted into a pulse by the comparator 2, and is transmitted to the I input terminal of the I-comparator 1 notator 12. If the rising pulse to the R input terminal of the comparator 1 notor 12 occurs earlier than the rising pulse to the S input terminal, or the rising pulse to the S input terminal, as in a double series (
31 Output of the rising signal difference comparator 12 (
AII, and conversely, if the rising tri-signal to the S input terminal is generated before the rising -1- signal to the R input terminal, the output of the rising signal difference comparator 12 becomes ■, and further (2) When rising signals are simultaneously input to the A and S input terminals, the comparator 12 is in an oven state. Therefore, the pulse of comparator 2, that is, electrode 1-
When the phase of the waveform from electrodes 1-1 and 3 leads the phase of the pulse from the inverter 18, that is, when the phase difference between the waveforms of electrodes 1-1 and -3 becomes 90° or more -L, the phase difference period The output of the minute comparator 12 becomes H and the corresponding I]
is input to VOC5 via low-pass filter 4,
(2) The input voltage to O05 increases, and the oscillation frequency of VOC5 increases accordingly.

The oscillation frequency of VOC5, that is, electrode 1-, , ]-, 1
---The higher the drive frequency to electrode 1-2, the more the signal input to electrode 1-1 changes in phase than the signal generated at electrode 1-3. −
The phase difference between 1 and 1-3 is controlled in the 90° direction.

Conversely, when the phase difference between electrodes 1-1 and 1-3 is within 90', the rising signal to the S input terminal of the comparator 12 is generated earlier than the rising signal to the R input terminal. Therefore, the output of the phase difference comparator 12 becomes L, and the oscillation frequency of the VCO 5 decreases. -1.
The driving frequency for electrodes 1-2 is also lower, and electrodes 1-1 and 1-3
The phase of the waveform increases and the phase difference between electrodes 1 and 1-3 shifts to 90' direction.

In this way, the phase difference between the waveforms of electrodes 1-1 and 1-3 is detected, and the driving frequency of the SSM is controlled so that this phase difference is always 90 degrees, so that the SSM is always driven and controlled in a resonant state. 3. Figure 11 is the SS shown in Figure 5.
This is a circuit diagram showing a specific configuration of M, and the same block portion as in FIG. 5 has the same arrow 1M=t. In phase comparator 12 in the figure]2-L]2-2. 12
-13. 12-1/I, 1.2-15. 12-
16 is an inverter, 12-3, 12-8 are ant games
1., 12-4, 1.2-5, 1.2-6,
12-7 is OR gate, 12-9, 12-12 is NOAKATE, ] 2- ], (1, 12-1, 1 is NAND G-1, 12-17 is D) channel MO3FET,
1.2-18 is NchiA Tunnel MOS FET
It is.

Since the comparator 12 itself is well known, a detailed explanation thereof will be omitted, and its input/output characteristics are as described in FIG. 7 above. It does not show wax or oven condition.

The low-pass filter 4 is composed of resistors 4-1 and 4-2 and a capacitor 4-3, and the resistor 4-1 is connected between the input and output of the low-pass filter 4, and the resistor /I-2 and the capacitor 4-3 are connected to each other.
-3 is connected in series for output run l;' (GND)l. 5-1 in VCO5. l: J operational amplifier, 5-2. 5-6. 5-7. 5-8.
5-8゜5-9 is N I) N-type transistor, 5-3
．． 5-4.5-5 is a PNP type transistor, 5-]
0, 5-1.6 is a resistor, 5-11 is a capacitor, 5
-i, 4.5-15 are Nantage-1, 5-], and 7 are constant current sources, respectively. The input of the VCO 5 is the ■ input of the operational amplifier 5-1, the θ input of the amplifier 5-1 is connected to the emitter of the transistor 5-2 and one of the resistors 5-10, and the other of the resistors 5-10 is Connected to GND. The operational amplifier 5-], ]l-run sister 5-2 and resistor 5--10 constitute a voltage-current conversion circuit, and a current corresponding to the voltage input to the amplifier 5-1 is transferred to the collector of the transistor 5-2. flow to.

The collector of transistors 5-2 is transistor 5
-3 collector and base, transistor 5-4.5
-5, and further connected to the constant current source 5-1.7, and the transistor 5-3.5-'I.

5-5 constitutes a current mirror circuit.

Further, the collector of the transistor 5-4 is connected to the I node of the tin sisters 5-6 and 5-7 and!・Run Sister 5-7. 5-8. It is connected to the base of 5-9. The collector of transistor 5-5 is connected to transistor 5-8. 5-! ○ input of 2 and ■ input of 5-13, and further (j
Connected to capacitor 5-11. The input voltage of the comparator 5-12 is the base voltage ■1, and the input voltage of the comparator 5-12 is
3 e input is the reference voltage JI V2 (V + > V2.
) is applied, and the output of the comparator 5-12 is applied to one input of the NAND game 1-5-14;
The output of the Nando game 1□5-15 is connected to the other human power.

The output of comparator 5-13 is connected to one input of a Nant gate and to the other input of gate 5-1-5 (") to the output of gate 5-14.

The gate 5-1. 4. , 5-], , 5 constitute a flip-flop, and the gates of the flip-flop 5-1 . The output of transistor 5 is applied to the base of transistor 5-6 via resistor 516.

In the frequency dividing circuit 19, 19-, ] to 19-5 are D-type flip-flops, which constitute a 32 frequency dividing circuit for the input pulse from the VOC5. In the amplifier 7, 7-1. 7-10. 7-2.
7-4. 7-5 is NI) N-type transistor, 7-3 is PNP-type l run sister, 7-7, 7-8
indicates a diode. Also, amplifier 8 is amplifier 7
It has the same configuration as .

In Schifl-1 no sister 20.25, 20-
1 to 20-16 and 25-1 to 25-8 are D-type flip-flops whose clock terminals are connected to the output of the VCO 5, and whose output terminals at the previous stage are connected to the D input terminals at the subsequent stage.

In the phase comparator 24, 24=1. 24
-2. 24-3. 24. -4-, 24--
5. 24. -6 is an inverter, 24. -7.
24. -8 is Antogame-1, 24-9.

24=10. 24-Il. , 24-12 is Orgate, 24-13. 24-1.4 is Noah Gate,
24-15. 24-16 is Nantes Gate.

In the thinning circuit 23, 2 3 − ], 2:
3-2 is an l) type flip-flop that responds to a signal change from L to I; 23-3. 23-4 is or game 1-.

The circuit operation in FIG. 11 is as explained in FIG.
3. The operations of the filter 4 and VCO 5 will be supplementarily explained.

First, the operation of the thinning circuit 23 will be explained. In the initial state, the flip-flop 23-1. , 23-2 is assumed to have an H output. In this state, the comparator 24 outputs an L signal as shown in FIG. 12(a), and when the signal 7 changes to H, the flip-flop 2 knee 1-1 outputs a Q output as shown in FIG. 12 (one). L and Nazu. At this time, or gate 2 3-
3 is connected to the Q output of the D flip-flop 23-3 and the output of the comparator 24, so the OR game 1-
23-3 does not respond to (2) of the comparator 24 written in -, and continues to send H as shown in FIG. At this point, the Q output of the flip-flop 23-1 is L, so the OR game 1-23-3 outputs 12 from the comparator 12 and transmits it to the counter 22, causing the counter 22 to perform a counting operation. The thinning circuit transmits the counter I signal and the L signal to the counter 22 only when the output of the comparator 1 noter 271 reaches the second turn.

As described above, when the OR gate 23-3 sends out the signal 7, the Q output of the flip-flop 23- becomes the Q output, and the operation described above cannot be repeated.

Also, flip-flop 23-2 and or gate 23-4
is the flip-flop 23-1 and the OR gate 23-
It performs exactly the same operation as 3.

Next, the operation of the filter 4 and vCO5 will be explained.

Capacitor 4-3 of filter 4 is comparator 1
Since it is connected to the output of the comparator 12, the longer the period in which H is output from the comparator 12, the more it is charged and becomes a high potential. When the output of the comparator 12 is in the open state, the potential of the capacitor 4-3 is maintained as it is.

That is, the filter 4 smoothes the output of the comparator 12, and as a result, an output corresponding to the output state of the comparator 12 is generated at the capacitor 4-3.

To be more specific, as mentioned above, the phase difference to the R4S input of the comparator 12 is zero, that is, electrodes 1-, ] and electrodes 1-3.
When the phase difference is 90°, the output of the comparator 12 is in an oven state, so the low-pass filter 4
The potentials of capacitors -4 and -3 remain as they are, but when the waveform of electrode 1-3 becomes a larger phase lead than the waveform of electrode 1-1, As described above, the output of the comparator I noter 12 is a high signal with a duty corresponding to the phase difference, and the voltage of the capacitor 4-3 of the filter 4 increases. The waveform of electrodes 1-3 is 90° with respect to the waveform.
When the phase is advanced by a smaller amount, the output of the comparator I noter 12 becomes a low signal (ground level) with a duty corresponding to the phase difference, and the charging potential of the capacitor 4-3 decreases according to the duty.

That is, the filter 4 has the function of converting the output state of the comparator 12 into a voltage and transmitting the converted voltage to vCO.

Since the output of the filter 4 is input to the vCO amplifier 5-1, a current corresponding to the output voltage of the filter 4 flows through the resistor 5-10, forming the current at one terminal of the collector of the transistor 5-2. That is, amplifier 5-1, resistor 5-
10. Transistor 5-2 connects a voltage-current conversion circuit that converts the filter output into current. To explain in detail, if the output of filter 4 is V, resistor 5-10
Since the voltage V is applied to the resistor 5-10, if the resistance value of the resistor 5-10 is R, the following current flows, and this current is formed at one terminal of the collector of the transistor 5-2. Also, constant current source 5
If the constant current of -17 is 12, then this 12 and "2ki 11
When the composite current (2) is supplied from the transistor 5-3 and forms a current mirror circuit, the current of the transistors 5-4, 5-5 also becomes the above T.

Assume that the transistor 5-6 is now off and the capacitor 5-11 is in a charged state.

In this state, all the current flowing through transistor 5-4 flows through transistor 5-7, so transistor 5
-7 and transistor 5 forming a current mirror circuit.
-8. A current having the same value as that flowing through the transistors 5-7 flows through the transistors 5-9, respectively.

As a result, the current value flowing through the l-run sister 5-5 and the current value flowing through the transistors 5-8, 5-9 are the same, so that the current flowing through the transistor 5-5 from the capacitor 5-11 is equal to the current value flowing through the transistor 5-5. A current flows out, and the capacitor 5-11 is discharged at the value of the current flowing through the transistor 5-5, that is, I.

As a result, the potential of capacitor 5-11 decreases, and when it becomes below the reference level v2, the output of comparator 5-13 becomes L.
Nantes gate 5-1 that constitutes a flip-flop
5's output I]. Therefore, transistor 5-6 is turned on. When the transistor 5-6 is turned on, all the current flowing through the transistor 5-4 flows to the ground, and the current flowing through the transistor 5-7. 5-8.
5-9 is off.

Therefore, in this case, the current flowing through the transistor 5-5, that is, the above I, charges the capacitor 5-11 with a constant current, and the potential of the capacitor 5-11 rises to the reference level ■]
reach. As a result, the comparator 5-12 is inverted and the output is set to L, so that the outputs of the NAND games 1-5-1 and 5 are set to L, and the I/Run sister 5-6 is turned off again. After this, the second discharge is performed again, and the subsequent charging and discharging are repeated.

"The charging and discharging of the capacitor 5-11 as in a double series is as follows.
The current value I of the transistor 5-4 is determined according to the voltage of the capacitor 4-3 of the filter, that is, the output state of the comparator 12. It will be determined according to the phase difference between the waveforms of -1 and electrode 1-3.

To explain in detail, the waveform of electrode 1-3 with respect to electrode 1-1 is 90
Since the output of the comparator 12 is in the open state when the phase is in the phase lead state, the potential of the capacitor 4-3 is held constant, so the current value I also becomes constant. Therefore, in this case, the second capacitor 5-
The charging/discharging operation for 11 is also at a constant speed, and the output of the NAND game 1-5-], /l that constitutes the flip-flop is also inverted at the above-mentioned constant speed, so the frequency of the output pulse of the flip-flop is maintained constant. S.S.
In this state, M is driven and maintained at a constant resonance frequency.

Also, if for some reason the waveform of electrode 1-3 with respect to electrode 1-1 becomes larger than a 90° phase lead, the output of comparator 12 becomes high and its period becomes longer as the phase difference becomes dog. , the capacitor 4-3 is charged and its potential becomes higher as the phase difference becomes larger. Therefore, since both the current value and (2) become large, the output frequency of the flip-flop moves in an increasing direction. With this, electrode 1-1
, ], the frequency of the drive waveform to -2 increases, the drive waveform returns to the resonant frequency of ``2'', and the electrodes ]-] and 1-
The phase difference between the waveforms in item 3 also returns to the 90° phase difference in item 2.

In addition, conversely, the drive waveform is different from that of electrode 1-1 with respect to the waveform of electrode 1-1.
3 and the waveform is smaller than 90° phase lead, the output of the comparator 12 indicates low, and the period of low becomes longer as the phase difference becomes larger. Therefore, capacitor-4
The amount of discharge of -3 also corresponds to the phase difference, and the potential of capacitor -4-3 decreases to the extent that the phase difference becomes small, and the current value I also becomes small, so the output frequency of the flip-flop becomes low. move in the direction of Now electrode 1-]-
, 1-2 also decreases, returning to the resonance state described above, and the waveforms to the electrodes 1-1 and 1-3 also become the 90' state.

In this way, the VCO filters its output pulse frequency to
It is determined according to the potential of the capacitor 4-3, and shifts the driving frequency to the electrodes 1.-1, . . . , .-2 to the resonance frequency as described above.

Also, in the initial stage of SSM operation, capacitor 4-3
Since the potential of is zero, no current flows through the collector of the transistor 5-2, but in this case, a constant current value regulated by the constant current source 5-17 is applied to the capacitor 5-11. The SSM is driven by charging and discharging.

<Effects> As described above, the present invention detects the waveforms of the drive electrodes 1-1 and 1-2, and performs the feedback control intermittently in the motor drive circuit that performs feedback control so that the phase difference between them is constant. Since the control is performed at a frequency of once every two synchronizations of the drive signal to the electrodes in the embodiment, even if feedback control is performed, the duty ratio of the pulse applied to the amplifier 8 will not change. This can reduce the probability that rotation will occur, and can prevent uneven rotation.

Further, in the embodiment, the thinning operation is performed once every two cycles of the frequency signal applied to the drive electrode, but this ratio may be determined as appropriate.

Alternatively, a timer that outputs a signal for a predetermined time at predetermined intervals may be provided as a circuit for performing the thinning operation, and the output of the comparator 24 may be transmitted to the counter 22 only while the timer output is being generated. good.

Furthermore, in the embodiment, the waveforms of electrodes]-1 and 1-2 are directly detected by a comparator, and when the phase difference increases or decreases with respect to 90°, the count value of the counter 22 is increased or decreased. It's okay. In this case, the comparator is 0UTI, 0U based on the time when there is a 900 phase difference.
It is sufficient to use one that outputs T2.

Furthermore, in the embodiment, the phase is controlled digitally, but the phase is controlled at 90° with respect to the waveform applied to one electrode analogously.
A phase shifter is arranged without any deviation, and there is no way to apply the output of this phase shifter to the other electrode.At this time, the phase difference between the waveforms of each electrode is detected, and the deviation from the constant relationship of the phase difference is sent to a comparator circuit. The phase shift amount by the phase shifter may be adjusted based on the detection output.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram showing the shape of the electrodes of the stator of the ultrasonic motor, Fig. 2 is a circuit diagram showing the configuration of the driving voltage application circuit section to the electrodes in Fig. 1, Fig. 3 (a, ), ( b) is a waveform diagram showing drive pulses of the ultrasonic motor; FIG. 4 is a configuration diagram showing the electrode shape of the stator of the ultrasonic motor according to the present invention; FIG. 5 is a drive circuit for the ultrasonic motor according to the present invention. A block diagram showing one embodiment; FIG. 6 is a block diagram showing the configuration of the comparator 12 shown in FIG. 5; FIGS. 7(a), (b), and (c) are characteristics of the comparator shown in FIG. FIG. 8 is a block diagram showing the configuration of the comparator 1 noter 24 shown in FIG. Waveform diagram showing characteristics, 1st
Figure 0 (a), (b), (c), (cl),
(e) and (f) are waveform diagrams explaining the operation of the embodiment shown in Fig. 5, Fig. 11 is a circuit diagram showing a specific circuit configuration of the embodiment shown in Fig. 5, and Figs. 12 (a) and (b). ) and (c') are waveform diagrams illustrating the operation of the thinning circuit 23 shown in FIG. , 19
・・・・・・・・・・・・・・・・・・ Frequency dividing circuit 20.
25...Mountain shift register 24...
・・・・・・・・・・・・Comparator 23・
・・・・・・・・・・・・・・・・・・ Thinning circuit 22・
・・・・・・・・・・・・・・・・・・Up-Down Counter 2I・・・・・・・・・・・・・・・・・・Multi-Blexer Patent Applicant Canon Co., Ltd. No. 1 Flash, /-4

Claims (1)

[Claims] An electric-mechanical energy conversion element is arranged on the first structure,
A progressive vibration wave is generated by applying frequency voltages having mutually different phases to the conversion element, and the vibration wave causes relative movement between the second structure and the first structure that are in contact with the first structure. In a drive circuit for a sonic motor, a feedback control circuit detects a frequency voltage applied to the conversion element and performs feedback control to maintain a constant phase difference between the frequency voltages, and a feedback control operation by the feedback control circuit. What is claimed is: 1. A drive circuit for an ultrasonic motor, comprising: a thinning circuit that performs this intermittently.