JPS6218992Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a timing circuit that outputs a signal for a certain period of time after a certain period of time from a certain reference pulse signal (hereinafter referred to as the reference signal), and in particular charges and discharges a capacitor using a reference signal of a certain period. This invention relates to a device in which a sawtooth potential due to charging and discharging of this capacitor is applied to the input side of a window comparator, and the output of this window comparator is used as the output of a timing circuit.

In such a timing circuit, the present invention is useful, for example, when using the signal output from the comparator on the rising side of the input of the window comparator (the charging potential of the capacitor) as the output signal of the timing circuit. Since the signal outputted at the discharge potential (discharge potential of This device is characterized in that it is possible to prevent the generation of the above-mentioned unnecessary signals that cause malfunction of the device.

Embodiments of the present invention shown in the drawings will be described in detail below. First, in Fig. 1, 1 is a reference signal generator that outputs a reference signal at a constant cycle, 2 is a base connected to the output terminal of the reference signal generator 1 via a resistor 3, and a collector connected to resistors 4 and 5 in series. The emitter is connected to the + side (Vcc) of the DC power supply through the terminal, and the emitter is connected to the earth side (E side) of the DC power supply, and the npn transistor acts as a discharge for the capacitor described later. 6 is the connection point between resistors 4 and 5. A charging/discharging capacitor is connected between the DC power source and the ground side of the DC power supply, 7 forms a series circuit with a resistor 8 and is connected between the + side of the DC power source and the ground side, 9 is a series circuit with the resistor 10. A resistor 11 connects the non-inverting input terminal to the connection point between the resistors 9 and 10, that is, point a, and 12 the inverting input terminal. This is a second comparator connected to the connection point between the resistors 7 and 8, that is, point b. The connection point of the resistors 4 and 5 and the capacitor 6, that is, the point L, is connected to the inverting input terminal of the first comparator 11 and the non-inverting input terminal of the second comparator 12 as inputs (in) of the window comparator. are doing. Further, the output ends of both comparators 11 and 12 are connected to a wired OR, and the output becomes the output (out) of the window comparator, that is, the output of the timing circuit.

3 is a NOT circuit connecting the input end to the output end of the reference signal generator 1, that is, point A, and inverter means), 14
is a pull-up resistor connected to the NOT circuit 13 between the output terminal and the + side of the DC power supply. Therefore, when the window comparator is an open collector and obtains a high-level output, it is necessary to connect the output to a high-level potential using a pull-up resistor 14. In this embodiment, the capacitor 6 is charged with the above circuit configuration. It is set so that it can be connected to a high level potential only when

Next, Figure 2 is a signal waveform diagram of each part of the proposed timing circuit, and Figure 3 is a timing circuit in which the proposed timing circuit is not implemented (the NOT circuit 13 is omitted and one end of the pull-up resistor 14 is connected to the + side of the DC power supply). thing)
1 is a signal waveform diagram of each part, A is the output waveform of the reference signal generator 1 [the waveform at point A in FIG. 1], B is the potential of the capacitor 6 [the potential at point B in FIG. 1], and a is the resistor. b is the potential of the non-inverting input terminal of the first comparator 11 determined by resistors 7 and 10 (potential at point a in FIG. 1), and b is the potential of the second comparator 12 determined by resistors 7 and 8. The potential at the inverting input end [the potential at point b in FIG. 1], and C indicates the output waveform of the window comparator [the output waveform at point C in FIG. 1]. and,
1 indicates the time from the reference signal until the signal is output, and 2 indicates the time from the reference signal until the output signal stops.

In the timing circuit configured as described above, when the reference signal generator 1 outputs the signal shown in FIG. Since the electric charge is discharged through the resistor 5 and the transistor 2, the potential of the capacitor 6 becomes approximately zero potential.

When the signal from the reference signal generator 1 disappears and the transistor 2 becomes non-conductive, the capacitor 6 is charged from the positive side of the DC power supply via the resistor 4 as shown in FIG. 2B. At the beginning of charging, the comparator 11 outputs a high level because the potential at the non-inverting input terminal is higher than the potential at the inverting input terminal, but the comparator 12 outputs a high level because the potential at the inverting input terminal is higher than the potential at the non-inverting input terminal. Since it is a level output, the output signal of the window comparator connected to wired OR is not output. When the potential of the capacitor 6 rises from this state and the potential of the non-inverting input terminal of the comparator 12 becomes higher than the potential of the inverting input terminal, the output of the comparator 12 also becomes high level, and the window comparator connected to the wired OR The signal shown in FIG. 2C is outputted after one hour has elapsed since the reference signal.

Then, when two hours have passed since the reference signal,
Since the potential at the inverting input terminal of the comparator 11 becomes higher than the potential at the non-inverting input terminal, the output of the comparator 11 becomes a low level, and the output of the window comparator also becomes a low level, as shown in FIG. 2C.

When the reference signal is output again from the reference signal generator 1, the transistor 2 becomes conductive and the charge in the capacitor 6 is discharged, and during the discharge, there is a period in which the outputs of both the comparators 11 and 12 are both at a high level. However, since the reference signal is inverted by the NOT circuit 13 and the output of the window comparator is not connected to the high-level potential by the pull-up resistor 14, the output of the window comparator is at a low level, as shown in Fig. 2 (c). As shown, no unnecessary signals are generated. In other words, while transistor 2 is turned on by the reference signal, the potential of the capacitor rapidly decreases and passes through potentials a and b, so between potentials a and b, the outputs of comparators 11 and 12 are both at a high level. becomes. Therefore, if the output terminal of the open collector window comparator is connected to a high level potential by the pull-up resistor 14, a signal such as α in FIG. 3 will be generated.

However, in the present invention, the pull-up resistor 14 is connected to the inverted low level potential by the inverter means 13 while the reference signal is generated, so that the output of the window comparator remains at a low level. However, a signal such as α in FIG. 3 is not generated.

Note that the timing circuit of the present invention detects the presence of an object to be detected by, for example, transmitting an ultrasonic pulse from an ultrasonic transmitter to a predetermined space and receiving the reflected wave by an ultrasonic receiver. In an ultrasonic pulse echo switch, it is used to set the sensing distance range for sensing the object to be detected, and the output of the window comparator is used as the sensing distance range. Of course, the timing circuit of the present invention is not limited to the above applications.

As described above, according to the present invention, generation of unnecessary signals can be prevented with a simple configuration, and a timing circuit without malfunction can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a timing circuit in which the present invention is implemented, Fig. 2 is a signal waveform diagram of each main part of Fig. 1, and Fig. 3 is a signal waveform diagram of each main part of a timing circuit in which this invention is not implemented. . 1...Reference signal generator, 6...Capacitor, 1
1, 12...Comparator, 13...NOT circuit, 14...Pull-up resistor.

Claims (1)

[Scope of Claim for Utility Model Registration] A reference signal generator that generates a reference pulse signal of a constant period, a switching means that is turned on and off by the reference pulse signal, and a switching means that is connected in parallel to a power source, A capacitor means for outputting a sawtooth potential in response to turning on and off of this switching means, a window comparator having the output of this capacitor means as a comparison input, an inverter means for inverting the reference pulse signal, and this inverter means. A timing circuit comprising: a pull-up resistor connected to the output end of the window comparator;