JPS6218990B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to semiconductor memory circuits.

The following is an N-channel MOSFET for convenience of explanation.
Let's talk about circuits using .

A conventional memory circuit is shown in FIG. The memory circuit includes digit lines D ₁₁ , D ₁₁ , D ₂₁ , D ₂₁ , data buses DB ₁ , D ₁ , and a sense amplifier 10 .
The operation of the circuit of FIG. 1 is as follows. Taking a memory read cycle as an example, now word line W ₁₁
is “1” potential, Y decoder output YDE ₁₁ is “1”
Since the memory cell _C11 is selected and the digit line _D11 is "1" and _D11 is "0", the data bus line is inevitably set to _DB1 as "1" and _D1 as "0". The output potential of the sense amplifier 10 is such that SA ₁ is "1" and S ₁ is "0". Now, in this state, the address input signal changes, the selection of the word line changes from W ₁₁ to W ₂₁ , and the Y-decoder output is that YDE ₁₁ continues to be selected, and the memory cell C
Assume that character ₂₁ is selected. In this case the memory cell
There is no problem if the memory information of C ₂₁ is the same as C ₁₁ , but
If the information is the opposite, the state of the digit line _D11 must be changed from "1" to "0", and the state of the digit line _D11 must be changed from "0" to "1". The same applies to the data bus lines DB ₁ , D ₁ and the sense outputs SA ₁ , S ₁ . Naturally, these state changes occur after the address input signal changes, so time is required for the outputs of the digit line, data bus line, and sense amplifier to reach the equalization potential. The control signal EQ', which is a one-shot signal generated by detecting a change in the address input signal, is generated by detecting a change in the address input signal, and equalizes the potential of the digit line equalizing transistors Q ₁₁ and Q ₂₁ and the data bus line equal potential. The voltage is supplied to the gates of the equalization transistor Q ₃₁ and the sense amplifier equalization transistor Q ₄₁ , and the respective nodes are equalized, and then the word line is directed to the potential that selects the memory cell, and accordingly the signal EQ is set to the potential of “0”. When a memory is selected, the digit line, data bus line, and sense amplifier output are at approximately the same potential. However, the potential of the signal EQ' is normally close to ground potential, and it takes time to reach the level of the equalization potential of the output of the digit line, data bus line, and sense amplifier. Since there is not enough time for the output potential to reach the equalization potential, the word line moves toward the selection level without sufficient equalization, resulting in a slow access time. If the equalization potential level remains unchanged, there is a drawback that the writing time is delayed.

An object of the present invention is to provide a memory circuit with faster access time.

In the present invention, first, a one-shot signal that equalizes the potentials of the digit line, data bus line, and sense amplifier output does not affect the potential equalization of the digit line, data bus line, and sense amplifier output unless it exceeds the equalization potential. First, we focused on the fact that the one-shot signal reaches the equalization potential after a certain period of time after the address change is detected. The inactive potential of the one-shot signal that equalizes the potential of the output of the digit line, data bus line, and sense amplifier is set to the lower level side of the digit line, data bus line, and sense amplifier during reading, that is, logic "0". The transistor used for equalization is kept at a potential that does not conduct with respect to the potential on the level side. For example, if the potential on the low level side is
When the voltage is 0.8V and the threshold value of the equalization transistor is 0.5V, the time it takes for the oneshot signal to reach the equalization potential level can be shortened by keeping the inactive potential of the oneshot signal around 1V. In the end, the access time can be shortened. Furthermore, when a one-shot signal is generated during writing, potential equalization occurs and works to prevent the writing operation and delays the writing time. The level of the one-shot signal when inactive is raised to the extent that the equalization transistor does not conduct with respect to the potential on the 0'' side.For example, when the low level side potential during writing is 0.3V and the threshold value of the equalization transistor is 0.5V. , writing time can be shortened by keeping the pulse around 0.5V.

FIG. 2 shows a logic circuit for obtaining a one-shot signal EQ from an address input signal. Input address input signal ADi, and its true complement signal ADi′,A
' is generated in the address buffer circuit AB, and the signal directly and the signal via the delay circuits 21 and 20 are respectively input to the NOR circuits N ₂ and N ₁ , and the gates N ₁ and N ₂
One shot signal Ai' is obtained by passing the output of NOR gate _N3 . Similarly other addresses AD ₁ ~ _{AD 12}
It is now possible to detect one-shot signals as well.
The operation of providing the OR gate RG and obtaining the signal EQ is as follows. Now, if the address input signal ADi changes from "0" to "1", the node C becomes "0" and the node D becomes "0" for a time (t _{D )} determined by the delay circuit DE.
_Ai ' remains at "0" until t _D
A one shot occurs with a pulse width of _E. The generated one shot is input to a decoding circuit (OR type decoder in the case of FIG. 2) together with one shots generated from other address input signals to generate an EQ. Similarly, when the address input signal changes in the opposite direction, a one shot is generated with the t _DE pulse width. The above operation is shown in FIG.

The present invention can be implemented by using the logic circuit shown in FIG. 2 in FIG.
An example of a circuit realized using MOSFET will be shown and explained.
The signal W is a signal with a potential of "1" during reading and "0" during writing. First, at the time of reading, W becomes the potential of "1", so the transistor Q ₃ is turned off, and the ratio of Q ₁ and Q ₂ becomes as shown in Fig. 5 (in the transfer characteristics of the inverter circuit), as described above. Select n such that the potential when the one-shot signal is inactive is obtained, and the EQ detects the address change, quickly reaches the equalization potential level, and equalizes the potential of the target node. Next, at the time of writing, Q ₃ becomes the ON state because the potential becomes "0", and similarly, the ratio of Q ₁ and Q ₃ is determined as follows: If n is selected so as to obtain a low level such that the equalizing transistor does not conduct with respect to the "0" potential of the digit line, data bus line, and output of the sense amplifier, the write operation cannot be prevented. The above operation is shown in FIG. 6, including changes in the address input signal, word line, digit line, data bus line, and sense amplifier output. In FIG. 6, the part indicated by the dotted line is the EQ shot pulse of the conventional example, and the rise of the EQ is improved by Δt in the figure.

Next, another embodiment according to the present invention will be described with reference to FIG. Digit lines D ₁₂ , D ₁₂ ,
D ₂₂ , D ₂₂ , data bus lines DB ₂ , D ₂ , a signal that equalizes the potential of the output of the sense amplifier 10 with SA ₂ , S ₂ ;
The potential of the outputs SA ₂ and S ₂ of the sense amplifier is equalized using the one-shot pulse EQ ₁ generated from the address input signal related to the selection of the word lines W ₁₂ and W ₂₂ using the address input signal related to the selection of the digit line. It is characterized by the use of the one-shot pulse EQ ₂ generated by the company.

Alternatively, the same effect can be obtained by using only the one-shot pulse generated from the address input signal related to word line selection, which equalizes the potential of the output of the digit line and data bus line sense amplifier. This is clear from the gist of the present invention.

Further, in FIG. 4, the effect of the present invention can be further enhanced by inserting a transistor _Q4 in parallel with the transistor _Q2 . The circuit diagram is 8th
The operating waveform diagram of FIG. 8 is shown in FIG. 9 and will be explained. One-shot pulse EQ in Figure 4
When returning from the “1” potential to the inactive potential,
Due to the characteristics of the inverter circuit, the response is poor as shown by the broken line in FIG. 9, so by inserting a one-shot pulse such as a signal, an improved one-shot signal EQ' can be obtained. For example, a signal may be used and the signal may be configured to be generated at the same time as the signal rises.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional memory circuit, Figure 2 is a circuit diagram showing a conventional memory circuit.
The figure shows a logic circuit for generating a one-shot signal from an address input signal.
FIG. 4 is an operation waveform diagram for explaining the operation of the circuit shown in the figure.
Figure 5 is a diagram showing the transfer characteristics of a general inverter circuit, Figure 6 is an operating waveform diagram showing the operation of the circuit in Figure 4, and Figure 7 is a diagram showing an example of a circuit realized using MOSFETs. 8 is a circuit diagram showing an embodiment of the present invention. FIG. 8 is a circuit diagram in which the circuit of FIG. 4 is improved in order to increase the effects of the present invention. FIG. 9 is an operating waveform diagram of the circuit of FIG. 8. C ₁₁ to C ₄₁ , C ₁₂ to _{C 42} ... memory cell, D ₁₁ , D
₁₁ , _D21 , _D21 , D12, _D12 , _D22 , _D22 ...digit line, _DB1 , _{D1 , DB2 , D2} ...data bus line.

Claims (1)

[Claims] 1 In a semiconductor memory circuit in which equalizing transistors are made conductive in response to a pulse to equalize a data line pair, the potential when the pulse is inactive is compared to the low level side potential that occurs on the data line pair during readout. and the potential of the pulse is set to a logic "0" that does not cause the equalization transistor to conduct with respect to the low level side potential of the data line pair during writing. A memory circuit characterized in that the level is set to .