JPS62189886A - Sub-sample filter device - Google Patents

Abstract

PURPOSE:To reduce the size of circuit scale by delaying an input picture signal in the vertical direction, sorting and supplying the outputs of the respective ones of plural horizontal signal processing circuits to two adding circuits, and switching the outputs of the adding circuits corresponding to the sampling phase of a line offset sub-sample. CONSTITUTION:A sub-sampled input picture signal (a) is delayed 1-4 in the vertical direction and subjected to arithmetics 5 and 6, then supplied to the plural horizontal signal processing circuits 8-10 that respectively have two signal-outputs. The circuits 8-10 respectively process an arithmetic operation centered on a transmitted sampling point and that of an interpolation arithmetic centered on a not-transmitted sampling point. The outputs of these circuits 8-10 are sorted in two lines, then added with each other 17 and 18. The outputs of these two adding circuits 17 and 18 are switched by means of a signal corresponding to the phase of the sampling.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to image restoration on the receiving side of an image signal transmission system in which a wide band image signal is narrowed by line offset subsampling and then transmitted.

2. Description of the Related Art Conventional sub-sampling filter devices include, for example, the Technical Report of the Television Society of Japan, “Satellite 1-channel transmission system for high-definition television JTEBS95-2, Vol. 7,”
It is shown in Ji44. Figure 3 shows 6 according to this conventional example.
This is an example of the configuration of a sub-sample filter device that constitutes a two-dimensional filter with 7 line taps. 41 to 44 are vertical delay circuits, and 47 to 49 are switches that are opened and closed by signals controlled according to the phase of subsampling. 61~
Reference numeral 63 denotes a one-dimensional filter that performs horizontal signal processing and has the configuration shown in FIG. 54 adds the outputs of 51 to 53.

The above example is an example in which N=2 and M=3, that is, 6 lines and 7 taps, but for the sake of simplicity, the conventional sub-sample filter device will be explained below based on this configuration example.

In the conventional sub-sample filter device configured as described above, the input signal originally corresponds to a signal at a so-called quincunx grid pixel position, as shown by the circle in Figure 5a or Figure 6. It is.

The signal corresponding to the pixel position marked with an x is not transmitted.

It is well known that by performing appropriate two-dimensional filter processing on such a quincunx grid input signal, interpolation can be performed on the transmitted signal. This purpose 2
As a dimensional filter, one having vertically symmetrical and horizontally symmetrical coefficients is generally used, for example, as shown in FIG. 5C. Since it is symmetrical in the vertical direction, the calculation in the vertical direction will output three signals: an output of 42, an output of 46, and an output of 46. On the other hand, the transmitted input signal is actually synchronized to a constant phase transmission lock with no line offset, as shown in FIGS. 6a or 6b.

In Fig. 6 a, b, it is assumed that there is no signal at the points marked with X, so in order to perform the two-dimensional filter processing shown in Fig. 6 C, This signal pattern causes a shift in the position of the pixel to be calculated, and also causes calculations to be performed using unnecessary signals. Therefore, in order to extract the transmission pattern according to the phase of the sub-samples and set unnecessary pixel positions to 0, the switch circuit 4 shown in FIG.
7 to 49 are provided. As a result, the rate of change of the output signal of the switch circuit is twice as fast as the transmission lock.

The signals extracted at predetermined pixel positions by the switches 37 to 39 are subjected to horizontal arithmetic processing by one-dimensional filters 61 to 63.The signals subjected to horizontal arithmetic processing are processed by an adder circuit 64. The output of this adder circuit becomes the output of the sub-sample filter device.

Problems to be Solved by the Invention However, in the above configuration, the switch circuits 47 to 49 for extracting the transmitted image signals at predetermined positions are
◇ Also, in the horizontal direction, as shown in Figure 4, in the case of 6 lines and 7 taps, the delay circuit requires 6
It requires seven stages, adder circuits, and four coefficient circuits, and has the drawback of being large in scale. Moreover, as mentioned above, this horizontal calculation must be performed at twice the speed of the transmission lock, and in particular, in order to operate the coefficient circuit and addition circuit stably, it is necessary to operate the same circuits in parallel. In many cases, there is a problem that the circuit size becomes even larger.The present invention eliminates such drawbacks in the conventional subsample filling device, and reduces the device size. SUMMARY OF THE INVENTION The present invention provides a sub-sampling filter device that operates stably in the sub-sample filter device. This is a sub-sampling filter device that includes a signal processing circuit, a first adding circuit, a second adding circuit, and a switching circuit.
The number of lines is 2N+1 and the number of taps is 2M+1, where is an integer.
a vertical signal processing circuit configured to constitute a two-dimensional filter, the device having a first signal delay circuit stage that performs 2N stages of vertical delay and outputting N+1 signals;
N+1 horizontal signal processing circuits that are coupled to each of the vertical signal processing circuits and include a second signal delay circuit stage that delays M horizontal pixels; an M1 addition circuit; and a second addition circuit; circuit, each of the horizontal signal processing circuits comprising an input signal to the second signal delay circuit stage and an input signal to the second signal delay circuit stage;
a first accumulation circuit configured to multiply the M signals delayed by the signal delay circuit stage by a predetermined coefficient, accumulate the result, and output the result; an input signal to the second signal delay circuit stage; It has a second accumulation circuit configured to multiply a part of the M-1 signals delayed by the second signal delay circuit stage by a predetermined coefficient, accumulate the result, and output the result. , the first addition circuit is configured to add a part of 2N+2 outputs of the N+1 horizontal signal processing circuits, and the second addition circuit is configured to add a part of 2N+2 outputs of the N+1 horizontal signal processing circuits.
The switching circuit is configured to add outputs of another part of the N+2 outputs, and the switching circuit switches the outputs of the first addition circuit and the second addition circuit by a signal that controls the sampling phase of the line offset subsample. This is a sub-sample filter device characterized by being configured as follows.

According to the above-described configuration, the present invention delays the subsampled input image signal in the vertical direction, performs a predetermined calculation, and then supplies the signal to a plurality of horizontal signal processing circuits each having two signal outputs. , each of the plurality of horizontal signal processing circuits performs two types of processing: processing that performs calculations centered on the transmitted sampling points, and processing that performs interpolation calculations centered on the points that are not transmitted, and performs these horizontal signal processing. The outputs of the circuits are classified into two systems and then added together, and the outputs of these two adder circuits are switched and outputted using a signal according to the phase of subsampling, thereby reducing the scale of the device and reducing the number of components of the device. It is possible to reduce the calculation speed required for the system and perform stable operation.

Embodiment FIG. 1 shows a sub-sample filter device in one embodiment of the present invention. In FIG. 1, 1 to 4 are vertical delay circuits, 6 and 6 are adder circuits, and 8 to 1o are horizontal signal processing circuits having the configuration shown in FIG. 17 and 18 are adder circuits, and 19 is a switching circuit. Figure 2 is Figure 1 8-1
The operation of the sub-sampling filter device of this embodiment configured as shown above in the block diagram of the horizontal signal processing circuit of No. 0 will be described below.

Figure 5 is a point A that is not transmitted by subsample transmission.
0x indicates that the signal marked with ○ around point A is multiplied by the coefficient in Figure 6 C using a delay circuit and then added. Therefore, the result is equivalent to calculation using the coefficients shown in FIG. 6a. On the other hand, the actually transmitted signal is as shown in Figure 7a.
It can be seen that it is not necessary to use all the coefficients shown in Figure C. Further, both the coefficients and the input signal necessary for the calculation for point A do not change during one transmission lock period, and the calculation only needs to be completed within one transmission lock period.

Similar calculations will be performed for point B. Figures 6, 6, 7, and 8 show calculations for point B. The above shows that calculations in the horizontal direction are possible by calculations between three or four pixels.

In the vertical direction, the symmetry is not lost even with the coefficients shown in FIGS. 8a and 8b, so it is possible to use the signal 7 and the outputs 5 and 6, respectively.

Based on the above, a two-dimensional filter corresponding to point A, that is, a in FIG. 8, is possible with the configuration shown in FIG. 9 a, and a two-dimensional filter corresponding to point B, that is, in FIG. This becomes possible with the following configuration, and the subsample filter can be switched between these two filters in accordance with the signal that controls the subsample phase. By the way, when comparing FIGS. 9a and 9b, many parts such as the vertical delay circuit and horizontal pixel delay are common, and when these are integrated, the sub-sample filter device shown in FIG. 10 can be obtained. The horizontal signal processing circuit has the configuration shown in Figure 2.Output 1 performs calculations between 4 pixels, and output 2 performs calculations between 3 pixels.In these calculations, the signal from the pixel delay stage is Although the calculation is performed by multiplying coefficients and accumulating them, a part of the delayed signals used in the calculation can be shared, so it is possible to use the configuration shown in FIG. 2.

As described above, according to this embodiment, the line offset subsampled input image signal is delayed in the vertical direction, and after predetermined calculations are performed, it is supplied to a plurality of horizontal signal processing circuits each having two signal outputs. , the scale of the device is reduced by classifying and supplying each of the plurality of horizontal signal processing circuits to two adder circuits, and switching the outputs of these two adder circuits according to the sampling phase of the line offset subsample. Addition circuits and coefficient circuits are the main components of the device.

Most of the pixel delay circuits and the like can be operated at low speed to perform desired calculations.

As described in detail, according to the present invention, the device can be made small-scale, most of the device can be operated at low speed, and stable operation can be expected. The low-speed operation greatly contributes to reducing the power consumption of the device, and its practical effects are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a sub-sample filter device according to an embodiment of the present invention, FIG. 2 is a block diagram of the horizontal signal processing circuit of FIGS. 8 to 1o in FIG. Block diagram, Figure 4 is Figure 3
Block diagram of one-dimensional filters 1 to 63, Figure 5 a, b
is a diagram showing the original pixel position of a signal subjected to line offset subsampling; FIG. 6C is a diagram showing an example of coefficients of a two-dimensional filter with 5 lines and 7 taps; FIG. 7 is a diagram showing a signal pattern transmitted by line offset subsamples, FIG. 8 is a diagram showing substantial coefficients in an embodiment of the present invention, and FIGS. FIG. 10 is a block diagram showing an example of a direct configuration of a filter with the coefficient b, and FIG. 10 is a block diagram of a device in which the components a and b in FIG. 9 are organized and integrated. 1-4, 41-44... Vertical delay circuit, 6, 6
゜17.18.24-2B,,46. 46. 54
. 61~66.77~88...addition circuit, 29~
32.64~67.90~96...Coefficient circuit,
60...Inversion circuit, 21-23.55-60.
71-76...Pixel delay circuit, 8-10...
...Horizontal signal processing circuit, 51-53...One-dimensional filter, 47-48...Switch, 19.
...Switching circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
figure? 4 Figure 3 Figure 4 Figure 5 It, Shishi 207 Figure 6/f! -, Send, go Tsuku River'' (Figure 9 (Reno)

Claims (1)

[Claims] A device that configures a two-dimensional filter having a line offset subsampled image signal as input, a number of lines of 2N+1, and a number of taps of 2M+1, where N and M are integers,
This device is coupled to a vertical signal processing circuit having a first signal delay circuit stage for performing vertical delay of 2N stages and outputting N+1 signals, and to each of the vertical signal processing circuits,
N+1 horizontal signal processing circuits each including a second signal delay circuit stage for delaying horizontal pixels, a first addition circuit, a second addition circuit, and a switching circuit. A horizontal signal processing circuit is configured to multiply the input signal to the second signal delay circuit stage and the M signals delayed by the second signal delay circuit stage by a predetermined coefficient, accumulate the result, and output the result. an input signal to the second signal delay circuit stage and M delayed by the second signal delay circuit stage;
- a second accumulator circuit configured to multiply a part of one signal by a predetermined coefficient, accumulate the result, and output the result; The second addition circuit is configured to add some of the 2N+2 outputs of the N horizontal signal processing circuits, and the second addition circuit is configured to add another part of the 2N+2 outputs of the N horizontal signal processing circuits. , wherein the switching circuit is configured to switch the outputs of the first addition circuit and the second addition circuit by a signal that controls the sampling phase of the line offset subsample.