JPS6218900U - - Google Patents
Info
- Publication number
- JPS6218900U JPS6218900U JP10807285U JP10807285U JPS6218900U JP S6218900 U JPS6218900 U JP S6218900U JP 10807285 U JP10807285 U JP 10807285U JP 10807285 U JP10807285 U JP 10807285U JP S6218900 U JPS6218900 U JP S6218900U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- hold
- track
- sampling head
- sampler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
- Electronic Switches (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案によるサンプラ回路の回路図、
第２図は第１図に示したサンプラ回路の動作説明
図、第３図は従来のサンプラ回路の回路図、第４
図は第３図に示した回路の動作説明図である。
２：ダイオードブリツジ、９，１６，２０：ホ
ールドコンデンサ、３：サンプリングヘツド、２
３：サンプリングパルス発生器、２４：タイミン
グ信号発生器。
Figure 1 is a circuit diagram of a sampler circuit according to the present invention.
Figure 2 is an explanatory diagram of the operation of the sampler circuit shown in Figure 1, Figure 3 is a circuit diagram of a conventional sampler circuit, and Figure 4 is an illustration of the operation of the sampler circuit shown in Figure 1.
This figure is an explanatory diagram of the operation of the circuit shown in FIG. 3. 2: Diode bridge, 9, 16, 20: Hold capacitor, 3: Sampling head, 2
3: Sampling pulse generator, 24: Timing signal generator.
Claims (1)
ングヘツドと、前記サンプリングヘツドに接続さ
れたトラツク／ホールド回路と、前記トラツク／
ホールド回路に接続されて前記サンプリングヘツ
ドへのバイアス電圧を変化させるバイアス回路と
より成るサンプラ回路。 (2) 前記トラツク／ホールド回路はスイツチと
ホールド素子とより成る実用新案登録請求の範囲
第１項記載のサンプラ回路。 (3) 前記トラツク／ホールド回路は直列接続さ
れた第１、第２トラツク／ホールド回路より成り
、各回路のスイツチは異なる時点でオン状態にさ
れる実用新案登録請求の範囲第２項記載のサンプ
ラ回路。 (4) 前記バイアス回路は前記サンプリングヘツ
ドへの２個の電圧値の平均値がホールド電圧に等
しくなるように制御する実用新案登録請求の範囲
第３項記載のサンプラ回路。[Claims for Utility Model Registration] (1) A sampling head including a switch and a hold element, a track/hold circuit connected to the sampling head, and a track/hold circuit connected to the sampling head.
A sampler circuit comprising a bias circuit connected to a hold circuit to vary a bias voltage to the sampling head. (2) The sampler circuit according to claim 1, wherein the track/hold circuit comprises a switch and a hold element. (3) The sampler according to claim 2, wherein the track/hold circuit comprises first and second track/hold circuits connected in series, and the switches of each circuit are turned on at different times. circuit. (4) The sampler circuit according to claim 3, wherein the bias circuit is controlled so that the average value of two voltage values applied to the sampling head is equal to the hold voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10807285U JPH0337200Y2 (en) | 1985-07-15 | 1985-07-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10807285U JPH0337200Y2 (en) | 1985-07-15 | 1985-07-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6218900U true JPS6218900U (en) | 1987-02-04 |
| JPH0337200Y2 JPH0337200Y2 (en) | 1991-08-06 |
Family
ID=30984928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10807285U Expired JPH0337200Y2 (en) | 1985-07-15 | 1985-07-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0337200Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01239469A (en) * | 1987-11-16 | 1989-09-25 | Analytek Ltd | Quantization of transient phenomenon and 10 giga sample/sec 2 stage analog memory integrated circuit for imaging oscillography |
| JPH04182997A (en) * | 1990-11-16 | 1992-06-30 | Inter Nitsukusu Kk | High-speed sample-hold circuit |
-
1985
- 1985-07-15 JP JP10807285U patent/JPH0337200Y2/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01239469A (en) * | 1987-11-16 | 1989-09-25 | Analytek Ltd | Quantization of transient phenomenon and 10 giga sample/sec 2 stage analog memory integrated circuit for imaging oscillography |
| JPH04182997A (en) * | 1990-11-16 | 1992-06-30 | Inter Nitsukusu Kk | High-speed sample-hold circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0337200Y2 (en) | 1991-08-06 |