JPS6218757U - - Google Patents
Info
- Publication number
- JPS6218757U JPS6218757U JP11118485U JP11118485U JPS6218757U JP S6218757 U JPS6218757 U JP S6218757U JP 11118485 U JP11118485 U JP 11118485U JP 11118485 U JP11118485 U JP 11118485U JP S6218757 U JPS6218757 U JP S6218757U
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- output
- microcomputer
- outputs
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000007599 discharging Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第1図は本考案実施例の暴走検出回路を含む装
置を示す概略図、第2図はそのマイクロコンピユ
ータの動作を示すフローチヤート、第3図及び第
4図はそれぞれ本実施例の暴走検出時の動作を示
すタイムチヤートである。
4;マイクロコンピユータ、8;暴走検出回路
、C1,R1;第1の充放電回路、C2,R2,
R3,D1,IN1;第2の充放電回路、AN1
;論理回路。
FIG. 1 is a schematic diagram showing a device including a runaway detection circuit according to an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the microcomputer, and FIGS. 3 and 4 are respectively at the time of runaway detection according to the present embodiment. This is a time chart showing the operation. 4; microcomputer, 8; runaway detection circuit, C 1 , R 1 ; first charging/discharging circuit, C 2 , R 2 ,
R 3 , D 1 , IN 1 ; second charging/discharging circuit, AN 1
;Logic circuit.
Claims (1)
ス信号を出力するマイクロコンピユータの暴走検
出回路において、 マイクロコンピユータからのパルス信号が入力
され、所定の周期でパルス信号が出力されている
間は充放電動作を繰り返すとともに、パルス信号
が正常に入力されなくなるとそれぞれ所定レベル
以上に充電もしくは放電される第1及び第2の充
放電回路と、 第1及び第2の充放電回路の出力が入力され、
両出力とも所定レベル以上に充電もしくは放電さ
れているときに出力信号を出す論理回路と、 を備えたことを特徴とするマイクロコンピユータ
の暴走検出回路。[Claim for Utility Model Registration] In a runaway detection circuit of a microcomputer that outputs a pulse signal at a predetermined period under normal operation, a pulse signal from the microcomputer is input, and the pulse signal is output at a predetermined period. first and second charging and discharging circuits that repeat charging and discharging operations while the pulse signal is being output, and are charged or discharged to or above a predetermined level, respectively, when the pulse signal is no longer input normally; The output of the discharge circuit is input,
A runaway detection circuit for a microcomputer, comprising: a logic circuit that outputs an output signal when both outputs are charged or discharged to a predetermined level or higher;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11118485U JPS6218757U (en) | 1985-07-19 | 1985-07-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11118485U JPS6218757U (en) | 1985-07-19 | 1985-07-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6218757U true JPS6218757U (en) | 1987-02-04 |
Family
ID=30990871
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11118485U Pending JPS6218757U (en) | 1985-07-19 | 1985-07-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6218757U (en) |
-
1985
- 1985-07-19 JP JP11118485U patent/JPS6218757U/ja active Pending
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