JPS62184558A - Interface device - Google Patents

Abstract

PURPOSE:To comparatively easily obtain a conversion interface device with universality by providing a ROM in which a data corresponding to each of control signals of a master side processor and a slave side device is stored in its inside. CONSTITUTION:A ROM8 is built in a conversion interface device 7, and data corresponding to the control signals of the master side processor 1 and of a prescribed slave side I/O2 are stored in the ROM. For example, when the control signal from the processor 1 is transmitted to the I/O2 with a control bus 5, the data stored in the ROM8 is read out with the control signal. A prescribed control signal is obtained from the data, thereby the I/O2 being controlled, and simultaneously, the prescribed control signal is sent to an address bus 3, and a data bus 4. By controlling the buses, a prescribed control from the processor 1 to the I/O2, such as a data transfer, etc., can be performed. When the class of the I/O2 is changed, the titled device can be used by changing the storing content of the ROM8.

Description

[Detailed Description of the Invention] [Summary] A conversion interface device provided in a control bus connecting a main processor and a slave device includes a read-only memory, and stores data corresponding to control signals for both devices. It is an interface device.

[Field of Industrial Application] The present invention is a conversion interface that converts control signals, etc. so that when a main processor and a slave device are connected by various buses, when one device is changed, the other device can be used as is. Regarding equipment.

[Prior Art] When data is transferred via multiple buses, such as between a microprocessor and an input/output device, three types of connection buses are used: an address bus, a data bus, and a control bus, each using several bits. ing.

The input/output device operates by accepting only predetermined data according to the configuration of the corresponding microprocessor. However, since there are many types of microprocessors on the market, when replacing the microprocessor for convenience, it would be a big waste to replace all the input/output devices with compatible ones, so as shown in Figure 4, it is converted to a control bus. We have established a department. That is, the fourth
In the figure, 1 is the main microprocessor, 2 is the slave input/output device 3 is the address bus, 4 is the data bus, 5 is the control bus for the input/output device, 6 is the control bus for the microprocessor, and 7 is the control bus for the microprocessor. 3 shows a conversion interface device. Therefore, the conversion interface device 7 is required when replacing the microprocessor/input/output device.
It is not always used at the beginning of the design.

[Problems to be Solved by the Invention] When the conversion interface device 7 is required, its design naturally requires knowledge of both the microprocessor 1 side and the input/output device 2 side. When changing one or both of the microprocessor and input/output device, it was necessary to design and manufacture a separate conversion section suitable for the change. That is, the procedure for putting data on the bus and the notification that data has been received are converted into a state that can be understood by the vaporizer. Since the conversion interface device is extremely complex, such as combining a plurality of logical operation circuits into a dedicated circuit, the conversion device lacks versatility and is expensive.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and provide a versatile conversion interface device with a relatively simple configuration.

[Means for solving problems] FIG. 1 is a block diagram showing the configuration of the present invention.

In FIG. 1, 1 is a main microprocessor, 2 is a slave input/output device, 3 is an address bus, 4 is a data bus, and 5.
6 is a control bus, and 7 is a conversion interface device provided in the control bus. The above is a conventional device that performs processing such as data transfer, and the present invention has a built-in read-only memory 8 in the signal conversion interface device 7, and the memory 8 stores control signals of the main processor and a predetermined slave input/output device. It stores the corresponding data.

[Operation] For example, when a control signal from the master microprocessor 1 is transmitted to the slave input/output device 2 via the control bus 5, data stored in the read-only memory 8 is read out by the control signal. A predetermined control signal is obtained from the data to control the slave input/output device 2, and at the same time, a predetermined control signal is sent to the address bus 3 and data bus 4. By controlling the bus, the master microprocessor 1 can perform predetermined control such as data transmission and reception to the slave input/output device 2.

Even when the type of slave input/output device 2 is further changed, it can be used as appropriate by changing the contents stored in the read-only memory 8.

[Example Figure 2 shows the conversion ink shown in Figure 1 as an example of the present invention.
FIG. 2 is a diagram specifically showing the configuration of the F2S device 7 and the read-only memory 8. FIG. In FIG. 2, everything except the read-only memory 8 is provided inside the conversion interface device, and almost the same components as in FIG. 2 are also provided in the control bus 6. In FIG. 2, 1) is a significant signal generator, 12 is a significant signal processor, 13 is a map, 14 is a buffer, 15 is a comparator, and 16
indicates force. When a significant signal is input to the map 13, corresponding instruction read information is obtained, and 2' flag bits are provided in the lower order. Flag 1 is an error bit, which is used to generate a prohibition state when a device is instructed to read a signal that cannot be transmitted. Flag 2 is a definition bit, and is turned off when it is outside the definition and when the previous state is to be retained. The significant signal processing unit 12 is active at L level, as shown in the example shown in the margin.
A table is defined for processing significant signals such as active at H level and active at rising and falling levels. H and L level signals from main processor 1 and signal processing unit 1
By applying the signal from 2 to the significant signal generator 1), it is output as a significant signal ON/OFF bit string, the map 13 is indexed, and the instruction for the memory 8 is retrieved. Buffer 14 has the definition bit in map 13 on,
In addition, a value different from the previous value is fetched and passed to the counter 16. The buffer 14 is used to align the operation sequence of input instructions and processing instructions of the read-only memory 8. Comparator 15 determines whether the significant signals have the same value or different values. The counter 16 reads out the start address of a predetermined instruction from the read-only memory 8 based on the value stored at the beginning of the instruction. Since the contents read from the read-only memory 8 are the Z signal for setting the address bus 3 and data bus 4 to a high impedance state and the control data for the slave input/output device 2, a predetermined control operation is performed. be able to.

More specifically, the name of the main microprocessor 1 is 280.
When the slave side input/output bag W2 is of the MC6800 type, the command signals correspond as shown in the table below.

780 MC6800 RD, WRR/W, Φ2 MRE Ro, l0REQ V
M AB U S RE Q TSC,RB
E, (HALT) BUSAK BA WAIT None HALT None In the first Z80, RD and WR are executed using (read/write) signal line data and its timing, whereas in MC6
In the case of 800, it is determined by the read or write level and the presence or absence of a strobe signal, and the last HALT is not used in the other case. Therefore, map 13 stores the data on the left side of FIG. 3, and read-only memory 8 stores the data on the right side of FIG. Read the microcode to be used. This signal becomes a predetermined control signal for the input/output device for MC6800.

[Effects of the Invention] Thus, according to the present invention, when the main processor or the slave input/output device is changed, each control signal can be converted and operated by the conversion interface device having a read-only memory. I can do it. Furthermore, when changing models, all you have to do is rewrite the contents stored in memory.
It is a versatile interface device because it can be easily adapted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a conversion interface device 7 in FIG. 1 as an embodiment of the present invention.
FIG. 3 is a diagram showing an example of the map shown in FIG. 2 and data stored in the memory. FIG. 4 is a diagram showing a conventional ink face device. 1 - Main side microprocessor 2 - Slave side input/output device 3 - Address bus 4 - Data bus 5.6 - Control bus 7 - Conversion interface device 8 - Read-only memory Patent applicant Fujitsu Limited Representative Patent attorney Suzuki Eisuke Figure 1 Map 13 +00100 1 100+01 1 100 units 01 +001) 1 1 + 01000 1 10100+ 1 + 01010 1 1 word 0101) 1 1 1000+ 1 1) 001) + 1) 101) (+) 1) 1 word 001 1 ) Electrical 1) 'Ol 7 3rd Read-only memory 8

Claims (1)

[Claims] When performing processing operations between the main processor (1) and the slave device (2) using the address bus (3), data bus (4), and control signal buses (5) and (6), Main processor (1)
・In the interface device (7), which is equipped with a signal conversion interface in the control signal bus for performing signal format conversion between the slave devices (2), the main processor (1) is installed in the interface device (7).
) and a predetermined slave device (2).