JPS62183649A - Carrier control circuit - Google Patents
Carrier control circuitInfo
- Publication number
- JPS62183649A JPS62183649A JP61026328A JP2632886A JPS62183649A JP S62183649 A JPS62183649 A JP S62183649A JP 61026328 A JP61026328 A JP 61026328A JP 2632886 A JP2632886 A JP 2632886A JP S62183649 A JPS62183649 A JP S62183649A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- output
- modulation
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 23
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 3
- 239000012050 conventional carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 206010012735 Diarrhoea Diseases 0.000 description 1
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はデータ伝送を行なうための送信機に関し、特に
ＦＳＫ変調方式の送信機のキャリア制御回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transmitter for transmitting data, and particularly to a carrier control circuit for a transmitter using an FSK modulation method.
従来、この種の方式には、Ｆ；’ Ｓ Ｋ変調回路の発
振器を制御して発振及び発振停止の動作をさせる方式と
、変調回路の出力をゲーＩ・回路で制御する方式とがあ
る。第３図は後者の方式による従来のキャリア制御回路
を含む送信機の回路図である。Conventionally, this type of system includes a system in which the oscillator of the F;'SK modulation circuit is controlled to perform oscillation and oscillation stop operations, and a system in which the output of the modulation circuit is controlled by a gate I circuit. FIG. 3 is a circuit diagram of a transmitter including a conventional carrier control circuit according to the latter method.
第４図は第３図の動作を示す波形図である。第３図のＦ
ＳＫ変調器１２の出力１６と制御信号入力端子１３の制
御信号１７との論理積により、送信制御されたキャリア
１８が論理積回路１４の出力に得られ、この出力は次段
の帯域通過ろ波器１５によって直流成分と帯域外の高調
波成分の除去されたキャリア信号となり、伝送路へ送出
される。FIG. 4 is a waveform diagram showing the operation of FIG. 3. F in Figure 3
By ANDing the output 16 of the SK modulator 12 and the control signal 17 of the control signal input terminal 13, a transmission-controlled carrier 18 is obtained at the output of the AND circuit 14, and this output is passed through the bandpass filter in the next stage. The carrier signal is converted into a carrier signal from which DC components and out-of-band harmonic components are removed by the converter 15, and is sent to a transmission path.
上述した従来のキャリア制御回路では、送信キャリアの
送出を停止しよ・うとする際に、送信制御信号が送信か
ら送信停止状態に変化する時点の変調キャリアとの位相
関係によっては変調器の変調波形が正しく伝送されない
場合がある。すなわち第４図のキャリア１８で示される
が如く、制御信号１７がＯＮからＯＦＦとなれ時点での
キャリア１８の最後の半周期は変調器の出力１６に比べ
て短かくなる場合があり、この半周期はＦ Ｓ Ｋ変調
方式においては高い周波数の信号として伝送されるため
、受信機においては高い周波数の極性が復調再生される
ことになり、送信機の変調器に入力されたデータ信号の
極性とは異なるので、データ伝送上誤りビットとなった
り、又はエクストラビ・ソトと呼ばれる余分なビットが
生じる欠点がある。In the conventional carrier control circuit described above, when attempting to stop transmitting the transmission carrier, the modulation waveform of the modulator changes depending on the phase relationship between the transmission control signal and the modulation carrier at the time when the transmission control signal changes from transmission to transmission stop state. may not be transmitted correctly. That is, as shown by the carrier 18 in FIG. 4, the last half cycle of the carrier 18 at the time when the control signal 17 changes from ON to OFF may be shorter than the output 16 of the modulator. Since the period is transmitted as a high frequency signal in the FSK modulation method, the polarity of the high frequency is demodulated and reproduced at the receiver, and it is different from the polarity of the data signal input to the transmitter's modulator. Since the numbers are different, there is a drawback that error bits may occur during data transmission, or extra bits called extra bits may occur.
本発明のキャリア制御回路は、ＦＳＫ変調器の変調信号
をクロック入力とし送信制御信号をデータ入力とするＤ
フリップフロップと、前記Ｄフリップフロップの出力信
号と前記送信制御信号との論理和出力信号を得る論理和
回路と、前記変調信号と前記論理和出力信号との論理積
出力信号を得る論理積回路とを具備することを特徴とす
る。The carrier control circuit of the present invention is a D
a flip-flop, an OR circuit that obtains an OR output signal of the output signal of the D flip-flop and the transmission control signal, and an AND circuit that obtains an AND output signal of the modulation signal and the OR output signal. It is characterized by comprising the following.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の回路図、第２図は第１図の
動作を示す波形図である。第１図において、Ｆ Ｓ Ｘ
変調器１でＦ Ｓ Ｋ変調された矩形波の変調信号７を
Ｄフリップフロ・ツブ３のクロ・Ｖり入力端子と論理積
回路５の第一の入力端子に入力し、Ｄフリップフロップ
３の出力信号９を論理和回路４の第一の入力端子に入力
し、送信制御信号８をＤフリップフロップのデータ入力
端子と論理和回路の第二の入力端子に入力し、論理和回
路４の出力信号を論理積回路５の第二の入力端子に入力
して、論理積回路５の出力に送信制御されたＦＳＫ変調
波を出力されるように構成し、送信制御されたＦ Ｓ
Ｋ変調波は帯域通過ろ波器６によって直流成分と帯域外
の高調波成分の除去されたキャリア信号となり伝送路へ
送出される。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operation of FIG. 1. In Figure 1, F S
The rectangular wave modulation signal 7 subjected to FSK modulation by the modulator 1 is input to the black/V input terminal of the D flip-flop block 3 and the first input terminal of the AND circuit 5, and the output of the D flip-flop 3 is The signal 9 is input to the first input terminal of the OR circuit 4, the transmission control signal 8 is input to the data input terminal of the D flip-flop and the second input terminal of the OR circuit, and the output signal of the OR circuit 4 is inputted. is input to the second input terminal of the AND circuit 5, and the transmission-controlled FSK modulated wave is outputted to the output of the AND circuit 5.
The K modulated wave becomes a carrier signal from which DC components and out-of-band harmonic components are removed by a bandpass filter 6, and is sent to a transmission path.
送信制御信号８がＯＦＦからＯＮになるとこの直後のＦ
ＳＫ変調波７の最初のＯから１／＼の立上り縁でＤフリ
ップフロップの出力信号９はＯから１の状態に変化する
。この状態は送信制御信号８がＯＮからＯＦＦ状態に変
化し、この直後のＦＳＫ変調波７の最初の０から１への
立上り縁まで保持される。Ｄフリップフロップの出力信
号つと送信制御信号８との論理和をとり、更にこの論理
和出力信号１０とＦ Ｓ Ｋ変調器出力信号との論理積
出力信号１１には、送信制御信号８がＯＮがらＯＦＦに
なった時点でもＦ Ｓ Ｘ変調器の出力と同じ＜Ｒ１＆
の半周期Ｔが出力される。この最後の半周期が変調器出
力と比べて短かくことはなく、従って高い帯域内周波成
分の発生送出を避けることができる。When the transmission control signal 8 turns from OFF to ON, the F immediately after this
At the first rising edge of the SK modulated wave 7 from O to 1/\, the output signal 9 of the D flip-flop changes from O to 1 state. This state is maintained until the transmission control signal 8 changes from an ON state to an OFF state, and until the first rising edge of the FSK modulated wave 7 from 0 to 1 immediately thereafter. The output signal of the D flip-flop is logically summed with the transmission control signal 8, and the logical product output signal 11 of this logical sum output signal 10 and the FSK modulator output signal is generated while the transmission control signal 8 is ON. Even when it is turned off, the same as the output of the F S X modulator <R1&
A half period T is output. This last half-period is not short compared to the modulator output, so that generation and transmission of high in-band frequency components can be avoided.
以上説明したように本発明のキャリア制御回路によれば
、キャリアを送信し終える時に高周波成分を発生せず、
従って最後のデータ信号まで正確に伝送できるため、受
信機では最後のデータ信号まで正確に復調再生できる効
果があると共に、データ伝送終了後に発生しやすいエク
ストラビットを生じにくくする効果がある。As explained above, according to the carrier control circuit of the present invention, high frequency components are not generated when transmitting the carrier,
Therefore, since it is possible to accurately transmit up to the last data signal, the receiver can accurately demodulate and reproduce up to the last data signal, and it also has the effect of making it difficult to generate extra bits that tend to occur after data transmission is completed.
第１図は本発明の一実施例の回路図、第２図は第１図の
動作を示す波形図、第３図は従来例の回路図、第４図は
第３図の動作を示す波形図である。
１．１２・・・ＦＳＫ変調器、２．１３−・・制御信号
入力端子、３・・・Ｄフリップフロップ、４・・・論理
和回路、５．１４・・・論理積回路、６．１５・・・帯
域通過ろ波器。
竿 １ 圓
４・−・論理刺獣烙５・・・痢廁剃路Ｉ・・・邦ル１祠
茹号第 ３ 圀Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a waveform diagram showing the operation of Fig. 1, Fig. 3 is a circuit diagram of a conventional example, and Fig. 4 is a waveform diagram showing the operation of Fig. 3. It is a diagram. 1.12...FSK modulator, 2.13-...control signal input terminal, 3...D flip-flop, 4...OR circuit, 5.14...AND circuit, 6.15 ...Bandpass filter. Rod 1 En 4 -- Logical Sashiju Fan 5 ... Diarrhea Road I ... Country Ru 1 Shrine No. 3
Claims (1)
号をデータ入力とするＤフリップフロップと、前記Ｄフ
リップフロップの出力信号と前記送信制御信号との論理
和出力信号を得る論理和回路と、前記変調信号と前記論
理和出力信号との論理積出力を得る論理積回路とを具備
することを特徴とするキャリア制御回路。a D flip-flop having a modulation signal of an FSK modulator as a clock input and a transmission control signal as a data input; an OR circuit for obtaining an OR output signal of the output signal of the D flip-flop and the transmission control signal; and the modulation circuit. A carrier control circuit comprising an AND circuit that obtains an AND output of a signal and the OR output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61026328A JPS62183649A (en) | 1986-02-07 | 1986-02-07 | Carrier control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61026328A JPS62183649A (en) | 1986-02-07 | 1986-02-07 | Carrier control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62183649A true JPS62183649A (en) | 1987-08-12 |
Family
ID=12190351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61026328A Pending JPS62183649A (en) | 1986-02-07 | 1986-02-07 | Carrier control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62183649A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009055182A (en) * | 2007-08-24 | 2009-03-12 | Hitachi Kokusai Electric Inc | Reference signal switching circuit |
-
1986
- 1986-02-07 JP JP61026328A patent/JPS62183649A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009055182A (en) * | 2007-08-24 | 2009-03-12 | Hitachi Kokusai Electric Inc | Reference signal switching circuit |
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