JPS62183145A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPS62183145A JPS62183145A JP61024333A JP2433386A JPS62183145A JP S62183145 A JPS62183145 A JP S62183145A JP 61024333 A JP61024333 A JP 61024333A JP 2433386 A JP2433386 A JP 2433386A JP S62183145 A JPS62183145 A JP S62183145A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- lead frame
- layer ceramic
- positioning
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims abstract description 24
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000003340 mental effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明はＩＣ１特に固体撮像素子のパッケージの構造に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a package for an IC 1, particularly a solid-state image sensor.
本発明は、ＩＣ，ｔｒｆに位置決め用の穴カ、リードフ
レームに形成された固体撮１象素子のパッケージにおい
て、リードフレームの下に構成される第１層セラミック
の穴の大きさを、リードフレームに形成した穴よりも若
干大きくすることにより、パッケージを実装基板にネジ
止めする際の強度を上げるものである。In the present invention, the size of the hole in the first layer ceramic formed under the lead frame is adjusted by adjusting the size of the hole in the first layer ceramic formed under the lead frame in a package of a solid-state sensor element formed in a lead frame. The hole is made slightly larger than the hole formed in the hole to increase the strength when screwing the package to the mounting board.
従来の固体撮像素子用のパッケージは、第２図のように
、第２層セラミック板（第２図（ａ））、リードフレー
ム（第２図（１＋） ） 、第１層セラミック板（第２
図（Ｃ））で構成されており、リードフレームにあけた
位置決め用穴＋２１ ′！ｉ−用いて、パッケージとパ
ッケージを実装する基板との位置決めを行なうようにな
っており、第１層セラミックと、第２層セラミックの切
れ欠き＋３１ ＋４１は同じ大きさとなっている。As shown in Fig. 2, a conventional package for a solid-state image sensor includes a second layer ceramic plate (Fig. 2 (a)), a lead frame (Fig. 2 (1+)), and a first layer ceramic plate (Fig. 2 (1+)).
Figure (C)) consists of a positioning hole drilled in the lead frame +21'! i- is used to position the package and the substrate on which the package is mounted, and the notches +31 to +41 in the first layer ceramic and the second layer ceramic have the same size.
しかし、前述の従来技術では、リードフレームのみで位
置決めを行なうネジをささえる構造となっているためネ
ジの強度が確保されないという問題点を有する。そこで
本発明は、このような問題点を解決するもので、その目
的とするところは、位置決めの穴を用いてネジ止めをす
る際にネジ止めの強度全大幅に大きくできるＩＣパッケ
ージを提供するところにある。However, the above-mentioned conventional technology has a structure in which the screw for positioning is supported only by the lead frame, so there is a problem that the strength of the screw cannot be ensured. SUMMARY OF THE INVENTION The present invention aims to solve these problems, and its purpose is to provide an IC package that can significantly increase the overall strength of screwing when screwing using positioning holes. It is in.
〔問題点ｔ−解決する几めの手段］
本発明のＩＣパッケージは第１層セラミックの切り欠き
の大きさをリードフレームにあけ念位置決め用の穴と同
一の大きさか、又は、若干大きな大きさとし、第２層セ
ラミックの切り火きと変えることを特徴とする。[Problem t - Elaborate means for solving the problem] In the IC package of the present invention, the size of the notch in the first layer ceramic is made to be the same size as the hole for mental positioning made in the lead frame, or to be slightly larger. , characterized by replacing the second layer with a ceramic cutter.
本発明の上記の構成によれば１位置決めはリードフレー
ムにあけた穴でおこないｓ 第１−セラミックの穴、又
は切シ欠きてネジをささえることにより、ネジ止めの強
度を大きくすることができる。According to the above-described structure of the present invention, the first positioning is performed using a hole drilled in the lead frame, and the strength of the screw fixing can be increased by supporting the screw using a ceramic hole or a notch.
第１図は本発明の実施例における構成図である。 FIG. 1 is a block diagram of an embodiment of the present invention.
第１図（ａ）は、第２層セラミック板であシ、第１図（
ｂ）はリードフレームである。以上は従来と同様である
。第１図（ｃ）か本実施例の特徴を示す第１層セラミッ
ク板である。Fig. 1(a) shows the second layer ceramic plate and Fig. 1(a).
b) is a lead frame. The above is the same as before. FIG. 1(c) is a first layer ceramic plate showing the features of this embodiment.
このように、第１図（ｂ）のリードフレームにあけた位
置決め用の穴２と同一の大きさか、または若干大きな穴
１を第１図（ｃ）の第１層セラミック板に゛形成する。In this way, a hole 1 of the same size or slightly larger than the positioning hole 2 drilled in the lead frame of FIG. 1(b) is formed in the first layer ceramic plate of FIG. 1(c).
なお、この第１図（Ｃ）の第１層セラミック板の穴は１
点線で示すように切り欠きとしてもよい。Note that the holes in the first layer ceramic plate in Fig. 1(C) are 1
It may also be a cutout as shown by the dotted line.
以上述べたように本発明によれば、第１層セラミックに
あける穴、又は切れ欠きをリードフレームにあけた位置
決め用の穴よりも若干大きな大きさとすることにより、
ネジ止めの強［ｋ大きくできるという効果を有する。As described above, according to the present invention, by making the hole or notch made in the first layer ceramic slightly larger than the positioning hole made in the lead frame,
It has the effect of increasing the strength of screw fixing.
第１図（ａ）〜（Ｃ）は本発明によるＩＣパッケージの
実施例の構成図。
第２図（ａ）〜（Ｃ）は従ｆ例による工Ｃパッケージの
構成図。
１・・・本発明の実施例の第１層セラミックの穴２・・
・リードフレームにあけた位置決め用穴３・・・従来例
の第１層セラミックの穴４・・・第２１−セラミックの
切り欠き以 上
他１名
第１咽（α）
箋４田（ｂ）
竿１１）（こ〕FIGS. 1(a) to 1(C) are configuration diagrams of an embodiment of an IC package according to the present invention. FIGS. 2(a) to 2(C) are configuration diagrams of a construction C package according to a conventional example. 1... Holes in the first layer ceramic of the embodiment of the present invention 2...
・Positioning hole 3 drilled in the lead frame... Hole 4 in the first layer ceramic of the conventional example... Notch 21-ceramic or above 1 other person 1st hole (α) 4th hole (b) Rod 11) (ko)
Claims (1)
フレームと、前記リードフレームをはさむように、第１
層セラミックと第２層セラミックで構成されるパッケー
ジにおいて、該第１層セラミックの穴の大きさが前記リ
ードフレームにあけた穴と同一の大きさか、又は若干大
きいことを特徴とするＩＣパッケージ。A lead frame having at least one hole for positioning, and a first lead frame sandwiching the lead frame.
An IC package comprising a ceramic layer and a ceramic second layer, wherein the hole in the first ceramic layer is the same size as the hole drilled in the lead frame or slightly larger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61024333A JPS62183145A (en) | 1986-02-06 | 1986-02-06 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61024333A JPS62183145A (en) | 1986-02-06 | 1986-02-06 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62183145A true JPS62183145A (en) | 1987-08-11 |
Family
ID=12135252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61024333A Pending JPS62183145A (en) | 1986-02-06 | 1986-02-06 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62183145A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5861654A (en) * | 1995-11-28 | 1999-01-19 | Eastman Kodak Company | Image sensor assembly |
| US5998878A (en) * | 1995-07-13 | 1999-12-07 | Eastman Kodak Company | Image sensor assembly and packaging method |
-
1986
- 1986-02-06 JP JP61024333A patent/JPS62183145A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5998878A (en) * | 1995-07-13 | 1999-12-07 | Eastman Kodak Company | Image sensor assembly and packaging method |
| US5861654A (en) * | 1995-11-28 | 1999-01-19 | Eastman Kodak Company | Image sensor assembly |
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