JPS62180593A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the time necessary to the test for screening by providing a driving means to be able to drive simultaneously plural word lines so as to select plural memory cells. CONSTITUTION:For respective gate circuits G of an X decoder 3, FETQB is respectively interposed between respective FETQ1,... QN and a low electric potential electric power source VSS, and the FETQB and a comparator 4 constitute a screening driving means 5. When the burn-in test for the screening is executed, with an external address signal A as the electric potential of a reference voltage signal VS or above, the output of the comparator 4 is made into the low electric potential of a threshold voltage or below of respective FETQB. For such a reason, the FETQB comes to be an off condition, and when a precharging signal phiP is a high electric potential, respective nodal points N of respective gate circuits G maintain the high electric potential. Thus, an internal signal phiA comes to be the high electric potential, and then, all word lines W are simultaneously driven and by driving a bit line B, plural memory cells are selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor memory device such as MO8RAM, and more particularly to a semiconductor memory device suitable for efficient screening.

[Conventional technology]

Generally, semiconductor devices are subjected to a burn-in test in which a bias voltage is applied in a cool-temperature atmosphere as a screening process, but recent semiconductor memory devices (hereinafter referred to as MO8C AM) are subjected to even more electrical stress. Dynamic burn-in tests have been conducted to provide more effective screening.

Conventionally, MO8RAM was screened for this strain.
For example, the one shown in FIG. 2 is known. In FIG. 2, 1 is a cell matrix in which memory cells are arranged in rows and columns, and the memory cells of cell matrix 1 are connected to a plurality of N word lines W and a plurality of M bit lines B.

Note that N and M are integers of 2 or more, and word lines W and bit lines B are specified by adding subscripts. Each word line W is an MO8 field effect transistor i (hereinafter abbreviated as FET) Q* + (h+ ---
The bit line B is connected to the X decoder 3 via QNk, and similarly, the bit line B is connected to the Y decoder 2.

The X decoder 3 has the same number of gate circuits G (specified by adding a subscript) as the number N of word lines W, and the gate circuits G
are connected to the corresponding word line W via FETQt* ---QN.

The gate circuit G includes N FETs connected in parallel to the FETQP to which the precharge signal φP is input to the gate.
Q +t + ---QIN @these N
The FET Q + t + --- QIN are used for the address signals X, , X2 . X3. ---
XN is input to each gate. These FETQ
P and I" E T Q■+ Qtz + ---Q
IN is connected in series between the high potential power supply Vjc and the low potential power supply VSS, and these FETQp and FETQtt
r --- Node N 1 e set between QIN
---N N is FET Q-ho respectively.

=-Connected to the gate of QN. These Fh T
Q r + ---QN is connected to the source or word line W, and an internal signal φ that shifts to a high potential during read and write operations is input to the drain. In addition.

Each gate circuit G receives an input address signal X, --XN
The configuration is the same except for the Y decoder 2, and the Y decoder 2 also has a well-known configuration, so explanation and illustration thereof will be omitted.

In such a M08RAM, when the precharge signal φP before a read or write operation is at a high potential, each gate circuit G
The node N of the address signal
For example, when Xl (the same applies hereinafter) shifts to a high potential, the nodes N of other gate circuits G except the corresponding gate circuit Gsk shift to a low potential. Therefore, when the internal signal φA becomes a high potential, the word line W1 is selected, that is, driven, by the first scanning FET Qt in the on state. And similarly 1
One bit line B is driven and a memory cell is selected.

[Problems to be solved by this invention] However,
In such conventional semiconductor memory devices, even when performing a burn-in test under electrical stress, that is, when a memory cell is selected, each word line is It is necessary to select memory and reset bits one by one by sequentially driving the memory and bit lines, and there is a problem that the test requires a lot of time and screening cannot be carried out efficiently. Ta. In particular, in recent years, as the number of memory cells in semiconductor memory devices has increased, the above-mentioned problems have become more prominent and a solution has been desired.

[Means for solving problems]

This invention was made in view of the above problems, and involves connecting a plurality of memory cells to a plurality of word lines and a plurality of bit lines in a matrix, respectively, and driving the word lines and bit lines to drive the memory cells. The semiconductor memory device to be selected is characterized in that a sliding hand &1- is provided which can simultaneously drive a plurality of the word blocks.

[For production]

According to the semiconductor memory device according to the present invention, a plurality of word lines can be simultaneously driven to select a plurality of memory cells when performing a final screening test. Therefore, the time required to simulate the test can be shortened, and screening can be carried out efficiently.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention. Hereinafter, the same parts as those of the conventional semiconductor memory device shown in FIG. 1 will be described with the same reference numerals.

As shown in the figure, each gate circuit jlG of the X decoder 3 has a low tt position I
A FETQa (identified with a subscript as shown in the figure) is interposed between the FETQa and the JLIA Vss.

These FETQB have drains connected to each FETQ,
breath.

---The source of QN, the source is low potential to the source V8S,
Further, the gate is connected to the comparator 4.

The comparator 4 receives an external address signal and a reference voltage signal s to its input terminal, and maintains its output at a low potential when the external address signal A is at a higher potential than the reference voltage signal v8. The above-mentioned FETQB and comparator 4 constitute the screening drive means 5. Note that the reference voltage signal ■S is read.

The upper limit is set to a level of potential that is permissible during a write operation.

In such a semiconductor memory device, when performing a screening burn-in test, the external address signal A is set to a potential higher than the reference voltage signal Vs, and the output of the comparator 4 is set to a low potential lower than the threshold voltage of each FETQ. Therefore, each FETQB is turned off, and the precharge signal φ
When P is at a high potential, each node N of each gate circuit G of the X decoder 3 maintains a high potential. , As a result, when the internal signal φA becomes a high potential, each FET Q1 . Q weight *---All word lines W are driven simultaneously by Qw, and then bit #
By driving B, a plurality of memory cells are selected. Therefore, a burn-in test can be performed in a short time, and screening can be performed efficiently.

On the other hand, 1. Normal read and write operations can be performed in the same manner as in the prior art described above, provided that the external address signal A''i is maintained at a potential lower than the reference voltage signal vs.

Note that the screening driving means is not limited to the above-mentioned configuration; for example, each FET, whose gate receives a control signal, is connected between a terminal to which an internal signal φA is input and a word line W. M T Q t
e --- It can also be configured by providing it in parallel with QN.

Further, it is also possible to directly apply a voltage g that becomes a low potential during a burn-in test to the gate of each FET QB described above, without using the comparator 4.

〔effect〕

As described above, according to the semiconductor memory device according to the present invention, the time required for testing for screening can be shortened and screening can be performed efficiently.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional semiconductor memory device. 1...Cell matrix, 2...Y decoder, 3...Xf decoder 4...Comparator, 5...Screening drive means, W
・・・・・・Word line, B・・・・・・Pit line, Q
B...PET. Agent Patent Attorney Uchihara Oto 3 Qt Year 1 Sen

Claims (1)

[Claims] In a semiconductor memory device in which a plurality of memory cells are connected to a plurality of word lines and bit lines respectively in a matrix and a memory cell is selected by driving the word lines and bit lines, a drive capable of simultaneously driving a plurality of the word lines. A semiconductor memory device characterized by being provided with means.