JPS6218046A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6218046A
JPS6218046A JP60156509A JP15650985A JPS6218046A JP S6218046 A JPS6218046 A JP S6218046A JP 60156509 A JP60156509 A JP 60156509A JP 15650985 A JP15650985 A JP 15650985A JP S6218046 A JPS6218046 A JP S6218046A
Authority
JP
Japan
Prior art keywords
plating layer
pellet
bed
layer
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60156509A
Other languages
Japanese (ja)
Inventor
Yukio Yoshida
行男 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60156509A priority Critical patent/JPS6218046A/en
Publication of JPS6218046A publication Critical patent/JPS6218046A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To check the parasitic effect of a pellet, and to enable to perform stable bonding by a method wherein a bed under a plating layer is made to have a projecting type partially, and connection between the pellet and the plating layer according to a bonding wire is performed at the parts thereof. CONSTITUTION:A plating layer 12 consisting of Ag, for example, is formed on a bed 11 consisting of Cu, for example, and the circumferential part of the bed 11 and the part the plating layer 12 are formed in projecting types using a press, etc. Then a pellet 14 is mounted on the bed 11 interposing the plating layer 12 and a solder mounting layer (a bonding agent layer) 15 between them. Moreover the surface of the pallet 14, a lead frame 16 and the plating layer 12 of the projecting part 13 are connected electrically through bonding wires 17 consisting of gold, and the pellet 14, etc. are sealed with a resin layer 18 to form a semiconductor device.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に関し、特にペレットがマウントさ
れるベッドに改良を施した半導体装置に係わる。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a bed on which pellets are mounted is improved.

〔発明の技術的背景〕[Technical background of the invention]

滑車　産道ａ−肱署計佑１げ笛９々＋（、）、１ハ１ｆ
壬斗如く製造されている。Pulley Birth canal a-Keiyu 1 Gebue 9+(,), 1ha 1f
Manufactured like Jinto.

まず、第２図６）に示す如く例えばＣｕ（銅）からなる
ベッド１上に例えばＡｇ（銀）からなるメッキ層２を形
成した後、前記ベッド１をプレス等を用いて周辺を凸状
にする（第２図（ｂ）図示）。First, as shown in FIG. 2 (6), a plating layer 2 made of, for example, Ag (silver) is formed on a bed 1 made of, for example, Cu (copper), and then the bed 1 is shaped into a convex periphery using a press or the like. (as shown in FIG. 2(b)).

つづいて、ペレット３を前記ペッド１上にメッキ層２、
平田マウント層４を介してマウントする（第２図（ｃ）
図示）。なお、同図（Ｃ）において、５はリードフレー
ムである。次いで、前記にレット３の表面とリードフレ
ーム５、メッキ層２とをボンディングワイヤ６を介して
接続する。Subsequently, the pellet 3 is placed on the plated layer 2,
Mount via the Hirata mount layer 4 (Fig. 2(c))
(Illustrated). In addition, in the same figure (C), 5 is a lead frame. Next, the surface of the let 3 is connected to the lead frame 5 and the plating layer 2 via the bonding wire 6.

更に、前記４レツト３等を樹脂層７で封止して半導体装
置を製造する（第２図（ｄ）図示）。Furthermore, the 4-lets 3 and the like are sealed with a resin layer 7 to manufacture a semiconductor device (as shown in FIG. 2(d)).

〔背景技術の問題点〕[Problems with background technology]

しかしながら、従来技術によれば、ペレット３をペッド
１上にメッキ層２、平田マウント層４を介してマウンす
る際、平田マウント層４が流れやすく、その為に大分離
れた所にボンディングをする必要がある。従って、パワ
ーＩＣ等でベッド１の電位を寄生防止の為にＧＮＤ電位
にする場合、生田流れ量コントロールで平田の量、温度
及び時間を制限しなければならない。また、デンディン
グも平田マウント層４の流れがあるため、マージンをも
って遠くに打たなければならない。事実、４レツトサイ
ズが大きいと（２，５ｍｍ’以上）、現状ではデンディ
ングできない。However, according to the prior art, when mounting the pellet 3 on the ped 1 via the plating layer 2 and the Hirata mount layer 4, the Hirata mount layer 4 tends to flow, and therefore it is necessary to perform bonding at a location that is far apart. There is. Therefore, when using a power IC or the like to set the potential of the bed 1 to GND potential to prevent parasitism, it is necessary to limit the amount, temperature, and time of Ikuta flow rate control. Also, since there is a flow of the Hirata Mount Layer 4 for Dending, you have to hit it far with a margin. In fact, if the 4-let size is large (more than 2.5 mm'), it is currently impossible to perform dending.

この場合、セットメーカーで外部でＧＮＤ電位になる様
指導している。In this case, the set manufacturer instructs the manufacturer to set the potential to GND externally.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、ラッチアッ
プ現象、リーク現象等のペレットの寄生効果を防止する
とともに、安定なデンディングがなし得る等の効果を有
した牛導体装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a cattle conductor device which has effects such as preventing pellet parasitic effects such as latch-up phenomenon and leakage phenomenon, and enabling stable dending. With the goal.

〔発明の概要〕[Summary of the invention]

本発明は、ベッドと、このベッド上にメッキ層及び接着
剤層を介してマウントされたペレットと、リードフレー
ムと、前記ペレットとメッキ層、リードフレーム間を電
気的に接続するがンディングワイヤと、前記ペレットを
封止する樹脂層とを具備した牛導体装置において、前記
メッキ層下のベッドを部分的に凸状とし、この部分でデ
ンディングワイヤによるペレット、メッキ層間の接続を
行なうことを特徴とし、これによシ前記目的の達成を図
ったものである。The present invention provides a bed, a pellet mounted on the bed via a plating layer and an adhesive layer, a lead frame, and a landing wire that electrically connects the pellet, the plating layer, and the lead frame. A conductor device comprising a resin layer for sealing the pellet, characterized in that the bed under the plating layer is partially convex, and the connection between the pellet and the plating layer is made by a dendritic wire in this part. , thereby attempting to achieve the above-mentioned objective.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を製造工程順に第１図（、）〜
（ｄ）を参照して説明する。An embodiment of the present invention will be described below in the order of manufacturing steps in FIGS.
This will be explained with reference to (d).

まず、例えばＣｕからなるベッド１１上に例えばＡｇか
らなるメッキ層１２を形成した（第１図（、）図示）。First, a plating layer 12 made of, for example, Ag was formed on a bed 11 made of, for example, Cu (as shown in FIG. 1(, )).

つづいて、前記ベッド１１をブレス等を用い、その周辺
及び前記メッキ層１２下の部分を凸状にした（第１図（
ｂ）図示）。なお、図中の１３は突起部を示す。次いで
、ペレット１４を前記ベッド１１上にメッキ層１２、平
田マウント層（接着剤層）１５を介してマウントした（
第１図（ｃ）図示）。なお、同図（ｃ）において、１６
はリードフレームを示す。更に、前記ペレット１４の表
面とリードフレーム１６、突起部１３のメッキ層１２と
を金からなる♂ンディングワイヤ１７を介して電気的に
接続する。しかる後、前記ペレット１４等を樹脂層１８
で封止して手導体装置を製造した（第１図（ｄ））。Next, using a brace or the like, the bed 11 was made into a convex shape around the bed 11 and under the plating layer 12 (see Fig. 1).
b) As shown). Note that 13 in the figure indicates a protrusion. Next, the pellets 14 were mounted on the bed 11 via a plating layer 12 and a Hirata mounting layer (adhesive layer) 15 (
(Illustrated in FIG. 1(c)). In addition, in the same figure (c), 16
indicates a lead frame. Furthermore, the surface of the pellet 14, the lead frame 16, and the plating layer 12 of the protrusion 13 are electrically connected via a female ending wire 17 made of gold. After that, the pellets 14 etc. are placed in the resin layer 18.
A hand conductor device was manufactured by sealing with (FIG. 1(d)).

本発明に係る手導体装置は、第１図（ｄ）に示す如く、
突起部１３を有したベッド１ノ上にメッキ層１２、平田
マウント層１５を介してベレッ　ｌトノ４を設け、この
ペレット１４と前記突起部１３上のメッキ層１２とをデ
ンディングワイヤ１７を介して接続した構造となりてい
る。従って、本発明によれば、以下に示す効果を得るこ
とができる。The hand conductor device according to the present invention, as shown in FIG. 1(d),
A pellet 4 is provided on the bed 1 having the protrusion 13 via the plating layer 12 and the Hirata mount layer 15 , and the pellet 14 and the plating layer 12 on the protrusion 13 are connected via a dendritic wire 17 . It has a structure in which it is connected. Therefore, according to the present invention, the following effects can be obtained.

■　ベッド１１をＧＮＤ電位にする効果；ペレット１４
の寄生効果（Ｓｕｂの電流増大によるＧＮＤ電位アンバ
ランスの為、ラッチアップ現象、リーク現象が起シ易い
）を防止するとともに、セットメーカーでベッド１１ｔ
ｌ−ＧＮＤ電位にする必要を回避できる。■ Effect of setting bed 11 to GND potential; pellet 14
In addition to preventing the parasitic effect of
It is possible to avoid the need to set the potential to l-GND.

■　ベッドデンディングの効果；平田マウントの時、ベ
ッドデンディングする所が設定できるため、安定なデン
ディングが可能となる。■ Effect of bed-dending: When using Hirata mount, you can set the place where bed-dending will occur, making stable dending possible.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く本発明によれば、ペレットの寄生効果
を防止するとともに、安定なデンディングをなし得る高
信頼性の生導体装置を提供できる。As described in detail above, according to the present invention, it is possible to provide a highly reliable live conductor device that can prevent the parasitic effect of pellets and achieve stable dending.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（−）〜（ｄ）は本発明に係るヰ導体装置を製造
工程順に示す断面図、第２図（、）〜（ｄ）は従来の牛
導体ｇ装置を製造工程順に示す断面図である。 １１・・・ベッド、１２・・・メッキ層、１３・・・突
起部、１４・・・ペレット、１５・・・平田マウント層
、１６・・・リードフレーム、１７・・・デンディング
ワイヤ、１８・・・樹脂層。FIGS. 1(-) to (d) are cross-sectional views showing a conductor device according to the present invention in the order of manufacturing steps, and FIGS. 2(-) to (d) are cross-sectional views showing a conventional conductor device in the order of manufacturing steps. It is. DESCRIPTION OF SYMBOLS 11... Bed, 12... Plating layer, 13... Projection, 14... Pellet, 15... Hirata mount layer, 16... Lead frame, 17... Dending wire, 18 ...resin layer.

Claims (1)

【特許請求の範囲】[Claims] 　ベッドと、このベッド上にメッキ層及び接着剤層を介
してマウントされたペレットと、リードフレームと、前
記ペレットとメッキ層、リードフレーム間を電気的に接
続するボンディングワイヤと、前記ペレットを封止する
樹脂層とを具備した半導体装置において、前記メッキ層
下のベッドを部分的に凸状とし、この部分でボンディン
グワイヤによるペレット、メッキ層間の接続を行なうこ
とを特徴とする半導体装置。A bed, a pellet mounted on the bed via a plating layer and an adhesive layer, a lead frame, a bonding wire electrically connecting the pellet, the plating layer, and the lead frame, and sealing the pellet. What is claimed is: 1. A semiconductor device comprising a resin layer, wherein a bed under the plating layer is partially convex, and a bonding wire is used to connect the pellet and the plating layer at this portion.
JP60156509A 1985-07-16 1985-07-16 Semiconductor device Pending JPS6218046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60156509A JPS6218046A (en) 1985-07-16 1985-07-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60156509A JPS6218046A (en) 1985-07-16 1985-07-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6218046A true JPS6218046A (en) 1987-01-27

Family

ID=15629318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60156509A Pending JPS6218046A (en) 1985-07-16 1985-07-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6218046A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723293A1 (en) * 1994-12-16 1996-07-24 Seiko Epson Corporation Semiconductor device with a heat sink and method of producing the heat sink
SG114453A1 (en) * 1994-12-16 2005-09-28 Seiko Epson Corp Semiconductor device with a heat sink and method of producing the heat sink

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723293A1 (en) * 1994-12-16 1996-07-24 Seiko Epson Corporation Semiconductor device with a heat sink and method of producing the heat sink
SG114453A1 (en) * 1994-12-16 2005-09-28 Seiko Epson Corp Semiconductor device with a heat sink and method of producing the heat sink

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