JPS6217907B2 - - Google Patents

Info

Publication number
JPS6217907B2
JPS6217907B2 JP1145979A JP1145979A JPS6217907B2 JP S6217907 B2 JPS6217907 B2 JP S6217907B2 JP 1145979 A JP1145979 A JP 1145979A JP 1145979 A JP1145979 A JP 1145979A JP S6217907 B2 JPS6217907 B2 JP S6217907B2
Authority
JP
Japan
Prior art keywords
circuit
output
detection
amplitude
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1145979A
Other languages
Japanese (ja)
Other versions
JPS55104152A (en
Inventor
Isao Akitake
Kazuhiko Yamazaki
Tsutomu Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1145979A priority Critical patent/JPS55104152A/en
Priority to US06/117,457 priority patent/US4349696A/en
Publication of JPS55104152A publication Critical patent/JPS55104152A/en
Publication of JPS6217907B2 publication Critical patent/JPS6217907B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H20/00Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/44Arrangements characterised by circuits or components specially adapted for broadcast
    • H04H20/46Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95
    • H04H20/47Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95 specially adapted for stereophonic broadcast systems
    • H04H20/49Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95 specially adapted for stereophonic broadcast systems for AM stereophonic broadcast systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H40/00Arrangements specially adapted for receiving broadcast information
    • H04H40/18Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Stereo-Broadcasting Methods (AREA)

Description

【発明の詳細な説明】 本発明はAMステレオ放送の一方式である
Belar方式、Magnavox方式のAMステレオ復調回
路に関するものである。
[Detailed Description of the Invention] The present invention is a method of AM stereo broadcasting.
This relates to AM stereo demodulation circuits using the Belar method and Magnavox method.

第1図、第2図にBelar方式の基本的なステレ
オ送信ブロツク図、ステレオ復調ブロツク図を示
す。第1図によつて送信部を説明する。マトリツ
クス回路4の入力端子5,6にはステレオ信号の
左信号(以後Lchと呼ぶ)、右信号(以後Rchと呼
ぶ)が入力し、該マトリツクス回路4によつて出
力端子7,8にはそれぞれ差信号(以後L−Rと
呼ぶ)、和信号(後L+Rと呼ぶ)が出力する。
(L−R)信号はプリエンフアシス回路3を介し
て周波数変調回路2に入力し、搬送波発振器1に
よつて発生した搬送波信号を周波数変調する。周
波数変調された搬送波信号はつぎに振幅変調回路
9に入力し、(L+R)信号によつて振幅変調さ
れる。
FIGS. 1 and 2 show a basic stereo transmission block diagram and a stereo demodulation block diagram of the Belar system. The transmitter will be explained with reference to FIG. A left signal (hereinafter referred to as Lch) and a right signal (hereinafter referred to as Rch) of a stereo signal are input to input terminals 5 and 6 of the matrix circuit 4, and output terminals 7 and 8 are respectively inputted by the matrix circuit 4. A difference signal (hereinafter referred to as LR) and a sum signal (hereinafter referred to as L+R) are output.
The (LR) signal is input to the frequency modulation circuit 2 via the pre-emphasis circuit 3, and frequency modulates the carrier signal generated by the carrier wave oscillator 1. The frequency-modulated carrier wave signal is then input to an amplitude modulation circuit 9, where it is amplitude-modulated by the (L+R) signal.

以上の様にBelar方式では搬送波信号を(L−
R)信号で周波数変調、(L+R)信号で振幅変
調する方式である。
As mentioned above, in the Belar method, the carrier signal (L-
This is a method in which frequency modulation is performed using the R) signal and amplitude modulation is performed using the (L+R) signal.

つぎに第2図によつて受信及び復調方法を説明
する。ステレオ送信信号は高周波増幅回路10、
中間周波増幅回路11を介して中間周波数に変換
される。中間周波数に変換されたステレオ信号
は、一方はAM検波回路12によつて(L+R)
信号に復調される。他方振幅制限回路13により
(L+R)信号のAM分を取り去り(L−R)信
号で変調されたFM信号だけとし、この信号を
FM検波回路14によりFM検波を行い(L−
R)信号を取り出す。この(L−R)信号は送信
時にプリエンフアシスされており、補正するため
にデイエンフアシス回路15を介して出力され
る。つぎにそれぞれ検波された変調信号(L−
R)、(L+R)信号はマトリツクス回路16によ
つてL信号、R信号に分離しステレオ復調を行
う。
Next, the reception and demodulation method will be explained with reference to FIG. The stereo transmission signal is transmitted through a high frequency amplification circuit 10,
The signal is converted to an intermediate frequency via an intermediate frequency amplification circuit 11. One side of the stereo signal converted to the intermediate frequency is (L+R) by the AM detection circuit 12.
demodulated into a signal. On the other hand, the amplitude limiting circuit 13 removes the AM component of the (L+R) signal, leaving only the FM signal modulated by the (L-R) signal, and this signal is
FM detection is performed by the FM detection circuit 14 (L-
R) Take out the signal. This (LR) signal is pre-emphasized at the time of transmission, and is output via the de-emphasis circuit 15 for correction. Next, each detected modulation signal (L-
R) and (L+R) signals are separated into L and R signals by a matrix circuit 16 and subjected to stereo demodulation.

第3図、第4図にMagnavox方式のステレオ送
信ブロツク図、ステレオ復調ブロツク図を示す。
Belar方式との差異はBelar方式が(L−R)信号
を周波数変調するのに対し、Magnavox方式は位
相変調(PM)する方式である。ゆえに送信では
第1図、第3図のブロツク図での違いは、第1図
の周波数変調回路2が第3図では位相変調回路4
4になりプリエンフアシス回路3がない。
Figures 3 and 4 show a stereo transmission block diagram and a stereo demodulation block diagram of the Magnavox system.
The difference from the Belar method is that the Belar method frequency modulates the (LR) signal, whereas the Magnavox method performs phase modulation (PM). Therefore, in transmission, the difference between the block diagrams in Figures 1 and 3 is that the frequency modulation circuit 2 in Figure 1 is replaced by the phase modulation circuit 4 in Figure 3.
4 and there is no pre-emphasis circuit 3.

第2図、第4図の受信ブロツク図での違いは、
第2図のFM検波回路14が第4図ではPM検波
回路45になり、デイエンフアシス回路15がな
い。他のブロツクは同一で、システムの動作は
Belar方式と同様である。いま、両方式でステレ
ス復調を行つた場合に問題になるのは、左・右の
分離度である。一般にAM検波(L+R信号の検
波)の場合、第5図、第6図で示す様にAM検波
回路12の出力を整流回路19に接続し、該整流
回路19の出力で高周波増幅回路10、中間周波
増幅回路11に帰還をかけるAGC回路が用いら
れるため、入力レベル対出力レベルは第7図中2
0の様な特性を示し、入力レベルが小さい時には
直線的に出力レベルは増加するが、ある値になる
とAGC動作が作動し出力レベルは飽和する。し
かし飽和レベルは完全に一定にはならず、入力レ
ベルと共に除々に増加して行く。
The difference between the reception block diagrams in Figures 2 and 4 is as follows:
The FM detection circuit 14 in FIG. 2 becomes a PM detection circuit 45 in FIG. 4, and the de-emphasis circuit 15 is not provided. All other blocks are identical and the system operates as follows:
This is similar to the Belar method. Now, when Stereth demodulation is performed using both methods, the problem is the degree of separation between left and right. Generally, in the case of AM detection (detection of L+R signals), the output of the AM detection circuit 12 is connected to a rectifier circuit 19 as shown in FIGS. Since an AGC circuit that applies feedback to the frequency amplification circuit 11 is used, the input level vs. output level is 2 in Figure 7.
When the input level is small, the output level increases linearly, but when it reaches a certain value, the AGC operation is activated and the output level is saturated. However, the saturation level is not completely constant and gradually increases with the input level.

一方FM検波またはPM検波(L−R信号の検
波)の場合は、第7図中21で示す様に、AM成
分を除去するために、振幅制限器の利得を大きく
し、入力レベルが小さい時から出力レベルを一定
にする。以上、上述した様にAM検波とFMおよ
びPM検波の入、出力特性は異り、それぞれで検
波された信号(L+R)、(L−R)信号にレベル
差があるため、マトリツクス回路16でL信号、
R信号に分離した時に弱入力レベル時、強入力レ
ベル時に分離度が劣化するという問題が生じる。
On the other hand, in the case of FM detection or PM detection (detection of L-R signals), in order to remove the AM component, the gain of the amplitude limiter is increased and when the input level is small, as shown at 21 in Figure 7. to keep the output level constant. As mentioned above, the input and output characteristics of AM detection and FM and PM detection are different, and there is a level difference between the detected signals (L+R) and (LR), respectively, so the matrix circuit 16 signal,
When separating into R signals, a problem arises in that the degree of separation deteriorates at weak input levels and at strong input levels.

本発明の目的は、上記した信号入力レベルが弱
入力時及び強入力時に分離度が劣化するという欠
点を軽減するBelar方式、Magnavox方式のステレ
ス復調回路を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a Belar type or Magnavox type Stereth demodulation circuit which alleviates the above-described drawback that the degree of separation deteriorates when the signal input level is weak or strong.

本発明の要点は、AM検波に使用しているAGC
回路の出力でFMおよびPM復調部の利得を制御
する。つまり振幅制限器に電流制限形の差動増幅
回路を用い、その定電流量を制御する。またフオ
ードラチヤ形検波器を用いた場合には、同様に差
動回路の定電流量を制御することにある。
The key point of the present invention is that the AGC used for AM detection
The output of the circuit controls the gain of the FM and PM demodulators. In other words, a current-limiting differential amplifier circuit is used as the amplitude limiter, and its constant current amount is controlled. Furthermore, when a quadrature detector is used, the purpose is to similarly control the constant current amount of the differential circuit.

以下本発明の実施例を図面に基づいて説明す
る。第8図は本発明の実施例を示すBelar方式の
AMステレス復調回路であり、第9図は
Magnavox方式のAMステレオ復調回路である。
第8図、第9図において、検波方法つまりAM検
波によつて(L+R)信号を、FM検波または
PM検波によつて(L−R)信号を取り出し、マ
トリツクス回路16にてL信号、R信号に分離す
るシステムの動作は、第2図、第4図、第5図、
第6図の従来回路で説明したものと同様である。
ここでは制御方法のみ説明する。
Embodiments of the present invention will be described below based on the drawings. FIG. 8 shows the Belar method showing an embodiment of the present invention.
This is an AM stereo demodulation circuit, and Figure 9 shows
This is a Magnavox type AM stereo demodulation circuit.
In Figures 8 and 9, the (L+R) signal is detected by AM detection, FM detection or
The operation of the system that extracts the (L-R) signal by PM detection and separates it into L and R signals in the matrix circuit 16 is shown in FIGS. 2, 4, and 5.
This is similar to that described in connection with the conventional circuit shown in FIG.
Only the control method will be explained here.

該AM検波回路12の出力は、該マトリツクス
回路16に入力されると共に、該整流回路19に
入力する。該整流回路19では上記検波出力のレ
ベルに応じた直流電圧を発生する。該整流回路1
9の出力は該高周波増幅回路10、該中間周波増
幅回路11に帰還され、入力信号レベルが大きく
なると出力をほぼ一定にする利得制御回路
(AGC回路)を構成する。また該整流回路19の
出力は該振幅制限回路13の制御端子48と接続
され、ANT入力レベルに比例して、該振幅制限
回路13の利得、振幅の制御を行う。
The output of the AM detection circuit 12 is input to the matrix circuit 16 and also to the rectifier circuit 19. The rectifier circuit 19 generates a DC voltage according to the level of the detected output. The rectifier circuit 1
The output of 9 is fed back to the high frequency amplifier circuit 10 and the intermediate frequency amplifier circuit 11, forming a gain control circuit (AGC circuit) that keeps the output substantially constant when the input signal level increases. The output of the rectifier circuit 19 is connected to the control terminal 48 of the amplitude limiting circuit 13, and controls the gain and amplitude of the amplitude limiting circuit 13 in proportion to the ANT input level.

該振幅制限回路13の構成の一実施例を第10
図で示す。第10図においてトランジスタ22,
23は差動対となつており、抵抗24,25はそ
れぞれの負荷抵抗、定電流源のトランジスタ26
のコレクタは上記差動対トランジスタ22,23
の共通エミツタと接続され、ベースは電源27と
接続される。またエミツタは電界効果トランジス
タのドレインと接続され、ソースは接地され、ま
たゲートは該整流回路19の出力と接続する。こ
の様な差動増幅回路構成の利得および出力振幅は
差動増幅回路の定電流量に依存している。
An example of the configuration of the amplitude limiting circuit 13 is shown in the 10th embodiment.
Illustrated in the diagram. In FIG. 10, the transistor 22,
23 constitutes a differential pair, resistors 24 and 25 are respective load resistances, and constant current source transistor 26
The collector of the differential pair transistors 22 and 23
The base is connected to the power supply 27. Further, the emitter is connected to the drain of the field effect transistor, the source is grounded, and the gate is connected to the output of the rectifier circuit 19. The gain and output amplitude of such a differential amplifier circuit configuration depend on the amount of constant current of the differential amplifier circuit.

定電流量を可変するには、該トランジスタ26
のエミツタに接続された該電界効果トランジスタ
28を可変抵抗領域で使用する。ゲートには
ANT入力レベルに比例した整流出力電圧を生じ
る該整流回路19の出力電圧が印加されるため、
ドレイン−ソース間の抵抗値、つまり該トランジ
スタ26のエミツタ抵抗を可変することができ
る。該トランジスタ26のベースは一定電圧であ
るため、エミツタ抵抗が変化すると電流量が変化
し、該振幅制限回路13を構成する差動増幅器の
利得、振幅を制御できる。
To vary the amount of constant current, the transistor 26
The field effect transistor 28 connected to the emitter of is used in the variable resistance region. At the gate
Since the output voltage of the rectifier circuit 19 that produces a rectified output voltage proportional to the ANT input level is applied,
The resistance value between the drain and the source, that is, the emitter resistance of the transistor 26 can be varied. Since the base of the transistor 26 has a constant voltage, when the emitter resistance changes, the amount of current changes, and the gain and amplitude of the differential amplifier constituting the amplitude limiting circuit 13 can be controlled.

第11図に上述の関係図を示し説明する。第1
1図において横軸はANT入力レベルを表し、縦
軸は復調器の検波出力レベルを表す。FM検波、
PM検波の入−出力特性は周知の様に入力レベル
が小さいときには直線的に増加するが、入力レベ
ルがあるレベル以上になると(振幅制限器のリミ
ツタレベルに達した時)検波出力レベルは一定と
なり、図中破線49,50,51,52で示した
特性となる。ここで各特性の違いを述べる。前記
した様に該振幅制限回路13には差動増幅器を用
いている。上述のリミツタレベルはこの差動増幅
器の定電流量によつて決定される。つまり定電流
量が多いほど利得、出力振幅が大きくなり、入力
レベルがより小さい所からリミツタがかかる様に
なり、また出力レベルは振幅が大きいほど大きく
なる。第8図のブロツク図を併用して説明する。
FIG. 11 shows the above-mentioned relationship diagram and will be explained. 1st
In Figure 1, the horizontal axis represents the ANT input level, and the vertical axis represents the demodulator detection output level. FM detection,
As is well known, the input-output characteristics of PM detection increase linearly when the input level is small, but when the input level exceeds a certain level (when it reaches the limiter level of the amplitude limiter), the detection output level becomes constant. The characteristics are shown by broken lines 49, 50, 51, and 52 in the figure. Here we will explain the differences in each characteristic. As described above, the amplitude limiting circuit 13 uses a differential amplifier. The limiter level mentioned above is determined by the amount of constant current of this differential amplifier. In other words, the larger the amount of constant current, the larger the gain and output amplitude, the more the limiter is applied starting from the smaller input level, and the larger the amplitude, the larger the output level. This will be explained using the block diagram of FIG.

入力レベルが大きい100dBμ時には該AM検波
回路12の出力電圧は大きいため、該整流回路1
9の直流出力電圧も大きくなる。この直流出力電
圧は該振幅制限回路13の制御端子48に印加さ
れるため、電界効果トランジスタ28のドレイン
―ソース間の抵抗値は小さくなり、定電流量を決
定する該トランジスタ26のエミツタ抵抗が小さ
くなり定電流量が大きくなる。よつて該振幅制限
回路13の利得、振幅が大きくなり破線49で示
した入−出力特性となる。同様に入力レベルが
70dBμ、30dBμ、23dBμと小さくなると、該整
流回路19の直流出力電圧はそれぞれに比例して
小さくなり、該振幅制限回路13の定電流量が小
さくなり、利得、振幅も小さくなつて行く。よつ
てリミツタがかかる入力レベルは大きくなつて行
く。また検波出力は小さくなつて行く。この状態
を示するの破線50,51,52の入−出力特性
である。
When the input level is 100 dBμ, the output voltage of the AM detection circuit 12 is large, so the rectifier circuit 1
The DC output voltage of No. 9 also increases. Since this DC output voltage is applied to the control terminal 48 of the amplitude limiting circuit 13, the resistance value between the drain and source of the field effect transistor 28 becomes small, and the emitter resistance of the transistor 26, which determines the amount of constant current, becomes small. Therefore, the amount of constant current increases. Therefore, the gain and amplitude of the amplitude limiting circuit 13 become large, resulting in the input-output characteristics shown by the broken line 49. Similarly, the input level
When it becomes smaller to 70 dBμ, 30 dBμ, and 23 dBμ, the DC output voltage of the rectifier circuit 19 decreases in proportion to each, the constant current amount of the amplitude limiting circuit 13 decreases, and the gain and amplitude also decrease. Therefore, the input level to which the limiter is applied increases. Furthermore, the detection output becomes smaller. Input-output characteristics of broken lines 50, 51, and 52 indicate this state.

しかし以上の入−出力特性49〜52は入力レ
ベルが一定と考え、それに対応した定電流量が流
れた場合の利得を持つ振幅制限回路13を用いた
時の入−出力特性であつたが、実際には、入力レ
ベルも変動しているため、定電流量および利得も
変化する。つまり入力レベルが100dBμ時には破
線49と入力レベル100dBμ時の交点53が実際
の出力レベルであり、入力レベル70dBμ時には
破線50と70dBμ時の交点54、同様に交点5
5,56が入力レベル30dBμ,23dBμ時の出力
レベルである。これらの交点を結んだ実線が該
AM検波器12の出力電圧で制御されたFM検波
回路14、PM検波回路45の入−出力特性であ
る。
However, the above input-output characteristics 49 to 52 are input-output characteristics when the input level is assumed to be constant and the amplitude limiting circuit 13 has a gain when a corresponding constant current flows. In reality, since the input level is also changing, the amount of constant current and gain are also changing. In other words, when the input level is 100 dBμ, the actual output level is the intersection between the broken line 49 and the intersection 53 when the input level is 100 dBμ, and when the input level is 70 dBμ, the intersection between the broken line 50 and the intersection 54 when the input level is 70 dBμ is the actual output level.
5 and 56 are the output levels when the input level is 30 dBμ and 23 dBμ. The solid line connecting these intersection points corresponds to
These are the input-output characteristics of the FM detection circuit 14 and the PM detection circuit 45 controlled by the output voltage of the AM detector 12.

以上の制御方法を用い、ある基準入力レベル
時、例えば70dBμ時にAM検波出力レベルとFM
又はPM検波出力レベルを同一になる様に該振幅
制限回路13の定電流量を調整する。つまり定電
流量を決定する該電界効果トランジスタ28のゲ
ートにかかる該整流回路19の電圧を調整する。
以上の調整をすればAM検波出力レベルによつて
FM検波出力レベルまたはPM検波出力レベルは
AM検波出力レベルと比例して変化させることが
でき、入力レベルが変化してもAM検波出力であ
る和信号(L+R)、FM,PM検波出力である差
信号(L−R)とはほぼ等しくすることができ、
従来回路で述べた入力レベルの変動による分離度
劣化を減少させることができる。
Using the above control method, at a certain reference input level, for example 70 dBμ, the AM detection output level and FM
Alternatively, the constant current amount of the amplitude limiting circuit 13 is adjusted so that the PM detection output level becomes the same. That is, the voltage of the rectifier circuit 19 applied to the gate of the field effect transistor 28 which determines the amount of constant current is adjusted.
If you make the above adjustments, it will depend on the AM detection output level.
FM detection output level or PM detection output level
It can be changed in proportion to the AM detection output level, and even if the input level changes, the sum signal (L + R), which is the AM detection output, and the difference signal (L - R), which is the FM and PM detection output, are almost equal. can,
It is possible to reduce the deterioration of the degree of separation due to fluctuations in the input level as described in the conventional circuit.

実施例の第8図、第9図では、振幅制限回路の
定電流量を可変抵抗素子によつて制御したが、第
12図、第13図では検波回路にクオードラチヤ
検波回路を用いた場合の実施例を示す。第12
図、第13図において検波方法および制御信号の
取り出しは、第8図、第9図で説明したと同様で
ある。
In the example shown in FIGS. 8 and 9, the constant current amount of the amplitude limiting circuit is controlled by a variable resistance element, but in FIGS. 12 and 13, a quadrature detection circuit is used as the detection circuit. Give an example. 12th
The detection method and control signal extraction in FIGS. 8 and 13 are the same as those described in FIGS. 8 and 9.

第14図に利得、振幅可変のクオードラチヤ検
波回路を示す。差動対トランジスタ29,30は
第1のスイツチ回路41を構成し、該トランジス
タ29のコレクタには差動対トランジスタ31,
32で構成された第2のスイツチ回路42の共通
エミツタが接続されている。トランジスタ31,
32のコレクタには抵抗33,34が電源43と
の間に接続され負荷抵抗となつている。該トラン
ジスタ30のコレクタは電源43と接続されてい
る。また差動対トランジスタ29,30の共通エ
ミツタはトランジスタ26のコレクタに接続され
ている。該トランジスタ26のベースは電源27
と接続され、エミツタは電界効果トランジスタ2
8のドレインと接続されている。該電界効果トラ
ンジスタ28のソースは接地され、ゲートは該整
流回路19の出力と接続されている。入力端子3
6には周波数変調または位相変調された入力信号
が印加され、該第1のスイツチ回路41に入力さ
れると同時に移相回路38に入力され、位相が90
゜移相された信号が該第2のスイツチ回路42に
入力される。この該第1のスイツチ回路41,該
第2のスイツチ回路42で構成された掛け算回路
でFM検波またはPM検波を行う。
FIG. 14 shows a quadrature detection circuit with variable gain and amplitude. The differential pair transistors 29 and 30 constitute a first switch circuit 41, and the collector of the transistor 29 has a differential pair transistor 31,
A common emitter of a second switch circuit 42 consisting of 32 is connected. transistor 31,
Resistors 33 and 34 are connected between the collector of 32 and a power source 43, serving as a load resistance. The collector of the transistor 30 is connected to a power source 43. Further, the common emitters of the differential pair transistors 29 and 30 are connected to the collector of the transistor 26. The base of the transistor 26 is connected to the power supply 27
The emitter is connected to field effect transistor 2.
It is connected to the drain of 8. The source of the field effect transistor 28 is grounded, and the gate is connected to the output of the rectifier circuit 19. Input terminal 3
A frequency-modulated or phase-modulated input signal is applied to 6, which is input to the first switch circuit 41 and simultaneously input to the phase shift circuit 38, so that the phase is set to 90.
The phase-shifted signal is input to the second switch circuit 42. A multiplication circuit composed of the first switch circuit 41 and the second switch circuit 42 performs FM detection or PM detection.

この時、検波回路の利得、出力振幅を決め、定
電流量を決定する該トランジスタ26のエミツタ
に接続された該電界効果トランジスタ28を可変
抵抗領域で使用する。該電界効果トランジスタ2
8のゲートは該整流回路19の出力と接続されて
おり、ドレイン・ソース間の抵抗値が入力レベル
に応じて変化するため、該第1,第2のスイツチ
回路41,42に流れる電流量も可変でき検波回
路の利得、出力振幅を入力レベルに応じて制御で
き、第11図で示した特性が得られ、分離度の劣
化を失くすことができる。
At this time, the field effect transistor 28 connected to the emitter of the transistor 26, which determines the gain and output amplitude of the detection circuit and determines the amount of constant current, is used in a variable resistance region. The field effect transistor 2
The gate of 8 is connected to the output of the rectifier circuit 19, and the resistance value between the drain and source changes depending on the input level, so the amount of current flowing through the first and second switch circuits 41 and 42 also changes. The gain and output amplitude of the variable detection circuit can be controlled according to the input level, the characteristics shown in FIG. 11 can be obtained, and deterioration of the degree of separation can be eliminated.

以上、実施例で述べた様に、本発明はAM検波
の出力レベルでFMおよびPM検波回路の利得、
振幅を制御することで、AM検波で得られる(L
+R)信号、FMおよびPM検波で得られる(L
−R)信号のレベル差を失くすことができ、分離
度の劣化を防ぐことができる。
As described above in the embodiments, the present invention allows the gain of the FM and PM detection circuits to be adjusted based on the output level of AM detection.
By controlling the amplitude, the amplitude can be obtained by AM detection (L
+R) signal, (L) obtained by FM and PM detection
-R) Signal level differences can be eliminated, and deterioration of separation can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図はBelar方式の送・受信ブロツ
ク図、第3図、第4図はMagnavox方式の送・受
信ブロツク図、第5図はBelar方式の従来回路、
第6図はMagnavoxの従来回路、第7図は両方式
の従来回路の入・出力特性、第8図はBelar方式
で可変出力リミツタを用いた第1の実施例、第9
図はMagnavox方式で可変出力リミツタを用いた
第1の実施例、第10図は両方式の第1の実施例
における可変利得振幅制限回路、第11図は第1
の実施例における特性例、第12図、第13図は
それぞれBelar方式、Magnavox方式でクオードラ
チヤ検波回路を用いた第2の実施例、第14図は
第2の実施例における可変利得クオードラチヤ検
波回路を示す。 12……AM検波回路、13……リミツタ回
路、14……FM検波回路、19……整流回路。
Figures 1 and 2 are transmission and reception block diagrams of the Belar system, Figures 3 and 4 are transmission and reception block diagrams of the Magnavox system, and Figure 5 is a conventional Belar system circuit.
Figure 6 shows the conventional Magnavox circuit, Figure 7 shows the input/output characteristics of both conventional circuits, Figure 8 shows the first embodiment using a Belar type variable output limiter, and Figure 9 shows the first embodiment using a variable output limiter using the Belar method.
The figure shows the first embodiment using a variable output limiter using the Magnavox method, FIG. 10 shows the variable gain amplitude limiting circuit in the first embodiment using both types, and FIG.
12 and 13 show a second embodiment using a quadrature detection circuit using the Belar method and Magnavox method, respectively, and FIG. 14 shows a variable gain quadrature detection circuit in the second embodiment. show. 12...AM detection circuit, 13...limiter circuit, 14...FM detection circuit, 19...rectifier circuit.

Claims (1)

【特許請求の範囲】 1 AM/FM多重受信機において、少くともAM
検波回路、整流回路、振幅制限回路およびFM検
波回路を具備し、上記AM検波回路の入力と上記
振幅制限回路の入力は共通の入力端子を持ち、上
記振幅制限回路の出力を上記FM検波回路に接続
し、上記AM検波回路の出力を上記整流回路を介
して上記振幅制限回路の制御端子に接続し、上記
整流回路の出力レベルに応じて上記振幅制限回路
の利得および振幅を制御することを特徴とした
AMステレオ復調回路。 2 AM/PM多重受信機において、少くともAM
検波回路、整流回路、振幅制限回路およびPM検
波回路を具備し、上記AM検波回路の入力と上記
振幅制限回路の入力は、共通の入力端子を持ち、
上記振幅制限回路の出力を上記PM検波回路に接
続し、上記AM検波回路の出力を上記整流回路を
介して上記振幅制限回路の制御端子に接続し、上
記整流回路の出力レベルに応じて上記振幅制限回
路の利得および振幅を制御することを特徴とした
AMステレオ復調回路。 3 特許請求の範囲第1項、第2項において、整
流出力を前記FMおよびPM検波回路の制御端子
に接続し、整流出力レベルに応じて、上記FMお
よびPM検波回路の利得および振幅を制御するこ
とを特徴としたAMステレオ復調回路。
[Claims] 1. In an AM/FM multiplex receiver, at least AM
It is equipped with a detection circuit, a rectification circuit, an amplitude limiting circuit, and an FM detection circuit, and the input of the AM detection circuit and the input of the amplitude limiting circuit have a common input terminal, and the output of the amplitude limiting circuit is connected to the FM detection circuit. and the output of the AM detection circuit is connected to the control terminal of the amplitude limiting circuit via the rectifying circuit, and the gain and amplitude of the amplitude limiting circuit are controlled according to the output level of the rectifying circuit. It was
AM stereo demodulation circuit. 2 In an AM/PM multiplex receiver, at least
It is equipped with a detection circuit, a rectifier circuit, an amplitude limiting circuit, and a PM detection circuit, and the input of the AM detection circuit and the input of the amplitude limiting circuit have a common input terminal,
The output of the amplitude limiting circuit is connected to the PM detection circuit, the output of the AM detection circuit is connected to the control terminal of the amplitude limiting circuit via the rectifier circuit, and the amplitude is adjusted according to the output level of the rectifier circuit. characterized by controlling the gain and amplitude of the limiting circuit.
AM stereo demodulation circuit. 3. In claims 1 and 2, the rectified output is connected to the control terminal of the FM and PM detection circuit, and the gain and amplitude of the FM and PM detection circuit are controlled according to the rectified output level. This is an AM stereo demodulation circuit characterized by:
JP1145979A 1979-02-05 1979-02-05 Am stereo demodulation circuit Granted JPS55104152A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1145979A JPS55104152A (en) 1979-02-05 1979-02-05 Am stereo demodulation circuit
US06/117,457 US4349696A (en) 1979-02-05 1980-02-01 AM Stereophonic demodulator circuit for amplitude/angle modulation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1145979A JPS55104152A (en) 1979-02-05 1979-02-05 Am stereo demodulation circuit

Publications (2)

Publication Number Publication Date
JPS55104152A JPS55104152A (en) 1980-08-09
JPS6217907B2 true JPS6217907B2 (en) 1987-04-20

Family

ID=11778673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1145979A Granted JPS55104152A (en) 1979-02-05 1979-02-05 Am stereo demodulation circuit

Country Status (1)

Country Link
JP (1) JPS55104152A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221090Y2 (en) * 1980-06-20 1987-05-28
JPS5737947A (en) * 1980-08-15 1982-03-02 Hitachi Ltd Am stereo receiver
JPS5767344A (en) * 1980-10-15 1982-04-23 Sharp Corp Am stereo receiver
JPS5797744A (en) * 1980-12-10 1982-06-17 Matsushita Electric Ind Co Ltd Am stereo receiver
JPS57206144A (en) * 1981-06-12 1982-12-17 Matsushita Electric Ind Co Ltd Am stereo broadcasting system and its signal receiver
JP2735832B2 (en) * 1987-09-18 1998-04-02 三洋電機株式会社 Television sound multiplex demodulation circuit

Also Published As

Publication number Publication date
JPS55104152A (en) 1980-08-09

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