JPS62177941A - Master-slice type integrated circuit device - Google Patents

Abstract

PURPOSE:To adopt various memory constitution by forming a bulk for an SRAM with an output port operating as a ROM by a wiring. CONSTITUTION:A bulk for a memory-cell on a master-slice type integrated circuit chip is shaped so as to be able to organize a cell in which an output port PT consisting of MIS transistors Q1, Q2 is added to normal SRAM constitution composed of MIS transistors Q1-Q8. When the bulk is used as an SRAM, a gate for the MISQ2 is connected to a latch circuit consisting of the MISs Q4-Q7, and Q2 is turned ON-OFF in response to the latch circuit. When the bulk is employed as a ROM, the gate for Q2 is grounded or wired fixedly at a power level. A reading word line WLR is brought to an H level, thus turning Q1 ON, then reading the state of Q2. Accordingly, various memory constitution can be adopted by wirings.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a master memory that can freely configure memory, etc., including random access memory, read-only memory, or both, in response to requests from customers.
A slice-type integrated circuit device having at least one output port including a transistor that can be operated as a read-only memory by wiring for fixedly applying a positive or ground power level to the gate. By providing a bulk that can be configured into static random access memory cells, both random access memory and read-only memory can be configured arbitrarily with extremely simple wiring changes. It has been made possible to do so.

[Industrial application field]

The present invention relates to a master slice type integrated circuit device, such as a gate array integrated circuit device, which has a built-in memory and can realize various logic circuit configurations according to customer's wishes.

[Conventional technology]

In general, in conventional fully custom integrated circuit devices, each type has its own unique random access
Memory (random accesses memo)
ry: RAM) or read only ψ memory (ROM)
are available.

Recently, semi-semiconductors such as gate array integrated circuit devices
There is also a strong demand for custom integrated circuit devices with built-in memory, but at present there are almost no devices that meet this demand.

[Problem that the invention seeks to solve]

When incorporating RAM and ROM into a semi-custom integrated circuit device that adopts the master slice method, it is possible to configure various RAM or ROM simply by changing the wiring, if requested by the customer. We must make it possible.

In the present invention, a bulk is prepared that can constitute an array of static RAM cells having peripheral circuits such as a plurality of address registers and row decoders, and at least one output port (single port). By setting the wiring appropriately, R
Provided is a gate array integrated circuit device that can easily configure AM or ROM.

[Means for solving problems]

The present invention will be explained with reference to FIGS. 1 to 3, which are diagrams for explaining embodiments.

In the gate array integrated circuit of the present invention, at least one transistor Q2 including a transistor Q2 which can be operated as a ROM by providing wiring for fixedly applying a positive side or ground side power supply level van or VSS to the gate. It has a bulk that can configure a static type RAM cell having an output port PT.

[Effect]

According to the above means, a bulk that can be used to configure a static type RAM having an output port is used, and a ROM is configured by wiring only the input/output portion, or a RAM is configured by wiring all transistors. can be easily implemented.

〔Example〕

FIG. 1 is for explaining one embodiment of the present invention.
A) shows an explanatory diagram of the main part, and (B) shows a circuit diagram of the main part.

In the figure, 1 is a chip, 2 is a logic section, 2-1 to 'l-n are basic cell columns, 3 is a memory, 4 is a RAM section, and 5
is a ROM section, 6 and 7 are peripheral circuits including address registers, row decoders, etc., and 8 is an I/O (in p
u t / o u t p u t ) buffer part, BC is basic cell, Pl and P2 are p channel MIS
) transistors, N1 and N2 respectively indicate n-channel MISI-transistors.

The logic section 2 shown in Figure (A) has a large number of basic cells B.
By changing the wiring pattern connecting these basic cells 80, a logic circuit according to the customer's wishes can be realized. Note that the basic cell BC is, for example, shown in FIG.
), and a large number of such circuits are formed on the board in advance.

The memory 3 in this embodiment uses a bulk that can configure a static RAM array having at least one input/output part, and can configure RAM or ROM by appropriately selecting the wiring. It is something that can be done.

Note that the number of output ports may be two (dual ports) or three (3-ports) or more.

Figure 2 is a concrete example to explain that the memory is fabricated using a bulk that can form an array of memory cells by adding one output port in addition to normal static RAM cells. It shows the main part circuit diagram.

In the figure, Ql to Q8 are transistors, BLW and BLW are write bit lines, BLR is a read bit line, WLW is a write word line, WLR is a read word line, and PT is an output port. There is. Note that among the transistors, Q4 and Q6 are p-channel MIS transistors, and the others are n-channel MIS transistors.

In this memory, in addition to the input/output means of a normal static RAM cell, transistors Q1 and Q2 constitute an additional output capacitor (PT), and transistors Q4. Q
5. Q6. Q7 constitutes a latch circuit. Note that transistors Q3 and Q8 are write gate transistors.

Since the operation of this memory is well known, its outline will be explained below.

Transistors Q3 and Q8 operate to write data into the launch circuit. These are normal static RA
Although it may have an output port function for reading in the same way as the input/output gate of the M cell, since another output port is added according to the present invention, it may be used only for writing (input). , that's how it is. In this case, it goes without saying that the bit lines BLW and the read amplifier connected to BLW can be omitted.

At the additional output port PT, the transistor Q2 is turned on and off in accordance with the data held by the latch circuit.

When reading, when the read word line WLR is set to "high" level ("H" level), transistor Q1
is turned on, and the data held in the latch circuit is output to the read bit line BLR via the transistor Q2.

With RAM wired as described above, input access can be performed independently and simultaneously with output access, and dual access is possible.
Functions similar to ports can also be added. Of course, it is also possible to use it as a normal single-port RAM, and next, a case where this RAM is used as a single-port RAM will be explained.

When configuring such a RAM, wiring must be performed for all transistors from the bulk state.

Figure 3 shows the ROM from the bulk that can constitute the RAM in Figure 2.
This figure shows a specific circuit diagram of the main parts when configuring the same system, and the same symbols as those used in FIG. 2 represent the same parts or have the same meanings.

In the figure, VDD indicates the positive power supply level, and VSS indicates the ground power supply level.

To construct a ROM as shown in FIG. 3 from the bulk that can construct the RAM described in connection with FIG. However, do not wire it to other transistors.

As is clear from the figure, a ROM-like operation is performed by applying the positive side power supply level V0 or the ground side power supply level VSS to the gate of the transistor Q2. In the case of FIG. 3, the writing gate transistors Q3 and Q8 of the static RAM cell are also used for reading, and of course serve as human output ports.

FIG. 4 shows a specific circuit diagram of main parts to explain that the memory is manufactured using a bulk that can constitute an array of static type RAM cells with two output ports. The same symbols as those used in FIGS. 2 and 3 represent the same parts or have the same meaning.

In the figure, Q9 and QIO are transistors, PT and PT' are output ports, and BLRI is the destination (
BLR2 is a source side read bit line, WLRI is a destination side read word line, and WLR2 is a source side read word line.

This memory is similar to the memory explained with reference to FIG. 2 in that transistors Q1 and Q2 constitute an output port PT, but in addition to this output port PT, it is composed of transistors Q9 and QIO. It has a so-called dual port function in terms of output function. Then, by wiring the output port PT' as a ROM, and wiring the output port PT as a single output port of a static RAM cell,
It can be used as a memory cell with additional ROM and output ports. In addition, in the wiring seen in Figure 4,
Output port PT' consisting of transistors Q9 and Q10
is an output capo-1-PT consisting of transistors Q1 and Q2.
Of course, it is possible to simultaneously read data read from the latch circuit and data of opposite polarity.

Figure 5 shows the ROM from the bulk that can constitute the RAM in Figure 4.
This figure shows a specific circuit diagram of the main parts when a system is constructed, and the same symbols as those used in FIGS. 3 and 4 represent the same parts or have the same meanings.

In order to construct the ROM and RAM as shown in FIG. 5 from the bulk that can construct the RAM described in connection with FIG. 4, the transistor Q9 constituting the output port PT'
and QIO are wired as shown in FIG. 5 to form a ROM, and each transistor for output port PT is wired to form a single port for output as in the embodiment shown in FIG. Just do it.

To access the static RAM cell in this case, the destination read word line WL
RI and destination side write word line WLW
You can use . Note that this point is completely the same as in the case where the RAM is configured in the embodiment shown in FIG.

Furthermore, it is of course possible to configure the ROM with a transistor used for the output port PT, and in that case, the output port P
It is optional to configure an output port or lROM on the T' side.

FIG. 6 shows an explanatory view of the main parts of another embodiment of the present invention.

In the figure, 21 is a chip, 22 is a dual port R
AM cell read and write amplifier, 23 is dual port RA, M section, 23' is single port R
AM section and ROM section, 23A is the memory cell area bit line dividing point, 24 is the single port RAM section and RO
Read and write amplifier for M section, 25 is a destination side lock buffer circuit, 26 is a single
Baud 1 - Clock buffer circuit for RAM section, 27 is a source side clock buffer circuit, 28 is a clock buffer circuit for ROM section, 29 is a destination side address register, 30 is an address register for RAM section , 31 is the source side address register, 32 is R
Address register for OM section, 33 is destination side row decoder, 34 is single port RAM
35 is a source side row decoder, and 36 is a ROM section row decoder.

As is clear from the figure, this embodiment corresponds to one using a bulk that can constitute a dual baud RAM as described with reference to FIGS. 4 and 5.

At the periphery of the memory there are four address registers and decoders marked 29, 30, 31, 32 and 33, 34, respectively.
35.36. R
Regarding the AM write word line WLW, one of the row decoders for the RAM section is shared, but it is also possible to add another decoder for this word line.

Further, the memory is divided into a dual port RAM section 23 and a single port RAM and ROM section 23', and the bit line in the memory is connected to the memory cell area bit line indicated by a two-dot chain line. The read/write amplifier 22 plays the role of Ilo for the dual port RAM section 23, and the single port RAM section and ROM section 23'
For this purpose, the read/write amplifier 24 plays the role of (10). The single port RAM section and ROM section 23' uses one bit of the dual baud 1-RAM as a single port RAM cell and a ROM cell.

The bulk of the aforementioned peripheral circuits, ie, address registers and row decoders, may be exactly the same for both the RAM section and the ROM section.

Furthermore, it is optional to reduce the area of the dual baud RAM section 23 and enlarge the single baud RAM section and ROM section 23', or vice versa.

〔Effect of the invention〕

In the gate array integrated circuit device according to the present invention,
Static type R with at least one output port
By using a bulk capable of configuring an AM and appropriately selecting and forming wiring, a RAM can be configured, or the output port can be configured as a ROM, or
It is possible to form a structure by mixing these, and selective formation of the wiring is extremely easy, so it can be easily implemented. If it were made easy, it would be possible to supply a semi-custom integrated circuit device with a built-in memory at a low cost, which can adopt various RAM and ROM configurations according to customer requirements, just by changing the wiring.

[Brief explanation of drawings]

FIG. 1 is for explaining one embodiment of the present invention, and (A)
2 is an explanatory diagram of the main part, (B) is a circuit diagram of the main part, FIG. 2 is a specific circuit diagram of the main part of the memory used when implementing the present invention, and FIG. 3 is a specific diagram of the main part when configuring the ROM. 4 is a specific essential circuit diagram showing another example of a memory used when implementing the present invention; FIG. 5 is a specific essential circuit diagram when configuring a ROM; FIG. 6 each shows an explanatory view of a main part of an embodiment of the present invention. In the figure, 1 is the chip, 2 is the logic section, 3 is the memory, 4 is the RAM section, 5 is the ROM section, and 6 and 7 are the addresses.
Peripheral circuits including registers and decoders, etc., 8 is the 110 section, Ql to QIO are transistors, PT and PT' are output ports, BLW and BLW are write bit lines, BL
R is the read bit line, WLW is the write word line, W
LR indicates read bit lines, respectively. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Akira Aitani Representative Patent Attorney: Hiroshi Watanabe - Explanatory Diagram of Main Parts of an Embodiment of the Present Invention (A) Figure 1 (B) Main Part Circuit of an Embodiment of the Present Invention Fig. 1 Fig. BLR Main part circuit diagram of this complete example - Fig. 2 Fig. 3 Main part circuit diagram when ROM is used

Claims (1)

[Claims] A static random type memory device having at least one output port including a transistor that can operate as a read-only memory by providing wiring for fixedly applying a positive side or ground side power supply level to the gate. - A master slice type integrated circuit device comprising a bulk pattern capable of configuring an access memory cell.