JPS62177116U - - Google Patents
Info
- Publication number
- JPS62177116U JPS62177116U JP1986063620U JP6362086U JPS62177116U JP S62177116 U JPS62177116 U JP S62177116U JP 1986063620 U JP1986063620 U JP 1986063620U JP 6362086 U JP6362086 U JP 6362086U JP S62177116 U JPS62177116 U JP S62177116U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- optical
- conversion element
- pulse width
- electrical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 7
- 230000003287 optical effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Networks Using Active Elements (AREA)
- Dc Digital Transmission (AREA)
- Optical Communication System (AREA)
Description
第１図はこの考案の一実施例である無調整絶縁
回路の概略構成を示すブロツク図である。第２図
は第１図の回路各部における出力信号波形を示す
図である。第３図はこの考案の一実施例において
用いられるパルス幅変調器の回路構成の一例を示
す図である。第４図は第３図に示されるパルス幅
変調器の回路動作を示すための信号波形図である
。第５図は従来のフオトカプラを用いた絶縁回路
の構成を示す回路図である。
図において、９はフオトカプラ、１７は発光ダ
イオード、１８はフオトトランジスタ、２１はパ
ルス幅変調器、２２はドライブ回路、２３は積分
器、２４は増幅器である。なお、図中、同一符号
は同一または相当部分を示す。
FIG. 1 is a block diagram showing a schematic configuration of an unadjusted isolation circuit which is an embodiment of this invention. FIG. 2 is a diagram showing output signal waveforms at various parts of the circuit shown in FIG. 1. FIG. 3 is a diagram showing an example of the circuit configuration of a pulse width modulator used in an embodiment of this invention. FIG. 4 is a signal waveform diagram showing the circuit operation of the pulse width modulator shown in FIG. 3. FIG. 5 is a circuit diagram showing the configuration of an insulating circuit using a conventional photocoupler. In the figure, 9 is a photocoupler, 17 is a light emitting diode, 18 is a phototransistor, 21 is a pulse width modulator, 22 is a drive circuit, 23 is an integrator, and 24 is an amplifier. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ための無調整絶縁回路であつて、 外部から与えられるアナログ信号をパルス幅変
調して出力するパルス幅変調手段と、 前記パルス幅変調手段出力を受けて電気信号に
変換する電気―光変換素子と、 前記電気―光変換素子からの光信号を受けて電
気信号に変換する光―電気変換素子と、 前記光―電気変換素子からの出力信号を受けて
積分し、当該光―電気変換素子からの出力信号を
アナログ信号に変換する積分手段とを備える、無
調整絶縁回路。 (2) 前記電気―光変換素子は発光ダイオードで
あり、前記光―電気変換手段はフオトトランジス
タである、実用新案登録請求の範囲第１項記載の
無調整絶縁回路。[Claims for Utility Model Registration] (1) A non-adjustable isolation circuit for electrically insulating an input signal and an output signal, which is a pulse width modulation circuit that pulse width modulates an externally applied analog signal and outputs the pulse width modulated signal. means; an electro-optical conversion element that receives the output of the pulse width modulation means and converts it into an electrical signal; an optical-electrical conversion element that receives the optical signal from the electro-optic conversion element and converts it into an electrical signal; A non-adjustable insulating circuit comprising an integrating means for receiving and integrating an output signal from an optical-to-electrical conversion element and converting the output signal from the optical-to-electrical conversion element into an analog signal. (2) The non-adjustable insulating circuit according to claim 1, wherein the electro-optical conversion element is a light emitting diode, and the photo-electric conversion means is a phototransistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986063620U JPS62177116U (en) | 1986-04-25 | 1986-04-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986063620U JPS62177116U (en) | 1986-04-25 | 1986-04-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62177116U true JPS62177116U (en) | 1987-11-10 |
Family
ID=30899018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986063620U Pending JPS62177116U (en) | 1986-04-25 | 1986-04-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62177116U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018518914A (en) * | 2015-06-25 | 2018-07-12 | マイクロ モーション インコーポレイテッド | Input protection circuit for analog optocouplers |
-
1986
- 1986-04-25 JP JP1986063620U patent/JPS62177116U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018518914A (en) * | 2015-06-25 | 2018-07-12 | マイクロ モーション インコーポレイテッド | Input protection circuit for analog optocouplers |
| US10425045B2 (en) | 2015-06-25 | 2019-09-24 | Micro Motion, Inc. | Input protection circuit for an analog optocoupler |
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