JPS62176239A - Packet transmission delay measuring system - Google Patents

Abstract

PURPOSE:To eliminate the effect of a measured communication line onto traffic by informing a signal representing the packet sending from the transmission side to the reception side through other line than the transmission line and allowing the reception side to measure the time until the arrival of packet after the signal is detected. CONSTITUTION:A packet transmission data bus 101 and a signal line 102 are provided between the transmission side and the reception side. A measuring packet sending signal representing the sending of a packet is sent to a signal line by a measuring packet sending signal generating means 103 at the transmission side. A packet transferred from a comparison means 104 at the reception side via the data bus 101 and the same packet received via a packet communication line are collated and a transmission delay time measuring means 105 measures the time from the detection of a measured packet sending signal till the coincidence of collation of the packets to measure the transmission delay of the packet.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for determining the problems (Figs. 1 to 2) Working examples First Example (Figure 3) Second Example (Figures 4 to 9) Effects of the Invention [Summary] Measuring the packet transmission delay from the packet transmission circuit to the packet reception circuit via the packet communication path In this method, the sending side sends the packet to the packet communication path and also transfers the packet to the data bus for packet transfer.
Furthermore, a measurement packet sending signal is sent to the signal line. On the receiving side, the packet transmission delay time is determined by measuring the time from when the measurement packet transmission signal is detected to when the same bucket 1- as the packet transferred to the data bus is received via the packet communication path.

Also, in a method for measuring the transmission delay of multiple packets in a system in which multiple packet transmitting circuits and multiple packet receiving circuits are connected via a packet communication network, a flag is set in the packet and sent to the packet communication network. At the same time, a measurement packet sending signal is sent to the signal line. On the receiving side, the packet transmission delay time is determined by measuring the time from when the measurement packet sending signal is detected to when the flag is detected. At this time, the transmission delay of a plurality of packets is simultaneously measured by transmitting the measurement packet transmission signal by time division multiplexing.

[Industrial application field]

The present invention relates to a method for measuring packet transmission delay, and particularly to a method for measuring packet transmission delay without affecting a packet communication channel and unaffected by communication channel speed.

In a packet network, the delay time of a bucket (bucket) is an element in network cost, and therefore there is a need for a method that can efficiently and accurately measure packet transmission delay time.

[Conventional technology]

The conventional method for measuring packet transmission delay is to generate a control packet for measurement from the packet transmitting side,
Generally, the control packet is stamped with an absolute time and transmitted, and when the measurement control packet is detected on the packet receiving side, the packet transmission delay time is measured from the difference from the arrival time.

[Problems that the invention attempts to resolve]

Such a conventional packet transmission delay measurement method requires a circuit to control a special bucket 1- called a measurement control packet in order to measure packet transmission delay.
This special packet becomes traffic on the measurement channel, and therefore there is a problem in that accurate delay time measurement cannot be performed.

[Means for solving problems]

In order to solve these problems of the prior art, in the first invention, as shown in the principle block diagram of FIG. 1, the packet transmission delay from the packet transmission circuit to the packet reception circuit via the packet communication path is reduced. In the measurement method, a data bus for packet transfer (1
01) and a signal line (102).

Reference numeral 103 denotes a measurement packet sending signal generating means for sending a measurement packet sending signal indicating the sending of a packet as a signal IJJI (102), and is provided on the sending side.

Reference numeral 104 refers to comparison means for comparing the packet transferred via the packet transfer data bus (lot) with the same packet received via the packet communication path, and reference numeral 105 refers to a comparison unit for comparing the packet transferred via the packet transfer data bus (lot) with the same packet received via the packet communication path. Transmission delay time measuring means for measuring time, these are provided on the receiving side.

In addition, in the second invention, as shown in the principle block diagram of FIG. In the method of measuring transmission delay,
A signal line (201) is provided to connect a plurality of packet transmitting circuits and a plurality of packet receiving circuits.

202 is a flag adding means for setting a measurement flag in a packet transmitted via a packet communication network, and 203 is a signal line (201') for transmitting a measurement packet sending signal indicating the sending of a packet.
) A measurement packet sending signal generating means for sending out a measurement packet to
These are provided in each packet transmission circuit.

204 is a flag detecting means for detecting a flag in a packet; 205 is a transmission delay time measuring means for measuring the time from detection of a measurement packet sending signal to detection of the flag; these are provided in each packet receiving circuit.

[For production]

In the first invention, a packet is sent from the sending side to a packet communication network, the packet is also transferred to a data bus for packet transfer, and a measurement packet sending signal is sent to a signal line. On the receiving side, the packet transmission delay time is determined by measuring the time from when the measurement packet transmission signal is detected until the same packet as the packet transferred to the data bus is received via the packet communication path.

In the second invention, a flag is set in the packet and sent to the packet communication network, and a measurement packet sending signal is sent to the signal line. On the receiving side, the packet transmission delay time is determined by measuring the time from when the measurement packet sending signal is detected to when the flag is detected. At this time, the transmission delay of a plurality of packets can be measured simultaneously by transmitting the measurement packet transmission signal by time division multiplexing.

〔Example〕

(First example) FIG. 3 shows the configuration of an embodiment of the present invention.

1 is a transmitting circuit including a latch circuit 10°, an address latch 12. Comparison circuit 13. It has a gate 14. 2 is a receiving circuit, and includes a latch circuit 11. - Comparison circuit 15.
Shift register 16.1? , delay measurement counter 18.
It has a gate 19. The transmitting circuit 1 and the receiving circuit 2 are connected by a packet communication path 3 to which traffic under measurement conditions is applied. 4 is a control circuit for measuring packet transmission delay time, and a state control circuit 20
have.

Transmission circuit 1. The receiving circuit 2 and the control circuit 4 are connected by a data bus, an address bus, various control signal lines, etc. which are separate lines from the packet communication path 3.

In the transmission circuit 1, the latch circuit 10 latches the transmission packet and transmits it to the packet communication path 3, and also outputs it to the gate 14. The address latch 12 has the address of the packet to be measured set in advance from the control circuit 4 via the bus for setting the address to be measured. The comparison circuit 13 has two data inputs, compares both in parallel, and outputs a comparison result indicating that the two are greater or smaller or equal.

In the receiving circuit 2, the latch circuit 11 latches the received packet and sends it out, and also outputs it to the gate 19. The shift register 16 is output via the gate 14,
The transmission packet input via the data bus is set,
Further, the shift register 17 is set with the received packets inputted through the gate 9, and outputs the set data strings in parallel while shifting them. Comparison circuit 15 is 2
It has a port data input, and compares the data string of the transmitted packet in the shift register 16 and the data string of the received packet in the shift register 17 in parallel, and outputs a comparison result indicating that the two are larger or smaller or equal. The delay measurement counter 18 is used to measure packet delay.

In the control circuit 4, a state control circuit 20 generates signals on various signal lines and also performs a state management function.

The state control circuit 20 in the control circuit 4 stores the address of the packet to be measured in advance in the address latch 1 in the transmission circuit 1.
2, and sends a measurement start signal to the latch circuit 10 in the transmitter circuit 1 at an arbitrary time to notify the start of measurement. When the latch circuit 10 receives this notification, it transfers only the address part of the received packet to the comparison circuit 13.

The comparison circuit 13 compares the address of the received packet from the latch circuit 10 and the measured address latched in the address latch 12, and when the same value is detected, sends a measurement packet transmission start signal to the gate 14. The data of the packet under test is output from the latch circuit 10 to the control circuit 4.
At the same time, a transmission start signal is sent to the state control circuit 20 in the control circuit 4. Accordingly, the control circuit 4 notifies the receiving circuit 2 of the data. In this case, the data notified to the receiving circuit 2 has a data length that allows it to be determined that it is a measurement packet.

In the receiving circuit 2, the notified data is sequentially stored in the shift register 16. In addition, the control circuit 4 receives the measurement packet transmission start signal from the transmitting circuit 1, and the receiving circuit 2
A measurement start notification signal is sent to the gate 19, and the gate 19 is enabled by this signal. As a result, data is transferred from the latch circuit 11 to the shift 1 register 17, and the data is sequentially transferred to the shift 1 register 17. It will be done. At the same time, the delay measurement counter I8 also starts counting in response to the measurement start notification signal. Comparison circuit 15 compares and collates one column of parallel data input from both shift registers 16 and 17, and if they do not match, shifts shift register 17 and supplements new data from latch circuit 11 while comparing. Continue checking.

When the data match in the comparator circuit 15, it is determined that the measurement is completed and a measurement completion notification signal is output to the state control circuit 20 in the control circuit 4, and at the same time, the operation of the delay measurement counter 18 is inhibited. The count value is notified to the control circuit 4. This allows the control circuit 4 to know the transmission delay time for the packet under test.

The above operation may be performed repeatedly, or may be stopped every time - measurements are completed. Selection of such an operating mode is controlled by the state control circuit 20.

In this way, the packet transmission delay can be measured. However, when trying to measure the delay of multiple packets simultaneously, since the transmitting circuit does not have information on the receiving circuit side, there is a risk of duplication of measurement packets in the receiving circuit, and the measurement packet sending signal is sent to the receiving circuit. It is necessary to provide a sending function.

(Second Embodiment) FIG. 4 shows another embodiment of the present invention, in which the delay of multiple packets can be measured simultaneously without causing fluctuations in the traffic on the transmission path for measurement. It is something. The figure shows the overall configuration, 1 1.1 2. -1 n
is a transmitting circuit, 2-1°2-2. -.-22-n is a receiving circuit, 4 is a control circuit, and each transmitting circuit and receiving circuit are respectively connected to the packet communication 11Q3A via a transmission path.

Further, each transmitting circuit, receiving circuit, and control circuit 4 connect to a data bus 5. They are connected in a helical manner by an address bus 6, connected in parallel with a clock signal line 7, and connected in a loop by a measurement packet sending signal line 8.

Each transmitting circuit has a function of setting a measurement flag on a part of the packet to be measured and transmitting it to the communication path where normal data is being transmitted. Each receiving circuit also has a function of detecting a measurement flag from a received packet while normal data is being received. Each transmitting circuit and receiving circuit are synchronized by a clock from the control circuit, and the transmitting circuit has a measurement packet designation register that can be rewritten arbitrarily from the control circuit, and a one-to-one connection to the receiving circuit.
The receiver circuit has a time slot designation register that is provided corresponding to the measurement packet transmission signal and designates the time slot assignment of the measurement packet transmission signal, and the reception circuit has a delay data register that holds the value of the delay time.

Further, FIG. 5 shows the clock timing in this embodiment. The clock is generated by the clock generation circuit in the control circuit 4, CKO is the basic clock for generating the measurement bucket 1 transmission signal by time division multiplexing, and CKI is the basic clock for generating the measurement packet transmission signal generated by time division multiplexing. This is a synchronization clock for synchronizing the transmitting circuit and receiving circuit.

FIG. 6 is a block diagram showing the detailed configuration of the control circuit 4. As shown in FIG. 21 is a clock generation circuit, and clock CKO
, CKI is generated. 22 is a packet T.

The H table is set by arbitrarily rewriting the values of the transmission header (T, H) of the packet. The decoder command decodes the packet address generated by the CPU 24 and enables buffer 4, thereby making the reception status data readable. It also enables the output of the register and makes it possible to read the value of the transmission header. Also buffer 27.2
8 to enable reading of time slot data, measurement start signal, and circuit select data. Here, the buffer 27 is enabled, and at the same time the T and H registers 26 are updated and the transmission header value read from the packet T and H table 22 is written. The buffer 29 returns the measurement packet sending signal and sends it to the receiving circuit.

FIG. 7 is a block diagram showing the detailed configuration of each transmitting circuit. Reference numeral 31 denotes a transmitting circuit select register, which is updated by the decoder 32 every time a packet is measured, and holds the value of the transmitting circuit number written from the data bus. −
The number output circuit 33 compares this value with the transmitting circuit number previously written in the transmitting circuit number register 34 by means such as a low reswitch, and when they match, the decoder 3
Enable 5. This is controlled via the decoder 35 and the time slot designation register 36. The measurement packet designation register 379 and the measurement start signal register 38 are cleared, and the data on the data bus output from the control circuit is written. The transmission control circuit 39 detects a packet on the transmission path, clears the T and H registers 40, and writes the value of the transmission header. - The number output circuit 41 is the measurement packet specification register 37
The measurement flag addition circuit 42 is enabled by detecting a match between the value held in the T and H registers 40 and the value of the T,H register 40, and thereby the measurement flag addition circuit 42 adds a flag to the packet on the transmission path. The measurement packet transmission signal adding circuit 43 adds a measurement packet transmission signal to the measurement packet transmission signal from the previous stage transmitting circuit at the time slot designated by the time slot designation register 36, and transmits the signal to the next stage.

FIG. 8 is a block diagram showing the detailed configuration of each receiving circuit. A receiving circuit select register 51 is updated each time the control circuit selects a receiving circuit by the decoder 52, and holds the value of the receiving circuit number written from the data bus. The reception state register 53 is cleared in response to the output of the decoder 52 and the reception state is written therein, and the delay data register 54 is cleared by flag detection by the flag detection circuit 62 and delayed data is written in accordance with the output of the decoder 52.

- The number output circuit 55 compares the value of the reception circuit select register 51 with the reception circuit number written in advance in the ambiguous circuit number register 56 by means such as a low reswitch, and when they match, the buffer 57. 58, which outputs the receive status and delayed data to the data bus. This also clears the delay counter 59. Reference numeral 60 denotes a packet transmission signal detection circuit, which causes the delay counter 59 to start counting when a measurement packet transmission signal corresponding to the number set in the receiving circuit number register 56 is detected. Reception control circuit 6I
When detecting a packet on the transmission path, it clears the flag detection circuit 62, and when the flag detection circuit 62 detects a flag, it stops counting the delay counter 59.

The packet delay measurement procedure in the embodiment shown in FIG. 4 is shown by the time chart in FIG.

First, data is written into each register in the transmitting circuit (FIG. 9). Next, the measurement start signal register 38
When "1" is written in (Fig. 9), the values of the T and H registers 40 and the value of the measurement packet constant register 37 are compared according to the timing taken by the transmission control circuit 39, and a mismatch is detected. If , wait for the next packet, and if it matches, add a measurement flag to the packet on the transmission path,
At the same time, a measurement packet sending signal is added to the time slot designated by the time slot 1 designation register 36.

The receiving circuit detects the measurement packet sending signal corresponding to the receiving circuit from the measurement bucket sending signal using the time slot that corresponds one-to-one with the receiving circuit number (Fig. 9 ■), thereby starting the delay counter 59. let Next, the reception control circuit 61 extracts the portion to which the flag has been added from the packet on the transmission path, and the flag detection circuit 62 detects the measurement flag (9th
Figure ■).

Upon detection of the flag, the delay counter 59 stops counting, writes the value of the delay counter 59 to the delay data register 54, and simultaneously sends a signal to the reception status register 53.

The reception status register 53 is a counter that does not indicate the status of the delay counter 59, and it is written therein whether the delay counter 59 has overflowed, has stopped counting due to the output of the flag IQ, or is in any other status. It is read out at regular intervals. When the reception status register 53 is in a state indicating a counter overflow, the packet is treated as discarded, and the reception status register 53 is cleared. Also, a flag is detected and the delay counter 5
9 has stopped, read the delay data from the delay data register 54 before starting the next cycle (Fig. 9■),
Clear the reception status register 53. delay counter 59
is cleared by reading delayed data or by overflow. In the next measurement cycle, the data in the register of the transmitting circuit is updated if there is a change in the measurement packet ((*) in FIG. 9), but if there is no change, the data is not rewritten.

In the embodiment shown in FIG. 4, transmission delays of a plurality of packets can be measured simultaneously by transmitting the measurement packet transmission signal in a time-division manner.

〔Effect of the invention〕

As explained above, according to the method of the present invention, a signal indicating packet transmission from the transmitting side is notified to the receiving side through a line separate from the transmission path, and after detecting this signal on the receiving side, the packet is transmitted via the transmission path. Since the packet transmission delay time is determined by measuring the time until the packet arrives, it is possible to measure the packet transmission delay without affecting the traffic on the measurement channel. In the method of the present invention, by performing delay measurement according to instructions from the measurement circuit, delay measurement can be performed intermittently and continuously at appropriate time intervals.

Furthermore, in the second invention, by transmitting the measurement packet transmission signal by time division multiplexing, the transmission delays of a plurality of packets can be measured simultaneously, and the hardware scale can thereby be reduced.

[Brief explanation of drawings]

1 and 2 are diagrams showing the basic configuration of the present invention, FIG. 3 is a diagram showing one embodiment of the present invention, FIG. 4 is a diagram showing another embodiment of the invention, and FIG. 6 is a block diagram showing the detailed configuration of the control circuit, FIG. 7 is a block diagram showing the detailed configuration of the transmitting circuit, and FIG. 8 is a block diagram showing the detailed configuration of the receiving circuit. , FIG. 9 is a time chart showing the procedure for measuring packet delay. 1. 1-1. 1-2.-“-+l n: Transmission circuit 2.2-duplex, 2-2, -.2-n: Receiving circuit 3: Packet communication path 3A: Packet communication network 4: Control circuit to, tt: Latch circuit 12 Near address launch 13.15: Comparison circuit 14.19: Gate 16.17: Shift register] 8: Delay measurement counter 20: State control circuit 21: Crochet generation circuit 22: Packet T, H Table 23: Decoder 24: CPU 25, 27.28.29: Buffer 26: T, H register 31: Transmission circuit select register 32.35: Decoder 33 match detection circuit 34: Transmission circuit number register 36: Time slot specification Register 37: Measurement packet designation register 38: Measurement start signal register 39: Transmission control circuit 40: T, H register 41-match detection circuit 42: Measurement flag addition circuit 43: Measurement packet sending signal addition circuit 51: Receiving circuit selection register 52 : Decoder 53: Receipt register 54: Delayed data register 55 - Match detection circuit 56: Receive circuit number register 57.58: Buffer 59: Delay counter 60: Packet sending signal detection circuit 61: Reception control circuit 62: Flag detection circuit

Claims (2)

[Claims] (1) In the method of measuring the packet transmission delay from the packet transmission circuit to the packet reception circuit via the packet communication path, a data bus for packet transfer (10
1) and a signal line (102), a measurement packet sending signal generating means (103) for sending a measurement packet sending signal indicating the sending of a packet to the signal line (102) is provided on the transmitting side, and the data bus (101) and a comparison means (104) for comparing the packet transferred via the packet communication path with the same packet received via the packet communication path; Transmission delay time measuring means (105
) is provided on the receiving side. (2) In a method for measuring the transmission delay of a plurality of packets in a system in which a plurality of packet transmission circuits and a plurality of packet reception circuits are connected via a packet communication network, the plurality of packet transmission circuits and a plurality of packets A signal line (201) connecting a receiving circuit is provided, a flag adding means (202) for setting a measurement flag in a packet transmitted via a packet communication network, and a measurement packet sending signal indicating sending of the packet is connected to the signal line. (201) is provided in each packet transmitting circuit, and a flag detecting means (203) for detecting a flag in the packet is provided.
4), and transmission delay time measuring means (20) for measuring the time from detection of the measurement packet sending signal to detection of the flag.
5) is provided in each packet receiving circuit, and the transmission delay of a plurality of packets can be measured simultaneously by transmitting the measurement packet transmission signal by time division multiplexing.