JPH01140240A - Test signal sending system - Google Patents

Abstract

PURPOSE:To make a trigger line unnecessary and to make a test in one slave unit rapid by transmitting only data to which the address of the slave unit to execute the test is added. CONSTITUTION:A shift register 2 is provided for the output of a test data generator 1, a setter 3 to output the address of the unit to execute the test is provided, a shift register 4 is provided on its output side and outputs of register 2 and 4 are supplied to an OR circuit 5. By the control of a control part 6, data by blocks of the output of the generator 1 are successively stored into the register 2, the data of the preceding block are sent and the address from the setter 3 is stored into the register 4 in the first half while the data of the next block are stored and block data are sent in the second half while the register 2 stores the data. Consequently, data D1-Dn to which an address Ad1 of the slave unit to execute the test is added are jointedly sent in block units from the output of the OR circuit 5.

Description

[Detailed Description of the Invention] [Summary] Regarding a test signal sending method for testing a receiving unit when data is transmitted from one unit to a plurality of receiving units connected in parallel, a trigger wire is provided. In order to provide a test signal sending method that does not require the use of a single incoming unit and allows the test to be performed quickly when testing is performed using one receiving unit, the first shift register includes:
The data of the output of the test data generator is stored one block at a time sequentially, and the data of the previous block is sent out in the first half while the data of the next block is stored, and the test data is stored in the second shift register. The output of the address setter for setting the address of the receiving unit to be sent is stored, and is output in the second half while the first shift register is storing the data of the block.

[Industrial application field]

The present invention improves the test signal sending method when transmitting data from one unit to multiple receiving units connected in parallel and testing whether errors occur on the bus between them and within the receiving units. Regarding.

An example of a system to which the present invention is applied is shown in FIG. 6, in which a master unit 1-10 connects slave units 11, 12, . ...Transmit data to In.

In this case, in order to test whether an error occurs in the lotus and slave unit between them, for example, a PN pattern test signal is transmitted from the mask unit 10 side and the slave unit is tested. When testing a slave unit and then testing another slave unit, it is desirable to be able to perform the test efficiently without requiring a trigger wire.

[Conventional technology]

A conventional example will be explained below using figures.

Figure 7 is a block diagram of the conventional test signal sending system;
The figure is a time chart of each part in Figure 7, (A) is the output of the test data generator, (B) is the data output timing of the memory retention shift register, (C) is the output of the memory retention shift register, (D) indicates the output of the trigger clock generation circuit.

For example, the PN pattern data output from the test data generator 1 shown in FIG. 7 is data DI, D2, D2, . D3°... is stored in the memory holding shift register 8, and if the number of slave units is n as shown in FIG. 6, for example, the second data D2 is stored as shown in (B). During this time, the first data D1 is sent out once.

Therefore, as shown in (C), the output of the memory holding shift register 8 is to send data D1 n times in the first frame and data D2 n times in the second frame.

Slave units 11, 12 shown in FIG.・・i
n is Adl, Ad2 .・・・Adn
At the timing of Dl, D2.・Take in the data of =Dn and test the bus up to the own slave unit and the own slave unit.

Note that a trigger clock indicating a break in data is transmitted from the trigger clock generation circuit 7 to each slave unit 11, 12, . . . via a trigger line. ...I'm sending it to In.

[Problem that the invention seeks to solve]

However, when testing with one slave unit,
Also, when testing on one slave unit (such as when testing on another slave unit), the data DI, D2. ...It is sufficient to send Dn once, but if there are n slave units, it is sent n times, so it takes extra time to perform the test, which is inefficient, and requires a trigger line to send the trigger clock. There is a problem.

An object of the present invention is to provide a test signal sending method that does not require the use of a trigger line (and can quickly perform a test when testing with one slave unit).

[Means for solving problems]

FIG. 1 is a diagram of the principle of the present invention, (A) is a block diagram showing the configuration, and (B) is a time chart.

As shown in FIG. 1(A), a first shift register 2 is provided at the output of the test data generator 1, an address setter 3 for outputting the address of the unit to be tested, and a second shift register at the output. 4, and the outputs of the first shift register 2 and the second shift register 4 are outputted via an OR circuit 5.

Then, under the control of the control unit 6, the first shift register 2 is made to sequentially store one block of data output from the test data generator 1, as shown in a of (B), As shown in b of (B), the data of the previous block is sent out in the first half while the data of the next block is being stored, and as shown in c of (B), the second shift register 4
The address output from the address setter 3 is stored in the first shift register 2, and the address is output in the second half while the first shift register 2 stores the data of the block.

[For production]

According to the present invention, the address (Adl) of the slave unit to be tested is attached to the output of the OR circuit 5 in FIG. 1(A) in block units, as shown in d in FIG. 1(B). Data DI, D2. . . . Since Dn is sent out continuously, testing on one slave unit can be performed quickly, and since the address is attached, there is no need to provide a trigger line.

On the slave unit side, this test signal is taken in only by the slave unit whose address is Adl and is tested.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram of the test signal sending system according to the embodiment of the present invention, and FIG. 3 is a time chart of each part in FIG.
(D) corresponds to points a-sd in FIG.

A case in which one slave unit is tested and then another slave unit is tested will be described with reference to FIGS. 2 and 3.

For example, the PN pattern data outputted from the test data generator 1 of FIG. 2 is data Di, D2°D3 . ... is input and stored in the shift register 2 under the control of the control unit 6, and as shown in (B), the previous data is output in the first half while the data of the next block is being stored.

On the other hand, the address of the slave unit to be tested, for example Adl, is set in the address setter 3, and as shown in (A), the data D1 of the first block is stored in the first half of the shift register 2, and each block Data DI, D2
．． D3. ... is output in the second half stored in shift register 2.

Therefore, at the output of the OR circuit 5, as shown in (D), each data Di, D2 . D3. ... is sent with the address Adl of the slave unit to be tested added to the beginning.

Next, the slave unit side will be explained.

FIG. 4 is a block diagram of a slave unit according to an embodiment of the present invention, and FIG. 5 is a time chart of each part in FIG.
~(D) corresponds to points a%d in FIG.

The sent test signal is input to the shift register 20 and separated into an address Adi and data Di as shown in (B) for each block, and the address Adi is input to the comparator circuit 21.
The data Di is input to the AND circuit 23.

In the comparator circuit 21, the input address Adi is compared with the address of its own unit, and if they match, a match pulse is output.

This coincidence pulse causes the data separation pulse generation circuit 22 to
outputs a pulse synchronized with the separated data Di as shown in (C) and adds it to the AND circuit 23,
is sent to the continuous pulse forming circuit 24 to form continuous data as shown in (D).

This data is converted into a frame pattern that passes through the slave unit main circuit 26 in the intra-unit passing pattern forming circuit 25, and after passing through the slave unit main circuit 26, the data extraction circuit 27 creates a continuous frame pattern as shown in (D). The data is converted to the original data, and an error bit extraction circuit 28 checks whether there are any bit errors based on the PN pattern in this case.

If there is an error bit, it is displayed on the error display circuit 29.

In this way, the slave unit salt bath and slave unit tests from the mask unit 10 shown in FIG. 6 are performed.

Incidentally, when checking for bit errors on the bus from the master unit JO to the slave unit, it is sufficient to flow data as shown by the dotted line in FIG.

Furthermore, when testing another slave unit next time, the address set by the address setter 3 in FIG. 2 can be changed.

That is, since only the data with the address of the slave unit to be tested is sent from the test signal transmitting side, a trigger line is not necessary and the test on the slave unit can be performed quickly.

〔Effect of the invention〕

As explained in detail above, according to the present invention, only the data with the address of the slave unit to be tested is sent from the test signal transmitting side, so a trigger line is not necessary, and one
This has the effect of allowing tests to be quickly performed on two slave units.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a block diagram of a test signal sending system according to an embodiment of the present invention, Fig. 3 is a time chart of each part of Fig. 2, and Fig. 4 is an embodiment of the present invention. 5 is a time chart of each part in FIG. 4, FIG. 6 is a block diagram of an example of a system to which the present invention is applied, and FIG. 7 is a block diagram of a conventional test signal sending system. Figure, 8th
The figure is a time chart of each part of FIG. 7. In the figure, 1 is a test data generator, 2 is a first shift register, a shift register, 3 is an address setter, 4 is a second shift register, a shift register, 5 is an OR circuit, 6 is a control unit, and 7 is a control unit. Trigger clock generation circuit; 8, memory retention shift register; 10, mask unit; 11.12. in is a slave unit, 20 is a shift register, 21 is a comparison circuit, 22 is a data separation pulse generation circuit, 23 is an AND circuit, 24 is a continuous pulse formation circuit, 25 is an intra-unit passing pattern formation circuit, 26 is the main slave unit 27 is a data extraction circuit, 28 is an error pit extraction circuit, and 29 is an error display circuit. Agent Patent attorney Igeta Page-・F-Ihi June's raw wool ψ-D] No. 1m Fig. 2 Fig. 3

Claims (1)

[Claims] When sending continuous test data from the test data generator (1) to any one of the plurality of units connected in parallel, the output of the test data generator (1) A first shift register (2) is provided, and an address setter (3) that outputs the address of the unit to be tested is provided, and a second shift register (4) is provided at this output, and the first shift register ( 2
) and the output of the second shift register (4) are outputted via the OR circuit (5), and under the control of the control unit (6), the output of the first shift register (
2), the data of the output of the test data generator (1) is sequentially stored one block at a time, and the data of the previous block is sent out in the first half while the data of the next block is being stored; The address output by the address setter (3) is stored in the second shift register (4), and is output in the second half while the first shift register (2) is storing block data. A test signal transmission method characterized by: