JPS62176175A - Semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the integration of both elements, by using a high purity layer for InGaAs, which is to become a light sensitive layer, using an InP layer for a multiplying layer, and using an InAlAs layer between both layers, in an avalanche photodiode; and employing a field effect transistor, which is formed at an InAlAs/InGaAs interface, for an amplifying element; so that many parts of a semiconductor layer are commonly used. CONSTITUTION:Pairs of electrons and holes are generated in a first semiconductor layer 12 with incident light. Owing to an internal electric field, the electrons move in the direction of a substrate 11 and the holes move in the direction of a P-type InP layer 16. Avalanche multiplication of the holes occur owing to the avalanche phenomenon by a high electric field, which is formed in an N-type InP layer 15. InAlAs layers 13 and 14 reduce a barrier for the movement of the holes from a light absorbing InGaAs light sensitive layer 12 to the InP from a light absorbing InGaAs light sensitive layer 12 to the InP multiplying layer 15. Thus the accumulation of the holes is suppressed and the high-speed operation can be performed. The change in potential at a load resistance with the output current of an ava lanche photodiode is applied to a gate electrode 18 of a field effect TRS. The potential is increased with the incident light, and the potential on the side of semiconductors 13' and 14' is decreased. Therefore, a recess at the interface between the layer 12 and 13' becomes large and the amount of an electron gas layer is increased. Thus the output current of the field TRS is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device in which a high-performance light receiving element for optical transmission and an electron amplification element are integrated on the same semiconductor substrate.

(Conventional wave (, Toi and its problems) An example of a conventional device of this type is shown in Fig. 1 (Patent application No. 58
-176368 “Receiver”). An n-type InGaAs layer 2 is laminated on a semi-insulating InP substrate 1, and p-type InGaAs layers 3 and 4 are formed within the same layer.

Here, the PIN photodiode is constructed in layers 2 and 3, and the field effect transistor is constructed in layers 2 and 4, respectively. A field effect transistor is composed of a drain electrode 5, a gate electrode 7, and a source electrode 6. Note that the photodiode in this device has a PIN structure and does not have an internal multiplication effect like an avalanche photodiode. P
IN photodiodes have inferior noise characteristics compared to avalanche photodiodes. Therefore, using an avalanche photodiode as a light receiver for optical transmission results in a high-performance light receiving element. However, avalanche
Compared to PINFOI diodes, photodiodes have problems such as a complicated structure and the application of a high electric field, and so far, monolithic integration with electronic amplification elements has not been realized.

(Objective of the Invention) An object of the present invention is to provide a semiconductor device in which an avalanche photodiode and a field effect transistor are monolithically integrated and have high performance.

(Structure of the Invention) The present invention provides an avalanche photodiode including:
A high-purity InGaAs layer is used as the photosensitive layer, an InP layer is used as the multiplication layer, and InA I! is used between both layers. By using the As layer as an intermediate layer, a high-performance avalanche photodiode is realized, and in the electron amplification element, a field effect transistor using a two-dimensional electron gas formed at the InA (As layer InGaAs interface) is adopted. As a result, monolithic integration has been achieved.As for integrated elements, the avalanche photodiode and field effect transistor can be optimally designed almost independently.In other words, high-purity InGaA
s and InA I! By adopting a heterostructure of the As layer, it plays the role of a photosensitive layer and an intermediate layer in an avalanche photodiode, and is formed at the InA I As / InGaAs heterojunction interface in a field effect transistor. This allows the two-dimensional electron gas layer to function as a current channel. Here, In
GaAs serves as the active layer for the pixel element. Ano\Lancy photodiodes require low concentration and field effect transistors require high mobility, but both of these requirements can be achieved by increasing the purity. Conventionally, InGa is required for the photosensitive layer of an avalanche photodiode and the current channel layer of a field effect transistor.
Although the thickness of the As layer was different and could not be standardized as it is, this was made possible by using the above-mentioned two-dimensional electron gas layer.

(Example) Examples of the present invention will be described in detail below.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

Here, 11 is a semi-insulating InP substrate, 23 is an n-type 1nA
β・)s buff 9 layers, 12 high purity n-type InGaAs photosensitive layer, 13゜13゛ high resistance lnA I As layer, 1
4.14' is n-type 1nA 1215 layer, 15 is n-type I
nP layer, 16 is p-type InP layer, 17.19°21 is n-side ohmic electrode, 18.20 is n-side ohmic electrode, 2
2 is incident light. Here, 12.13.14°15,
On 16.20.21, the avalanche photodiode
12, 13', 14', and 17, 18, and 19 constitute field effect transistors, respectively. In the avalanche photodiode, the buffer layer 23 and the photosensitive layer 12 are the first semiconductor layer, 13 and 14 are the intermediate layer which is the second semiconductor layer, 15 is the multiplication layer, and 16 is the third semiconductor layer. , 15.16 is a pn junction.

On the other hand, in a field effect transistor, a two-dimensional electron gas layer formed at the 12.13' heterojunction interface becomes a current channel layer. Note that 17 is operated as a source electrode, 18 as a gate electrode, and 19 as a drain electrode. Also,
Although not shown in FIG. 2, wiring is provided between the electrodes 18 and 20 within the device.

Note that in this device, the buffer layer 23 is an n-type 1nA I
2As layer, but n-type InA 1. An n-type InP layer or an n-type InGaAs layer may be used instead of the As layer.

Furthermore, as shown in another embodiment in FIG. 3, the first semiconductor layer may be composed of the photosensitive layer 12 without using the haphazard layer 23. However, in this case, the electric field distribution inside the first semiconductor layer 12 is not uniform, which may cause some deterioration of the characteristics.

Next, an equivalent circuit of this device is shown in FIG. To operate this device, the terminal 31 is grounded, +4V is applied to the terminal 32, 0.5V to the knee of the terminal 33, and about 80V to the terminal 32. Therefore, a large reverse bias voltage is applied to the avalanche photodiode 35 between terminals 33 and 34. In this state, the optical signal incident on the terminal 35 is converted into an electrical signal and avalanche amplified. The potential difference generated across the load resistor connected to the avalanche photodiode is applied to the gate terminal of the field effect transistor, amplified, and taken out as a drain current.

Figure 5(a) shows the internal field strength distribution of the avalanche photodiode and field effect transistor during the above operation, and the hand structure diagram is shown in Figure 5(bl).
Shown below. In the avalanche photodiode, first, electron-hole pairs are generated inside the first semiconductor layer 12 by incident light. Due to the internal electric field, electrons are transferred to substrate 1
In one direction, the holes travel toward the p-type InP layer 16, respectively. Among these, holes cause avalanche multiplication due to an avalanche phenomenon caused by a high electric field (E, 1 is about 590 KV/cm 2 ) formed inside the n-type InP layer. In addition, avalanche
The role of the InApAs layers 13 and 14 in the photodiode is that the real name is the light-absorbing InGaAs photosensitive layer 12 and the multiplication I
The purpose is to reduce the barrier (energy difference between the valence bands at both ends) when transferring to the nP layer 15 to suppress accumulation of holes and enable high-speed operation. The output current from the avalanche photodiode is passed through a load resistor. On the other hand, as shown in the hand structure diagram [Fig. 5(C)], the field effect transistor has an electron gas layer 3 at the interface between the layer 12 and the N13.
7 is occurring. A potential change generated across the load resistor by the avalanche photodiode output current is applied to the gate electrode 18 of the field effect transistor. At this time, the potential of the electrode 18 increases compared to when no light is incident. That is, the potential on the sides of the semiconductor layers 13'' and 14'' decreases. Therefore, the depression at the interface between the layers 12 and 13'' becomes larger, and the amount of the electron gas layer 37 increases.

This increases the output current of the field effect transistor.

In the above embodiments, the second and third semiconductor layers are
The reason why the bandgap of the semiconductor layer is large is as follows.

For the avalanche photodiode, see Figure 5 (b).
The electric field strength is strong in the range of 13 to 15 at l (the slope becomes steeper when an electric field is applied). In this state, dark current other than the current excited by light tends to flow, but if the hand gap is made larger, this dark current becomes difficult to flow (
Become.

Although there is no hand gap difference between layers 13, 14 and 15 in FIG. 5 (bl), there may be a difference. Layer 12 is a photosensitive layer, and electron-hole pairs are generated by light incidence.

Regarding the field effect transistor, the carrier supply layer 14'' and the spacer layer (
Since the band gap of layer 13" (high resistance) is larger than that of channel layer 12, carriers in layer 14" are transferred to layer 12.
A channel is formed at the interface between layer 12 and layer 13''.

In the above embodiments, a field effect transistor is used as an amplification element of an avalanche photodiode, but it is also possible to apply a field effect transistor to a logic element, a memory element, etc.

(Effects of the Invention) As described above, in the present invention, the semiconductor layer 12 is a photosensitive layer of an avalanche photodiode, and also serves as an active layer of a field effect transistor. Layer 12 is I
Since it is made of nGaAs, it has sufficient sensitivity up to a wavelength of 1.65 μm. In order to obtain sufficient quantum efficiency in an avalanche photodiode, the thickness of layer 12 needs to be greater than 3 μm.

Furthermore, the gearia concentration needs to be 5×10 15 CI 11-3 or less. On the other hand, in order to increase the degree of amplification in a field effect transistor, it is desirable to increase the mobility of the layer 12. These two conditions are completely consistent. Therefore, many parts of the semiconductor layers constituting the avalanche photodiode and the field effect transistor can be shared, and it becomes easy to integrate pixel elements on the same semiconductor substrate.

[Brief explanation of drawings]

Fig. 1 is a sectional structural diagram of a conventional device, Figs. 2 and 3 are sectional views showing an embodiment of the inventive device, Fig. 4 is an equivalent circuit diagram of the inventive device, and Figs. ) (C) is an internal electric field strength distribution diagram and a band structure diagram for explaining the operation of the device of the present invention. 1... Semi-insulating InP substrate, 2... N-type InGa
AsN, 3.4-p-type InGaAs layer, 5.6-n side electrode, 7.8... n-side electrode, 11... semi-insulating I
nP substrate, 12/n type InGaAsli, 13.1
3”...High resistance InA I As layer, 14.14°・
・・n-type 1nA IAs layer, ts-n-type InP layer,
16-p-type InP layer, 17.19.21-n-side ohmic electrode, 18.20...p-side ohmic electrode,
22...Incoming light, 23...N type 1nA 124
3 layers, 31... source terminal of field effect transistor;
32...Drain terminal of field effect transistor, 33
...Gate terminal of field effect transistor, 34...
N-side terminal of avalanche photodiode, 35...
Avalanche photodiode, 36... Field effect transistor, 37... Electron gas layer.

Claims (4)

[Claims] (1) A first semiconductor layer formed on a semi-insulating semiconductor substrate, a second semiconductor layer having a larger band gap energy than the first semiconductor layer, and a second semiconductor layer having a larger band gap energy than the first semiconductor layer. an avalanche photodiode having a third semiconductor layer having a bandgap energy and a pn junction; What is claimed is: 1. A semiconductor device comprising: a field boundary transistor including a heterojunction interface formed between a semiconductor layer and a semiconductor layer; (2) The first semiconductor layer is InGaAs, the second semiconductor layer is InAlAs, and the third semiconductor layer is InP.
2. A semiconductor device according to claim 1, wherein the semiconductor device is comprised of: (3) The first semiconductor layer has a carrier concentration of 5×10^1
^5cm^-^3 or less, mobility at room temperature 10,00
N-type I with a thickness of 0 cm^2/V・s or more and a thickness of 3 microns or more
The second semiconductor layer is an nGaAs layer, and the second semiconductor layer is an n-type InAlA layer.
2. The semiconductor device according to claim 1, wherein the third semiconductor layer is an InP layer. (4) The first semiconductor layer is a buffer layer and n-type InGa.
The second semiconductor layer is made of an As layer, and the second semiconductor layer is made of a high resistance -InA layer.
2. The semiconductor device according to claim 1, wherein the third semiconductor layer is comprised of an lAs layer and an n-type InAlAs layer, and the third semiconductor layer is comprised of an n-type InP layer and a p-type InP layer.