JPS62175828A - Data processor - Google Patents

Abstract

PURPOSE:To attain execution of plural working modes by using the control memories which store plural different microprogram groups. CONSTITUTION:The address produced by an address producing circuit 13 is taken into an address register AR12. The control memories 11-1-11-n store the different microprogram groups in order to attain the desired working modes respectively and also have a common address space. When the addresses are designated to memories 11-1-11-n by the register AR12, the contents of these designated addresses are outputted at a time and supplied to a selecting circuit 14. The circuit 14 selects a microinstruction given from the memory designated by a register 15 among those memories 11-1-11-n. Thus the degree of freedom is increased for setting function of each working mode required to a data processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprogram-controlled data processing device having multiple operation modes.

[Technical Background of the Invention] A microprogram-controlled data processing device may be required to operate in several different operation modes. For example, a newly developed data processing device is required to have an operating mode that guarantees software compatibility with previous models, and an optimal operating mode is required depending on the nature of the program being processed. There is also. Furthermore, with regard to program error detection, etc., since strict implementation generally involves a decrease in execution speed, it is conceivable to set a special mode for error detection.

[Problems with Background Art] Now, in order to realize the several operation modes as described above, (1) The mode is determined by the hardware and the operation of the hardware is changed.

■ Determine the mode using the microprogram and change the processing of the microprogram.

■ Software determines the mode and dynamically replaces the microprogram.

Possible methods include:

However, in the method (2), since the microprogram processing is basically fixed, there is a problem that the degree of freedom is small. Also ■
However, there is a problem in that there is a large time overhead for determining the mode. Regarding the method (■), it is possible to dynamically replace the microprogram between the main memory or external memory and the control memory, but the control of this replacement is complicated, and the time required for the replacement is complicated. There is a problem with large overhead.

[Purpose of the Invention] This invention was made in view of the above circumstances, and its purpose is to provide an extremely large degree of freedom in setting the performance of each of a plurality of operation modes, and furthermore, the above-mentioned operation modes incur time overhead. An object of the present invention is to provide a data processing device that can be switched without any trouble.

[Summary of the Invention] In the present invention, a plurality of control memories storing various microprograms are provided. These plurality of control memories provide a common address space, and their addresses are commonly specified by the addressing means. Microinstructions output from the plurality of control memories according to the designations of the addressing means are guided to the selection circuit. This selection circuit selects the microinstruction read from the control memory designated by the selection target designation means. This results in
The microinstruction from the specified control store is executed.

In this way, in the present invention, the selection circuit switches the control memory according to the designation of the selection target designation means, thereby switching the operation mode.

[Embodiment of the Invention] FIG. 1 is a block diagram of a data processing device using a microprogram control method according to an embodiment of the present invention. In the figure, control memories 11-1 to 11-n store different microprogram groups for realizing respective required operation modes. Control memory 11-
1 to 11-n provide a common address space,
The address is commonly designated by an address register (AR) 12. The input of this address register 12 is connected to the output of an address generation circuit 13 that generates the address in the address space of the microinstruction to be executed first.

14 is a selection circuit that selects one of the microinstructions output from the control memories 11-1 to 11-n; 15 is a selection circuit 1;
This is a register for specifying a control memory to be selected (selection target control memory) from among the control memories 11-1 to 11-n in response to the control memory 4. 16 is a microinstruction register (M
IR), 17 is a decoder that decodes a predetermined field of the output of the microinstruction register 16 and outputs various control signals and the like. The output of the decoder 17 includes an n-bit control storage designation signal group 18 that designates the selected control storage in bit units, and a control signal 19 for latching the signal group 18 in the register 15.

Next, the operation of the configuration shown in FIG. 1 will be explained. The address generated by the address generation circuit 13 is taken into the address register 12, and the control memory 11-
1 to 11-n. That is, control memories 11-1 to 11
-n is addressed by address register 12. As a result, the contents (microinstructions) of the address specified by the address register 12 are simultaneously outputted from the control memories 11-1 to 11-n and guided to the selection circuit 14.

The selection circuit 14 selects a microinstruction from the control memory designated by the register 15 from among the control memories 11-1 to 11-n. The microinstruction selected by the selection circuit 14 is taken into the microinstruction register 16. The contents of a predetermined field of the microinstruction loaded into the microinstruction register 16 are guided to a decoder 17. The decoder 17 decodes the contents of a predetermined field of the microinstruction and outputs various control signals. Each section is controlled by various control signals outputted from the decoder 17, and the processing specified by the above-mentioned microinstruction is performed.

Now, the operating mode (operating state) in which processing is performed by the microprogram stored in the control memory 11-1.
is the first operation mode, and the operation mode (operation state) in which processing is performed by the microprogram stored in the control memory 11-2 is the second operation mode.
Assuming that the operation mode (operation state) in which processing is performed by the microprogram stored in 1-n is called the n-th operation mode, in the device shown in FIG. An n-th n type of operation mode can be realized. In this example, register 1
A mode that specifies switching the n-th operation mode to the n-th operation mode (i, j are any one of 1 to n, where 1≠j) in order to change the contents of 5, that is, to switch the operation mode. A switching microinstruction is provided. In this embodiment, when the microinstruction is a mode switching microinstruction, the specific field of the microinstruction is an operation mode designation field that specifies one of the n types of operation modes, that is, a control field [11-1 to 11-1]. It is used as a control storage specification field to specify one of n.

If the microinstruction taken into the microinstruction register 16 is a mode switching microinstruction, the decoder 17
The control signal 19 is activated and one of the n-bit control storage designation signal group 18 is activated.

This control storage designation signal group 18 is the result of decoding the contents of the specific field of the mode switching microinstruction. The control storage designation signal group 18 is led to the input of the register 15,
It is latched into the same register 15 in response to the active υ control signal 19.

That is, the contents of the register 15 are rewritten according to the mode switching microinstruction. The selection circuit 14 has a register 15
The selection target control memory is switched in accordance with the rewriting of the contents.

That is, the selection circuit 14 switches the selected control memory to the control memory corresponding to the only active signal among the n-bit control memory designation signal group 18 newly latched in the register 15.

The mode switching microinstruction described above is the final microinstruction of a microinstruction sequence forming a microprogram corresponding to, for example, a macroinstruction (machine language instruction) that defines normal processing and operation mode switching. Therefore, in this embodiment, mode switching is performed at the break between processing units of the microprogram. Note that instead of the macro instruction that defines normal processing and operation mode switching, it is also possible to use a macro instruction dedicated to operation mode switching. In this case, the microprogram corresponding to the macroinstruction can be composed of only one mode switching microinstruction.

As described above, according to this embodiment, a data processing device having n types of dynamically switchable operation modes is realized. Since these n types of operation modes are highly independent from each other, the degree of freedom in setting functions in each mode is extremely large.

The above description has been about specifying operation mode switching using a macro instruction, but fields for specifying the operation mode (i.e., control memories 11-1 to 11-
It is possible to control the operation mode without using a command by setting a field that specifies one of n. Regarding operation mode control by specifying this PSW,
This will be explained with reference to FIG. Note that the same parts as in FIG. 1 are given the same reference numerals.

In FIG. 2, 2) is a PSW register that holds PSW. The PSW has an operation mode designation field (sting memory designation field) 22.

The PSW is replaced every time a program is switched, that is, every time a task is switched. Now, the contents of the PSW operation mode designation field 22 held in the PSW register 2) are as follows:
It is supplied to the input of a register 23 corresponding to the register 15 in the figure, and is latched into the register 23 in response to an instruction fetch signal 24 that becomes active when a macro instruction is fetched from a main memory (not shown).

The selection circuit 14 switches the selected control memory according to the contents of the register 23. If the contents of the operation mode designation field 22 are changed due to PSW exchange, this switching will be performed at the time of the first instruction fetch after PSW exchange.

As described above, according to the configuration shown in FIG. 2, by providing the operation mode designation field 22 in the PSW, it is possible to automatically switch the operation mode (control memory) according to the contents of the field 22 without using a macro instruction. can. Note that instead of the instruction fetch signal 24, a PSW for PSW replacement is used.
It is also possible to use register 2) control signals. It is also possible to control the latch operation of the register 23 using a microinstruction for fetching instructions.

[Effects of the Invention] As detailed above, according to the present invention, each operation mode required for the device can be realized separately by microprograms stored in mutually independent control memories. The degree of freedom in setting functions becomes extremely large. Further, according to the present invention, the operating mode can be quickly switched without incurring any time overhead.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a microprogram 611111 type data processing device directly related to the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. 11-1 to 11-n... Control memory, 12... Address register (AR), 14... Selection circuit, 15.23
...Register, 1G...Micro instruction register (M
IR), 17...decoder, 2)...PSW register, 22...operation mode designation field (control storage designation field).

Claims (4)

[Claims] (1) In a microprogram control type data processing device, a plurality of control memories that provide a common address space and store various microprograms, and an addressing means that commonly specifies addresses of these plurality of control memories; a selection circuit that selects one of the microinstructions respectively output from the plurality of control memories in accordance with the designation of the address designation means; and a selection target designation means that designates a selection target control memory to the selection circuit. A data processing device, characterized in that the operation mode is switched by switching the selection target control memory. (2) The data processing according to claim 1, wherein the selection target specifying means specifies the selection target control memory according to a microinstruction in a microprogram corresponding to an operation mode switching macroinstruction. Device. (3) The data processing apparatus according to claim 1, wherein the selection target designation means includes a program status word having a selection target control storage designation field. (4) The selection target designation means switches the selection target control memory for the selection circuit according to the information in the selection target control memory designation field of the same word when fetching the first instruction after exchanging the program status word. 4. The data processing device according to claim 3, wherein the data processing device specifies the following.