JPS62175078A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To provide a VTR with a stroboscopic reproduction function by setting a period of prescribed fields, outputting an input video signal and writing in a field memory during the first field cycle and outputting a video signal repeatedly read out from the memory during remaining cycle. CONSTITUTION:When a start signal ST is supplied to a system controlling circuit 7 from a key device 8, one field share of video signals SV1 from the VTR are sequentially written in the memory 4 during the cycle of first one field, and at the same time are outputted directly to an output terminal 6 through a switching switch 2. Thereafter, the signals SV1 are read out from the memory 4 repeatedly for N-times during N field cycles. Thus video signals SV2 are outputted to the terminal 6 through the switch 2. A picture displayed by using said signals comes to be a so-called strobescopic picture i.e. still pictures sequentially updated at every (1+N)-th field.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing circuit having a field memory for processing a reproduced video signal from, for example, a video tape recorder (VTR).

[Summary of the invention]

The present invention provides a video signal processing circuit having a field memory, in which a predetermined field cycle is set, and during the first one field period, an input video signal is output and this input video signal is written to the field memory, During the remaining field periods, the video signal repeatedly read out from the field memory is output, so that, for example, a VTR can be provided with a playback function.

[Conventional technology]

Conventionally, it has been proposed that a VTR is equipped with a memory and that special playback of slow and still images is performed using the video key stored in the memory. Such a VTR has advantages such as being able to omit a special playback head and the like.

[Problem that the invention seeks to solve]

However, in order to install high IIfIi memory in a VTR, it is necessary to recognize the usage value commensurate with it.

In other words, as mentioned above, even if special reproduction such as slow and still can be performed without providing a special reproduction head, the impact is weak.

In view of this point, the present invention enables a VTR, for example, to have a playback function.

[Means for solving problems]

The present invention is a video signal processing circuit having a field memory (4). First, l + N (N is a positive integer)
The period of the field is set. Then, during the first field period of the 1+N field period, the reproduced video signal SVt from, for example, a VTR is supplied to the input terminal.
is supplied to the output terminal (6) Ic, and is also supplied to the field memory (4) and written therein, and during the following N field period, the Eirin signal written in the field memory (4) is repeatedly read out. The resulting video signal is supplied to the output terminal (6).

[Effect]

In the above configuration, the contents of the output terminal (6) are updated every 1+N fields, and during the period of 1+N fields, a video signal in which the same field signal is repeated is obtained.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG.

In the same figure, (l) is a video tape recorder (￥rR
), the video signal S output from this VTR (1)
v1 is supplied to the fixed terminal on the A side of the changeover switch (2).

Further, the video signal outputted from the VTR (1) is converted into a digital signal by the SVI inset converter (3) and then supplied to the field memory (4) as a write signal.

Further, the video signal SV2 read out from the memory (4) is converted into an analog signal by a D/A converter (5) and then supplied to the fixed terminal on the B side of the changeover switch (2). Then, from the output side of this changeover switch (2), the output terminal (6
) is derived.

In addition, (7) is a system control circuit equipped with a microcomputer, and the operation of the VTR (1) is controlled by this system control circuit (7). , this key family [ii (8)
A start signal 8T is generated by the user's operation, and this is supplied to the system control circuit (7).

In addition, in the middle device (8), the user connects the output terminal (6)
It is possible to set rNJ in the l+N field, which is the update period of the video signal obtained in
).

In addition, (9) is a counter, and the reproduction control pulse CTL (generated at a rate of one per frame by two fields PLl) from the VTR (1) is counted a.
This counter (9) is supplied as 4 pulses, and the time and
A time signal 8TM of minutes and seconds is output and supplied to the system control circuit (7).

Further, the color burst signal SC (frequency!, .) from the VTR (1) is supplied to the clock generator (11), and from this generator αQ, a clock C with a frequency of 3f0, for example, is supplied to the clock generator (11).
LK is generated and this clock CLK is ~ raw converter (3
), a memory (4), a D/A converter (5), and a timing generator αυ. Also, VT
The RF switching pulse SwP from R(1) is supplied to the system control circuit (7) and the timing generator αp. The operation of the timing generator (1υ) is controlled by the system control circuit (7), and the output of the timing generator α causes the ~0 converter (3) and the memory (
4) and the operation of the D/A converter (5) are controlled.

In this case, based on the RF switching pulse, the memory (4) is placed in a write state during the first field period of the above-mentioned 1+N field cycle, and is placed in a read state during the following N field period.

In addition, the system control circuit (7) is connected to the selector switch (2).
A switch control signal SW is supplied. The changeover switch (2) is connected to the A side during the first field period of the above-mentioned 1,000N field period, and is connected to the B side during the following N field period.

In the above configuration, when the start signal ST is supplied from the intermediate device (8) to the system control circuit (7), the VTR
Operations such as reproducing (1), reading/writing to/from memory (4), and switching of selector switch (2) are started.

1+ set by the rNJ information signal SN supplied in advance from the gear device (8) to the system control circuit (7).
The first field period of the N field period is the second field period.
As shown in FIG.
One field of the video signal SVI output from (1) is sequentially written. Also, during this first field period, the selector switch (2) is connected to the A side as shown in Figure 2C, so the output terminal (6
), the video signal SVI output from the VTR (1) is directly obtained via the changeover switch (2). Furthermore, Figure 2A
indicates the RF switching 14 rus S evaluation.

Next, during the N field period in which the period of 1+N fields continues, as shown in FIG. The written video signal for one field is read out repeatedly N times. 9. During this N field period, selector switch (2
) is connected to the B side, so the video signal SV2 read out from the memory (4) is obtained at the N field period output terminal (6) of and via the changeover switch (2).

As a result, the output terminal (6) obtains an image signal whose contents are updated every 1,000N fields, and the video signal of the same field is repeated during the 10N field period in between. The image display using this video signal becomes a so-called Stroge image in which the contents of the methyl image are sequentially updated every 1+N fields.

Therefore, according to this example, a so-called straw playback function can be added to the VTR (1).

The VTR (1) of the above embodiment is used as a master machine, and the video signal obtained at the output terminal (6) is supplied to the slave machine, and the value of "N" is set to a large value (several minutes to several tens of minutes). minutes), and at this time the time signal S from the counter (9)
Based on the TM, if the VTR (1) is placed in a fast-forward state during the N field period, it becomes possible to edit a long playback tape to shorten it. For example, it is effective for editing and dubbing scenes such as flowering scenes that last several hours, or scenes where the sun or stars move. In this case, the reading speed of the memory (4) during the N field period is the same as in the above embodiment, and the video signal of the same field is repeatedly read out a considerably smaller number of times than N.

In the above embodiment, the video signal 8V1 outputted from the VTR (1) is processed, but for example, the video signal outputted from the tuner of a television receiver, the video signal outputted from a video disc playback device, etc. , processing of other video signals can be performed in the same way.

〔Effect of the invention〕

According to the present invention described above, for example, a so-called strobe playback function can be added to a VTR, and a long playback tape can be shortened and edited.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIG. 2 is a ninth timing chart for explaining the same. (1) is a video tape recorder! , (2) is a selector switch, (4) is a field memory, (6) is an output terminal, (7
) is the system control circuit.

Claims (1)

[Claims] In a video signal processing circuit having a field memory, a period of 1+N (N is a positive integer) field is set,
Of the 1+N field cycle, during the first field period, the video signal supplied to the input terminal is supplied to the output terminal and is also supplied to the field memory for writing, and for the following N field period, the video signal is written to the field memory. A video signal processing circuit characterized in that a video signal read out is repeatedly read out, and the read video signal is supplied to the output terminal.