JPS62175010A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To constitute the circuit of a small quantity of the circuit element and to make it into the circuit suitable to a high integration by constituting an edge trigger type flip-flop circuit of an inverter circuit and plural switches MOSFET to change the connecting condition of the inverter and shift the input data. CONSTITUTION:For an edge trigger type flip-flop circuit, inverter circuits N1 and N2 to constitute the latch when a clock pulse CK is a high level and an inverter circuit N3 to constitute the latch with the inverter circuit N2 when the clock pulse CK is a low level are of the basic constitution. A P channel MOSFET 11 and an N channel MOSFET Q1' are connected to the parallel mode, and functions as a switch MOSFET to input the inverting signal by an inverter circuit N0 of input data Din to the inverter circuit N1. To the gate of the P channel MOSFET Q1, the clock pulse is supplied, to the gate of the N channel MOSFET Q1', a clock pulse, the inverse of CK is supplied respectively, and when the clock pulse CK is a low level, both MOSFET are turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an edge-triggered flip-flop circuit, for example, a logic semiconductor integrated circuit device such as a gate array constructed of CMO5 (complementary MO5). It is related to effective technology that can be used for.

[Conventional technology]

Edge-triggered flip-flop circuits have been generalized, for example, in "Digital IC Practical Circuit Manual" by Yotsube Yokoi, published by Radio Gijutsu Co., Ltd. on July 25, 1978 (pages 99 to 101). A basic circuit example is described.

FIG. 2 shows a logic circuit diagram of the Edge 1-Riga type flip-flop circuit, and this circuit system is also used in commonly used logic integrated circuits such as gate arrays. This edge-triggered flip-flop circuit has a NAND gate Gl that constitutes a first input latch for holding the positive logic (high level) of input data Din.
and G2, and a NAN that constitutes a second input latch for holding the negative logic (low level) of input data Din.
D gates G3 and G4 and NA forming the output latch
It is composed of ND gates G5 and G6. The output data Q of the output latch goes high when the output of the NAND gate G2 of the first input latch goes low, and goes low when the output of the NAND gate G3 of the second input latch goes low. level. The outputs of G2 and G3 (NAND gate of each input latch) are fixed at a high level and in a reset state while the clock pulse CK is at a low level, and when the clock pulse CK rises to a high level, the state of the input data Din is Transfer to output latch. At this time, if the input data Din is at a high level, the output of the NAND gate G1 on the cent input side of the first input latch is at a high level, so the condition of the NAND gate G2 is satisfied and its output becomes a low level. ,
The output data Q of the output latch becomes high level. on the other hand,
If the input data Din is at a low level when the clock pulse CK rises to a high level, the output of the NAND gate G4 on the set input side of the second input latch is at a high level, so the condition for the NAND gate G3 is satisfied. The output of the output latch becomes low level, and the output Q of the output latch becomes low level (output Q is high level). If the input data Din changes while the clock pulse CK is at a high level, for example, when the input data Din changes from a low level to a high level, the output of the NAND gate G3 has already become a low level. , changes in the NAND gate G4 due to the input data Din are prohibited.

Furthermore, when the input data Din changes from high level to low level while the clock pulse CK is at high level, the output of NAND gate G2 is already at low level, so the change in NAND gates G1 and G3 due to the input data Din is prohibited. Since the input latch takes in new input data after the clock pulse CK falls to low level and the outputs of NAND gates G2 and G3 return to high level, the output latch takes in new input data at the next clock. It is forced to wait until the rise of pulse CK. As a result, this flip-flop circuit functions as an edge-triggered flip-flop circuit that changes its output only in synchronization with the rising edge of the clock pulse CK.

[Problem that the invention seeks to solve]

The inventors of the present application have discovered that the edge-triggered flip-flop circuit described above has the following problems. That is, when the edge-triggered flip-flop circuit is constructed using CMO3 (complementary MOS), which is effective due to its high-speed operation and low power consumption, the basic NAND gate is as shown in the lower part of FIG. It requires twice the number of MO5FE′r as the number of input terminals, and the total number of edge-triggered flip-flop circuits is 26.
MOSFETs are required. This number is the normal R
There are considerably more circuits than 379717071 circuits, etc., and this causes a reduction in the number of circuits to be mounted in highly integrated gate array integrated circuits and the like.

SUMMARY OF THE INVENTION An object of the present invention is to provide an edge-triggered flip-flop circuit that can be constructed with a small number of circuit elements and that can be highly integrated.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
two inverter circuits that form a latch at one level of the clock signal; a third inverter circuit that shares one of the inverter circuits and forms another latch at the other level of the clock signal; An edge-triggered flip-flop circuit is constructed with a plurality of switch MOS FETs for moving input data by changing the connection form of the inverter circuit.

[For production]

According to the above-mentioned means, an edge-triggered flip-flop circuit can be configured with at least 14 MOSFETs by sharing the inverter circuit, etc., and thereby,
This makes it possible to realize an edge-triggered flip-flop circuit with a simplified circuit and suitable for high integration.

〔Example〕

FIG. 1 shows an edge trigger type flip 7 according to the present invention.
A circuit diagram is shown as an example in which the 071 circuit is configured with a CMO5 (complementary MO5). Each circuit confection in the figure is formed on a semiconductor substrate such as, but not limited to, a single crystal N-type silicon by known CMO3 integrated circuit fabrication techniques.

In the same figure, M with an arrow added to the channel part
OS FET is a P-channel type. P-channel MOS FET is a semiconductor substrate with a thin gate insulating film formed on the surface of the semiconductor substrate such as a source region, a drain region, and a region between the source region and the drain region. It is composed of a gate electrode made of polysilicon formed through the gate electrode. N channel M
The OSFET is formed in a P-type well region formed on the surface of the semiconductor substrate. This allows the semiconductor substrate to
Multiple P-channel MOS F E formed on it
constitute a common substrate gate of T. The P-type well region is
The substrate gate of the N-channel MOSFET formed thereon is configured. The semiconductor substrate, which is the substrate gate of the P-channel MOSFET, is supplied with the power supply voltage Vcc of the circuit, and the substrate gate of the N-channel MOSFET, that is, the P-type well region, is, in principle, supplied with the ground potential of the circuit.

In the figure, the edge-triggered flip-flop circuit is
Inverter circuits N1 and N2 forming a latch when clock pulse CK is at high level, and clock pulse CK
When is at a low level, the basic configuration is the inverter circuit N2 and the inverter circuit N3 forming a latch.

Although not particularly limited, P channel MOS F E
TQ L and N channel MOS FETQ 1
are connected in parallel and act as switch MOSFETs for inputting an inverted signal of the input data Din by the inverter circuit NO to the inverter circuit N1. A clock pulse Ck is applied to the gate of the P-channel MOSFET QI, and a clock pulse C, which is an inverted version of the clock pulse CK, is applied to the gate of the N-channel MOSFET QI'.
When the clock pulse CK is at a low level, both MOSFETs are turned on. Similarly,
P-channel MOSFETQ2 and N-channel MOSF
ETQ 2°, P channel MOS F ETQ 3 and N
Channel/L/MOS 1? E T Q 3 ' is turned on when the clock pulse GK is at a high level, and makes the inverter circuits N1 and N2 into a latch mode.

Also, P-channel MOSFET Q4 and N-channel MOSFET
OS FET Q4' is turned on when clock pulse GK is at low level, and inverter circuit N2
and N3 are in latch form. The output of the inverter circuit N2 is outputted as an output Q1 of this edge-triggered flip-flop circuit, and the output of the inverter circuit N3 is outputted as an output Q to the outside. Here, as shown in the lower part of FIG.
3), and in particular, the inverter circuit N1 is designed to have a larger driving force than the inverter circuit N2 by, for example, increasing the conductance of both MOSFETs. A non-inverted clock pulse Ck formed based on the clock pulse GK and an inverted clock pulse Ck generated by the inverter circuit N4 are supplied to the gate of each switch MOSFET.

Next, the operation of this edge-triggered flip-flop circuit will be explained. When the clock pulse CK is at a low level, the switches MOSFETs QI and Qlo are turned on, so the inverted signal of the input data Din by the inverter circuit NO is sent to the inverter circuit N1, and the MOSFETs QI and Qlo are turned on.
Charge the gate capacitance of ET. At this time, inverter circuits N2 and N3 are connected to switch MOSFETs Q4 and Q
4° is in the on state, it is in a latch form and holds the state of the input data Din at the high level immediately before the clock pulse CK. Switch MOS F E
TQ 2 and Q2° and switch MOSFETs Q3 and Q3' are in the off state, and the input circuit and rear latch are in the disconnected state.

On the other hand, when clock pulse GK rises to high level, switch MOSFETs QI and Qlo and switch M
OSFETs Q4 and Q4' are turned off, and at the same time, switch MOSFETs Q2 and Q2' and switch MOSFETs Q3 and Q3' are turned on. As a result, the inverter circuits N1 and N2 become latched, and the inverter circuit N3 becomes the inverter circuit f.
Simply connected to 8N2. Here, inverter circuit N1
is the input data D just before the clock pulse GK rises.
An attempt is made to drive the inverter circuit N2 based on the gate voltage charged by in, and the inverter circuit N2
attempts to drive the inverter circuit N1 based on the gate voltage charged by the state of the input data Din at the rising edge of the previous clock pulse GK, which has been held until then. As described above, since the inverter circuit N1 is designed to have a larger driving force than the inverter circuit mN2, the latches of the inverter circuits N1 and N2 are set depending on the state of the new input data Din.

As a result, the input data Din is transferred to the previous stage latch (inverter circuit N) in synchronization with the rising edge of the clock pulse CK.
l and N2), and thereafter the switch MOSF
Since ETQI and Ql' are in the off state, there is no effect even if the input data Din changes while the clock pulse GK is at a high level.

Next, when the clock pulse CK becomes low level again,
Switch MOSFET Q2 and Q2゜ and switch MO
Since SFETs Q3 and Q3° are turned off and switch MOSFETs Q4 and Q4' are simultaneously turned off, inverter circuits N2 and N3 take over the state of the new input data Din and become latched. As a result, the data held in the previous-stage latch is transferred to and held in the subsequent-stage latch (inverter circuits N2 and N3) in synchronization with the falling edge of clock pulse GK. Further, after the data is held in the previous stage latch, new input data Din is output as output Q. Due to the above,
This circuit will be used as an edge-triggered flip-flow 71 circuit.

The following effects can be obtained from the operation of the above embodiment.

That is, (1) two inverter circuits that form a latch when the clock signal is at a high level; a third inverter circuit that shares one of the inverter circuits and forms another latch when the clock signal is at a low level; By changing the connection form of the inverter circuit and using multiple switch MOSFETs to move input data, a minimum of 14 MOSFETs can be used, excluding the input inverter circuit and the inverter circuit for clock inversion. The advantage is that an edge-triggered flip-flop circuit can be constructed.

(2) By simplifying the configuration of the basic edge trigger type flip-flow 71 circuit according to the above (1),
The effect is that it is possible to realize a logic integrated circuit such as a gate array with a further increased number of circuits mounted without increasing the chip size.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in Fig. 1, inverter circuit NO and
E 'r' Q l and Qlo, inverter circuit N
1 and switch MOS FET Q 2 and Q2
', also inverter circuit N3 and switch MOSFETQ
4 and Q4' may be combined to form a clocked inverter circuit which supplies the operating voltage of the inverter circuit by means of a switch MOSFET. In addition, each switch MOSFET is a P-channel MOSFET.
Either T or N channel MOS FET may be used, and each inverter circuit may be 0MO5.
(complementary type MO8). Furthermore, the inverter circuit NO may be omitted by interchanging the outputs Q and 100, and the inverter circuit N4 for clock inversion may also be omitted if the clock generation circuit has an inverted signal.

The above explanation will mainly focus on the field of application made by the present inventor, 0MO3 (complementary M
Although we have described the case where it is applicable to an edge-trigger type flip-flop circuit housed in a logic integrated circuit such as a gate array constructed by O3), the present invention is not limited thereto. 11 types of flip-flops etc.
Can be used for M. The present invention can be applied at least to conditions in which a logic integrated circuit constituted by MOSFETs is used.

[Efficacy of invention]

A brief explanation of the gjj results obtained by typical inventions disclosed in this application is as follows. That is, by configuring an engine-trigger type Flimb-Fronb rfA path with a small number of circuit elements, it is possible to realize a logic integrated circuit such as a gate array f with an increased number of mounted circuits without increasing the chip size.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the edge-triggered flip-flop circuit 71 according to the present invention, and FIG. 2 is a circuit diagram showing a conventional edge-triggered flip-flop circuit. ~Q4...P channel MOS FET (switch MOSFET) Q1°~Q4°...N channel MOSFET (switch MOSFET) 01~G6...NAND gate Din......Manual data Q, Q...Output data CK...Clock pulse "tFIJP!-t:"゛"-■.'-,- Figure 1 Figure 2

Claims (1)

[Claims] 1. At one level of the clock signal, the first and second inverter circuits forming a latch by the second and third switch MOSFETs, and at the other level of the clock signal, the input A first switch MOSFET that inputs a signal to the first inverter circuit, and a fourth switch MOS
A flip-flop circuit comprising the second inverter circuit and a third inverter circuit forming a latch using FETs. 2. The flip-flop circuit according to claim 1, wherein each circuit element of the flip-flop circuit is constituted by a complementary MOSFET.