JPS62174852A - Receiving control method in data transmission system - Google Patents
Receiving control method in data transmission systemInfo
- Publication number
- JPS62174852A JPS62174852A JP61017135A JP1713586A JPS62174852A JP S62174852 A JPS62174852 A JP S62174852A JP 61017135 A JP61017135 A JP 61017135A JP 1713586 A JP1713586 A JP 1713586A JP S62174852 A JPS62174852 A JP S62174852A
- Authority
- JP
- Japan
- Prior art keywords
- data
- transmission
- reception
- buffer memory
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 92
- 238000000034 method Methods 0.000 title claims description 7
- 230000007175 bidirectional communication Effects 0.000 claims description 3
- 230000006870 function Effects 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims 5
- 230000006854 communication Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、データ伝送システムにおける受信制御方式に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reception control method in a data transmission system.
従来、データ伝送システムにおける受信制御方式は、ノ
ードに設けられている受信バッファメモリに、データ伝
送路からの受信データの蓄積が終了すると、受信完了と
いう割込みを発生して、受信制御プログラムに通知し、
受信制御プログラムは、受信完了の割込みが発生したこ
とを検出すると、受信バッファメモリ内に蓄積されてい
る受信データに含まれている受信データ長の情報を読み
取り、受信データ長を解釈して、このデータ長だけ受信
バックアメモリ内にある受信データを主メモリにＤＭＡ
転送するための受信ＤＭＡコマンドを起動していた。Conventionally, in a reception control method in a data transmission system, when the reception buffer memory provided in a node finishes storing reception data from a data transmission path, an interrupt indicating reception completion is generated to notify the reception control program. ,
When the reception control program detects that a reception completion interrupt has occurred, it reads the reception data length information included in the reception data stored in the reception buffer memory, interprets the reception data length, and executes this reception data length. DMA the received data in the receive backup memory to the main memory by the data length
A receive DMA command was activated for transfer.
上述したデータ伝送システムにおける受信制御方式では
、伝送されるデータ長が可変であるため受信制御プログ
ラムは、データ伝送路から受信したデータを主メモリに
格納するためには、受信データを受信バッファメモリに
蓄積後発生する受信完了の割込みを処理し、受信バッフ
ァメモリ内の受信データ長を読んで、受信データのデー
タ長を知り、このデータ長だけ、受信バッファメモリ内
の受信データを主メモリにＤＭＡ転送するための受信Ｄ
ＭＡコマンドを起動するので、受信制御に要する処理時
間が増加するという問題点がある。In the reception control method in the data transmission system described above, since the length of the transmitted data is variable, the reception control program must store the received data in the reception buffer memory in order to store the data received from the data transmission path in the main memory. Processes the reception completion interrupt that occurs after accumulation, reads the reception data length in the reception buffer memory, learns the data length of the reception data, and DMA transfers the reception data in the reception buffer memory to the main memory by this data length. Receive D to
Since the MA command is activated, there is a problem in that the processing time required for reception control increases.
本発明は、データ伝送システムの各ノードの受信制御部
において、データ伝送路から受信バックアメモリへ受信
データの蓄積が終了すると、受信制御プログラムに対し
ては、受信完了の割込みを発生せずに、受信データ長の
カウントと保持を行う受信データカウントレジスタと、
受信制御プログラムが、受信したデータ長だけ受信ＤＭ
Ａコマンドを起動したのと同等な受信ＤＭＡ起動信号を
受信ＤＭＡ制御部に出力する回路を設けることにより、
上記の受信制御に要する処理時間が増加するという欠点
を解決し、受信制御プログラムは、データ伝送路からデ
ータを受信する前に、あらかじめ受信ＤＭＡコマンドを
起動して受信ＤＭＡの設定を行っておけば、データ伝送
路から受信したデータ長だけの受信データを受信バッフ
ァメモリに蓄積してこれを直ちに主メモリに格納するこ
とができる受信制御方式を提供する。According to the present invention, when the reception control unit of each node of the data transmission system finishes storing the reception data from the data transmission path to the reception backup memory, the reception control program does not generate a reception completion interrupt. a receive data count register that counts and holds the receive data length;
The reception control program receives DM only by the length of the received data.
By providing a circuit that outputs a reception DMA activation signal equivalent to that which activated the A command to the reception DMA control section,
To solve the drawback that the processing time required for reception control increases as described above, the reception control program can activate the reception DMA command in advance and configure the reception DMA before receiving data from the data transmission path. To provide a reception control method that can accumulate reception data of the data length received from a data transmission path in a reception buffer memory and immediately store it in a main memory.
次に本発明の実施例について図面を用いて説明する。第
１図はデータの送信機能と受信機能を有するノード１０
とノード１１が双方向性通信を行うために、ノード１０
がノードＩＩＫデータを送信する伝送路１２と、ノード
１０がノード１１からデータを受信する伝送路１３から
成るデータ伝送システムの構成図である。第２図は、各
ノードの送受信制御部の構成図である。各ノードは、受
信データのノードアドレス判定と伝送誤シ検出を行う受
信伝送路アクセス制御部２２、データ伝送路から受信し
たデータを蓄積するための受信バックアメモリ２３、デ
ータ伝送路から受信したデータのデータ長をカウントし
て、このデータ長を保持するための受信データカウント
レジスタ２４、受信バッファメモリ２３に蓄積された受
信データを主メモリ２ＢへＤＭＡ転送するための受信Ｄ
ＭＡ回路２５、受信バッファメモリ２３に受信データの
書込がが終了したことを検出後、受信バッファメモリ２
３内に蓄積されている受信データを受信データカウント
レジスタ２４に保持されているデータ長だけ主メモＩＪ
２ ＢへＤＭＡ転送する制御を行う受信バッファ制御
部２６、送信伝送路にデータを送信するための送信権を
獲得後、送信データに伝送誤り検出符号の付加を行い、
送信バッファメモリから送信データを読み出してデータ
伝送路に送信するための送信伝送路アクセス制御部２７
、送信データを蓄積するための送信バッファメモリ２８
、主メモリ内にある送信データを送信バッファメモリ２
８にＤＭＡ転送するための送信ＤＭＡ回路２９、主メモ
１Ｊ２Ｂから送信バッファメモリ２８に送信データの書
込みが終了したことを検出後、送信伝送路アクセス制御
部２７に対して送信要求起動を行う送信バッファメモリ
制御部２人を備えている。Next, embodiments of the present invention will be described using the drawings. Figure 1 shows a node 10 that has data transmission and reception functions.
In order for node 10 and node 11 to perform bidirectional communication, node 10
1 is a configuration diagram of a data transmission system consisting of a transmission path 12 through which node IIK transmits data, and a transmission path 13 through which node 10 receives data from node 11. FIG. FIG. 2 is a configuration diagram of the transmission/reception control section of each node. Each node includes a reception transmission path access control unit 22 that determines the node address of received data and detects transmission errors, a reception backup memory 23 that stores data received from the data transmission path, and a reception backup memory 23 that stores data received from the data transmission path. A reception data count register 24 for counting and holding the data length, and a reception D for DMA transfer of the reception data accumulated in the reception buffer memory 23 to the main memory 2B.
After the MA circuit 25 detects that writing of received data to the reception buffer memory 23 is completed, the reception buffer memory 2
3 is stored in the main memory IJ by the data length held in the received data count register 24.
After acquiring the transmission right to transmit data to the transmission transmission path, the reception buffer control unit 26 that controls DMA transfer to 2B adds a transmission error detection code to the transmission data,
Transmission transmission path access control unit 27 for reading transmission data from the transmission buffer memory and transmitting it to the data transmission path
, a transmission buffer memory 28 for storing transmission data
, the transmission data in the main memory is transferred to the transmission buffer memory 2.
A transmission DMA circuit 29 for DMA transfer to the transmission line access control unit 27 after detecting that writing of transmission data from the main memory 1J2B to the transmission buffer memory 28 has been completed, and a transmission buffer that initiates a transmission request to the transmission line access control unit 27. Equipped with two memory controllers.
相手ノードから受信送路２０を経て受信したデータは、
受信伝送路アクセス制御部２２においてノードアドレス
及び伝送誤りのチェックが行われ、伝送誤りがない場合
は、受信データを受信バッファメモリ２３に書込んで蓄
積するとともに、受信データのデータ長をカウントして
、受信データの受信バックアメモリ２３への書込みが終
了した時点で、受信データのデータ長を受信データカウ
ントレジスタ２４に保持する。同時に、受信バッファ制
御部２６は、受信データの受信バックアメモリ２３への
書込みが終了したことを検出後、受信ＤＭＡ回路２５に
対して、受信ＤＭＡ起動を行い、受信データカウントレ
ジスタ２４に保持されているデータ長だけ受信バッファ
メモリ２３内の受信データを主メモリ２ＢへＤＭＡ転送
し、この受信ＤＭＡ転送が終了すると受信制御プログラ
ムに対して受信終了の要因で割込みを発生し、受信動作
を完了する。The data received from the other node via the reception path 20 is
The reception transmission path access control unit 22 checks the node address and transmission error, and if there is no transmission error, writes the reception data to the reception buffer memory 23 and stores it, and counts the data length of the reception data. , the data length of the received data is held in the received data count register 24 when writing of the received data to the reception backup memory 23 is completed. At the same time, after detecting that the writing of the received data to the reception backup memory 23 has been completed, the reception buffer control unit 26 activates the reception DMA in the reception DMA circuit 25 and stores the data held in the reception data count register 24. The reception data in the reception buffer memory 23 is transferred to the main memory 2B by DMA for the data length, and when this reception DMA transfer is completed, an interrupt is generated to the reception control program due to the reception end factor, and the reception operation is completed.
以上説明したように、本発明はデータ伝送システムの各
ノードの受信バッファ制御部に受信データのデータ長を
カウントする回路と、データの受信が終了した時点で、
受信データのデータ長カウント回路により計数したデー
タ長を保持する受信データカウントレジスタを設けるこ
とにより、データ伝送路から受信したデータのデータ長
が受信データ毎に可変長になった場合でも、受信制御プ
ログラムは、データを受信する前にあらかじめ受信ＤＭ
Ａの起動を設定しておけば、データを受信する毎に受信
バッファメモリ内の受信データに含まれている受信デー
タ長を読み取らなくても、受信バッファ制御部が受信デ
ータカウントレジスタに保持した受信データ長だけ受信
ＤＭＡ回路に対して受信バッファメモリ内のデータを主
メモリへＤＭＡ転送の起動を行うので、データ伝送路に
伝送されるデータには、データ長を表わす情報は不要で
あり、また受信制御プログラムには、受信データ毎にデ
ータ長を読み取り、受信ＤＭＡの設定を行うことが不要
なため、受信制御プログラムの受信制御に要する処理時
間が短縮できる効果がある。As explained above, the present invention includes a circuit that counts the data length of received data in the reception buffer control section of each node of a data transmission system, and a circuit that counts the data length of received data, and
By providing a receive data count register that holds the data length counted by the data length count circuit of the receive data, even if the data length of the data received from the data transmission path becomes variable for each received data, the receive control program is to send the received DM in advance before receiving the data.
By setting the activation of A, the reception buffer control unit does not have to read the reception data length included in the reception data in the reception buffer memory every time data is received. Since the reception DMA circuit starts DMA transfer of the data in the reception buffer memory to the main memory by the data length, the data transmitted to the data transmission path does not require information indicating the data length, and the reception Since the control program does not need to read the data length of each received data and set the reception DMA, it has the effect of shortening the processing time required for reception control by the reception control program.
第１図は、２つのノードが双方向性通信を行うためにデ
ータ伝送路で接続されたデータ伝送システムの構成図、
第２図は本発明の一実施例を示す構成図である。
２０・・・・・・受信系伝送路、２１・・・・・・送信
系伝送路、２２・・・・・・受信伝送路アクセス制御部
、２３・・・・・・受信バッファメモリ、２４・・・・
・・受信データカウントレジスタ、２５・・・・・・受
信ＤＭＡ回路、２６・・・・・・受信バッファ制御部、
２７・・・・・・送信伝送路アクセス制御部、２８・・
・・・・送信バックアメモリ、２９−・・・・・送信Ｄ
ＭＡ回路、２人・・・・・・送信バッファ制御部、／−
一＼
２Ｂ・・・・・・主メモリ、２Ｃ・・・・・・主制御部
。、−代理人 弁理士 内 原 普コノ弗 １
回FIG. 1 is a configuration diagram of a data transmission system in which two nodes are connected via a data transmission path for bidirectional communication;
FIG. 2 is a configuration diagram showing an embodiment of the present invention. 20... Receive system transmission line, 21... Transmit system transmission line, 22... Receive transmission line access control unit, 23... Receive buffer memory, 24・・・・・・
... Reception data count register, 25 ... Reception DMA circuit, 26 ... Reception buffer control unit,
27... Transmission transmission path access control unit, 28...
...Transmission backup memory, 29-...Transmission D
MA circuit, 2 people...Transmission buffer control section, /-
1\2B...Main memory, 2C...Main control unit. , - Agent Patent Attorney Fukono Uchihara 1
times
Claims (1)
方向性通信を行うために送信伝送系と受信伝送系から成
るデータ伝送路により接続して対向通信を行うデータ伝
送システムにおいて、各ノードに受信データのノードア
ドレス判定と伝送誤り検出を行う手段と、受信データを
蓄積するための受信バッファメモリと、受信データのデ
ータ長をカウントする手段と、前記受信データカウント
手段により計数した受信データ長を保持するための受信
データカウントレジスタと、受信バッファメモリ内にあ
る受信データを主メモリにＤＭＡ転送する手段と、デー
タ伝送路から受信バッファメモリに受信データの蓄積が
終了したことにより前記受信データを受信バッファメモ
リから主メモリにＤＭＡ転送するための受信ＤＭＡ起動
を行う手段と、送信データを蓄積するための送信バッフ
ァメモリと、主メモリ内にある送信データを送信バッフ
ァメモリにＤＭＡ転送する手段と、主メモリから送信バ
ッファメモリへの送信データのＤＭＡ転送が終了したこ
とにより、前記送信データを送信バッファメモリからデ
ータ伝送路に送信要求起動を行う手段と、送信データに
送信先ノードアドレスと伝送誤り検出符号の付加を行う
手段を設け、前記ノードがデータ伝送路からデータを受
信した場合はあらかじめ受信ＤＭＡコマンドにより設定
しておいた受信バッファメモリから主メモリへのＤＭＡ
転送が、受信バッファメモリに受信データの蓄積と受信
データカウントレジスタに受信データ長の保持が終了し
たことにより起動され、受信データのデータ長が受信デ
ータ毎に可変長になった場合でも、前記受信データカウ
ントレジスタに保持された受信データ長だけ、受信バッ
ファメモリ内のデータを主メモリへＤＭＡ転送すること
を特徴とするデータ伝送システムにおける受信制御方式
。In a data transmission system in which two nodes having a data transmission function and a data reception function are connected by a data transmission path consisting of a transmission transmission system and a reception transmission system for bidirectional communication to perform two-way communication, each node receives data. means for determining the node address of data and detecting transmission errors; a reception buffer memory for accumulating received data; means for counting the data length of the received data; and holding the received data length counted by the received data counting means. a reception data count register for transferring the reception data from the data transmission path to the reception buffer memory; and a means for DMA transferring the reception data in the reception buffer memory to the main memory; means for activating reception DMA for DMA transfer from memory to main memory; transmission buffer memory for accumulating transmission data; means for DMA transfer of transmission data in main memory to transmission buffer memory; and main memory. When the DMA transfer of the transmission data from the transmission buffer memory to the transmission buffer memory is completed, a means for activating a transmission request for the transmission data from the transmission buffer memory to the data transmission path, and a means for activating a transmission request for the transmission data from the transmission buffer memory to the transmission buffer memory, and a means for activating a transmission request for the transmission data from the transmission buffer memory to the transmission buffer memory, and a means for activating a transmission request for the transmission data from the transmission buffer memory to the transmission buffer memory, A means for adding data is provided, and when the node receives data from the data transmission path, it transfers DMA from the receive buffer memory set in advance by a receive DMA command to the main memory.
Even if the transfer is started when the received data is stored in the receive buffer memory and the received data length is stored in the received data count register, and the data length of the received data becomes variable for each received data, the received A reception control method in a data transmission system, characterized in that data in a reception buffer memory is transferred to main memory by DMA for the length of reception data held in a data count register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61017135A JPS62174852A (en) | 1986-01-28 | 1986-01-28 | Receiving control method in data transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61017135A JPS62174852A (en) | 1986-01-28 | 1986-01-28 | Receiving control method in data transmission system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62174852A true JPS62174852A (en) | 1987-07-31 |
| JPH0476148B2 JPH0476148B2 (en) | 1992-12-02 |
Family
ID=11935579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61017135A Granted JPS62174852A (en) | 1986-01-28 | 1986-01-28 | Receiving control method in data transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62174852A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01120656A (en) * | 1987-11-04 | 1989-05-12 | Nec Corp | Transmission/reception data processor |
| JPH04233055A (en) * | 1990-06-29 | 1992-08-21 | Digital Equip Corp <Dec> | Server architecture for terminal apparatus |
-
1986
- 1986-01-28 JP JP61017135A patent/JPS62174852A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01120656A (en) * | 1987-11-04 | 1989-05-12 | Nec Corp | Transmission/reception data processor |
| JPH0544695B2 (en) * | 1987-11-04 | 1993-07-07 | Nippon Electric Co | |
| JPH04233055A (en) * | 1990-06-29 | 1992-08-21 | Digital Equip Corp <Dec> | Server architecture for terminal apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0476148B2 (en) | 1992-12-02 |
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