JPH06175960A - Address confirmation system - Google Patents

Abstract

PURPOSE:To improve the reliability of data transfer executed in an information processing system while using a conventional device which handles addresses having no error detecting and correcting functions with respect to the address confirmation system in the information processing system where a channel controller and plural input/output controllers are connected by an input/output bus. CONSTITUTION:A channel controller 300 is provided with an address return means 391 which holds an address (a) sent from each input/output controller 400 to an input/output bus 500 and returns it to the input/output bus 500, and each input/ output device 400 is provided with a transmission address holding means 491, which holds the address to be sent to the input/output bus 500 at the time of execution of data transfer, and a collating means 492 which collates the transmission address and the return address and confirms the normalcy of the address transferred through the input/output bus 500 based on the collation result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address confirmation system in an information processing system in which a channel controller and a plurality of input / output controllers are connected by an input / output bus.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an example of an information processing system to which the present invention is applied, FIG. 8 is a diagram showing an example of a conventional input / output control device, and FIG. 9 is a conventional channel control device. FIG. 10 is a diagram showing an example, and FIG. 10 is a diagram showing an example of a conventional data transfer operation.

The information processing system shown in FIG. 7 has a central controller (CC) (1), a main memory (MM) (2),
A channel controller (CHC) (3), a plurality of input / output controllers (IOC) (4), and an input / output bus (5) are provided, and each input / output controller (IOC) (4) is central. Under the control of the controller (CC) (1), the main memory (M
M) (2) and a channel controller (CHC)
Transfer the data via (3) and the input / output bus (5).

A parity bit is added to the data transferred by each input / output control unit (IOC) (4) via the input / output bus (5) at the time of data transfer. It is assumed that no parity bit is added to the address transmitted by the device (IOC) (4) to the input / output bus (5).

Input / output control unit (IOC) shown in FIG.
(4) is an external storage unit (FM) configured from a semiconductor storage element and storing a predetermined number of words of data with parity bits.
U) (401), buffer memory (BM) (402) for temporarily accumulating data to be written to or read from the external storage unit (FMU) (401), error in generating parity bit to be added to data and performing parity check on the data Detection and correction unit (ECC) (403), central control unit (CC)
Input / output control device (IOC) based on the command from (1)
A DMA controller (DMC) (406) for controlling data transfer between the (4) and the main memory (MM) (2) in a direct memory access (hereinafter referred to as DMA) format, and a self input / output controller (IOC) ) (4) Input / output address holding unit (IOA) holding the input / output address assigned to (4) (41
1), address bus (AB) (5) in input / output bus (5)
1) The address transferred via 1) is collated with the input / output address held in the input / output address holding unit (IOA) (411), and if they match, the self input / output control unit (IOC) Program mode controller (PM) in (4)
C) Matching unit (MCH) (41) that activates (413)
2), the input / output controller (IO) specified by the address transferred via the address bus (AB) (51)
C) Decoder (DCR) (4) that activates each unit in (4)
14), a device status register (DSR), a word count register (WCR), a memory address register (MAR), a file address for accumulating various data or the like necessary for the DMA control unit (DMC) (406) to control data transfer Register group (REG) (41) including register (FAR), command register (CMR), etc.
5), a processor (MPU) (421) for controlling each unit in the input / output control unit (IOC) (4), an internal bus (42)
2), decoder (DCR) (423), read only memory (ROM) (424), write / read memory (RAM) (4
25), interrupt control unit (IRC) (426), clock generation unit (CKG) (431), external storage unit (FMU) (4)
01) is composed of a D-RAM, a refresh unit (REF) (441) and various gates (404), (405), (407), (416),
(417), (418), (427), (442),
It is composed of (443) and (444).

Further, the channel controller (C
HC) (3) is based on a command from the central control unit (CC) (1), and the input / output control unit (IOC) (4) is connected to the main storage unit (MM) (2) by an input / output bus ( 5) A DMA for controlling the data transfer executed via the DMA format
An interface control unit (32) for exchanging various signals between the control unit (31), the central control unit (CC) (1) and the main memory unit (MM) (2), and various gates (3).
3), (34) and (35).

The central controller (CC) (1) passes the channel controller (CHC) (3) to the target input / output controller (IOC) (4) to the main memory (MM) (2).
When activating the data transfer operation to the target input / output control device (IOC) (4), the input / output address of the target input / output control device (IOC) (4) is transferred via the address bus (AB) (51). IOC) (4) Program mode controller (P
MC) (413) is started, and register group (REG) (4
Refer to the contents of the device status register (DSR) in 15) to confirm whether data transfer can be executed. If possible, store the number of words in the word count register (WCR) and main memory in the memory address register (MAR). The transfer target address (a) on the device (MM) (2) is stored in the file address register (FAR) in the external storage unit (FMU).
The transfer target address on (401) is stored in the command register (CMR), such as instructions for writing / reading and executing transfer.

The processor (MPU) (421) analyzes the contents stored in the command register (CMR), and DMA
DM specified by activating the control unit (DMC) (406)
The operation A is started.

Conventional data transfer operation (DMA operation)
Is executed in the process as shown in FIG. First, the DMA controller (DM) in the input / output controller (IOC) (4)
C) (406) requests the use of the I / O bus (5), the control bus (CB) (53) in the I / O bus (5)
The bus request signal (c ₁ ) is transferred to the channel controller (CHC) (3) via the.

D in the channel controller (CHC) (3)
When the MA control unit (31) receives the bus request signal (c ₁ ) transferred via the control bus (CB) (53) and determines that the input / output bus (5) is available, the control bus (31) C
B) Request source input / output control unit (IO) via (53)
C) Transfer the bus request acceptance signal (c ₂ ) to (4).

DM in the input / output control unit (IOC) (4)
The A control unit (DMC) (406) has a control bus (CB)
When the bus request acceptance signal (c ₂ ) transferred via (53) is received, the bus reservation signal (c ₃ ) is sent to the control bus (CB) (53), and the input / output bus (5) transmits data. Occupancy of the I / O bus (5) as soon as transfer is possible is indicated to the channel controller (CHC) (3) and the other I / O controller (IOC) (4).

When the input / output bus (5) becomes ready for data transfer, the DMA controller (DMC) (406).
The bus occupation signal (c ₄ ) on the control bus (CB) (53)
And set the gate (418) to the conductive state,
The address (a) to which the parity bit accumulated in the memory address register (MAR) is not added is sent to the address bus (AB) (51), and the gate (4)
42) to the conductive state, and the file address register (F
The address stored in AR is stored in the external storage unit (FM).
U) (401) and the external storage unit (FMU) (40
After the data (d) is extracted from 1) and once stored in the buffer memory (BM) (402), the gate (404) is set to the conductive state and sent to the data bus (DB) (52). The control bus (CB) (53) indicates that the address (a) sent to the address bus (AB) (51) and the data (d) sent to the data bus (DB) (52) are valid. A valid display signal (c ₅ ) is sent.

D in the channel controller (CHC) (3)
When the MA control unit (31) receives the valid display signal (c ₅ ) transferred via the control bus (CB) (53),
The gates (33) and (35) are set to the conductive state, and the address bus (AB) (51) and the data bus (DB) are set.
The address (a) and the data (d) transferred via (52) are transferred to the main memory (MM) (2) via the interface controller (32), and the main memory (M) is transferred.
M) The transfer data (d) is stored in the predetermined address (a) of (2), and the target input / output control device (IOC)
A reception confirmation signal (c ₆ ) indicating that the address (a) and the data (d) sent from (4) are received,
Transfer to the transfer target input / output controller (IOC) (4) via the control bus (CB) (53).

DM in the input / output control unit (IOC) (4)
The A control unit (DMC) (406) has a control bus (CB)
When the reception confirmation signal (c ₆ ) transferred via (53) is received, the effective display signal (c ₅ ) being sent to the control bus (CB) (53) is stopped, and the channel controller (C) is stopped.
The DMA controller (31) in the (HC) (3) controls the control bus (CB) (53) based on the stop of the valid display signal (c ₅ ).
When the reception confirmation signal (c ₆ ) being sent to the device is stopped, the DMA controller (DMC) in the input / output controller (IOC) (4)
(406) is an address bus (AB) (51), a data bus (DB) (52) and a control bus (CB) (53)
The address (a), the data (d) and the bus occupation signal (c ₄ ) being sent to the device are stopped to stop the transfer of the data (d) for one word, and then the word count register (WCR)
Subtract one word from the number of words (w) stored in (w = w-
1), and the address (a) stored in the memory address register (MAR) is advanced one step (a = a + 1), and the next word is transferred.

[0015]

As is apparent from the above description, in the conventional information processing system, the input / output control unit (IOC) (4) executes data transfer via the input / output bus (5). In this case, the normality of the transfer can be confirmed by adding the parity bit to the data (d), but the normality of the transfer cannot be confirmed because the parity bit is not added to the address (a). When the disturbance is generated on the input / output bus (5) during the data transfer, the wrong address (a) may be transferred, and the reliability of the information processing system is deteriorated.

In order to solve such a problem, if a parity bit is added to the address (a), the existing channel controller (CHC) (3), input / output controller (IOC) (4) and input channel controller (IOC) (4). The output bus (5) becomes unusable, impairing the economical efficiency of the information processing system, and cannot be an appropriate solution.

The present invention uses the existing channel controller, input / output controller, and input / output bus that handle addresses that do not have an error detection / correction function, and the reliability of data transfer executed by the information processing system. The purpose is to improve.

[0018]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, 100 is a control device and 200
Is a storage device, 300 is a channel control device, 400 is a plurality of input / output control devices, and 500 is a channel control device (30
0) is connected to a plurality of input / output control devices (400) and constitutes an information processing system which is a target of the present invention.

Reference numeral 391 is an address returning means provided in the channel controller (300) according to the present invention. 49
Reference numeral 1 is a transmission address holding means provided in the input / output control device (400) according to the present invention.

Reference numeral 492 is a collating means provided in the input / output control device (400) according to the present invention.

[0021]

The address return means (391) transfers data from the input / output control device (400) that executes data transfer to the input / output bus (5).
The address (a) sent to 00) is held and returned to the input / output bus (500).

The transmission address holding means (491) holds the address (a) to be sent to the input / output bus (500) when executing data transfer. The matching means (492) matches the address (a) held by the transmission address holding means (491) with the address (a) returned from the channel control device (300) to the input / output bus (500), Based on the collation result, the normality of the address (a) transferred via the input / output bus (500) is confirmed.

It is considered that the address returning means (391) returns the held address (a) after the data transfer by the input / output control device (400) is completed. The I / O controller (400) also sends the address (a) sent to the I / O bus (500) to the channel controller (300).
After confirming that it has received, it is considered to stop sending to the I / O bus (500).

Further, it is considered that the collating means (492) tries again the data transfer which cannot be confirmed as normal by the collation result. Therefore, the normality of the address transferred via the I / O bus can be confirmed without adding an error detection / correction function to the address, and the reliability of the data transfer in the information processing system can be controlled by the existing channel control. It is greatly improved by using the device, I / O controller and I / O bus.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing an input / output control device according to one embodiment of the present invention, FIG. 3 is a diagram showing an address confirmation function part in FIG. 2, and FIG. 4 is a channel control device according to one embodiment of the present invention. 5 is a diagram showing an example of the address buffer in FIG. 4, and FIG. 6 is a diagram showing a data transfer operation according to an embodiment of the present invention. The same reference numerals denote the same objects throughout the drawings. The target information processing system is as shown in FIG.

In FIG. 7, a central control unit (CC) (1) is shown as the control unit (100) in FIG. 1, and a main storage unit (MM) (2) is shown as the storage unit (200) in FIG. The channel controller (CH) shown in FIG. 1 is used as the channel controller (300).
C) (3), an input / output controller (IOC) (4) is shown as the input / output controller (400) in FIG. 1, and an input / output bus (500) is shown as the input / output bus (500) in FIG. 5) is shown.

In FIG. 2, a transmission address register (SAR) (461) is provided as the transmission address holding means (491) in FIG. 1, and a reception address register (RA) is provided as the matching means (492) in FIG.
An R (462), a matching unit (MCH) (463) and a gate (G) (428) are provided.

Further, in FIG. 4, an address buffer (36) is provided as the address returning means (391) in FIG.
And a gate (37) is provided. 2 to 6
At the input / output control device (I
The DMA controller (DMC) (406) in the OC (4) and the DMA controller (31) in the channel controller (CHC) (3) are connected to the bus in the same process as shown in FIG. The request signal (c ₁ ), the bus request acceptance signal (c ₂ ) and the bus reservation signal (c ₃ ) are sequentially transmitted and received via the control bus (CB) (53) in the input / output bus (5). Reserve the output bus (5).

When the input / output bus (5) becomes ready for data transfer, the DMA controller (DMC) (406).
Sends the bus occupation signal (c ₄ ) to the control bus (CB) (53), sets the gate (418) to the conductive state, and is stored in the memory address register (MAR) in the same manner as described above. The address (a) to which no parity bit is added is sent to the address bus (AB) (51),
Data (d) from the external storage unit (FMU) (401)
After being extracted and stored in the buffer memory (BM) (402) once, the gate (404) is set to the conductive state and sent to the data bus (DB) (52), and then the control bus (C
B) The effective display signal (c ₅ ) is sent to (53).

The DMA controller (DMC) (406)
Activates the transmission address register (SAR) (461) when transmitting the address (a) stored in the memory address register (MAR) to the address bus (AB) (51) as the transmission address (a _S ). , Sending address (a
_S ) is stored and placed in the transmission address register (SAR) (461).

In FIGS. 2 and 3, when the bus occupation signal (c ₄ ) is being transferred to the control bus (CB) (53) and further transfer of the valid display signal (c ₅ ) is started, the gate is From (464) to the transmission address register (SA
The clock signal is input to the terminal (CP) of the R (461), and the transmission address (a _S ) input to the terminals (D ₀ ) to (D ₁₅ ) is transmitted to the transmission address register (SAR) (4).
61) is stored in.

D in the channel controller (CHC) (3)
The MA control unit (31) has a control bus (C
B) When receiving the valid indication signal (c ₅ ) transferred via (53), the gates (33) and (35)
Is set to a conductive state, and the transmission address (a _S ) and data (d) transferred via the address bus (AB) (51) and the data bus (DB) (52) are transferred to the interface control unit (32). ) Via main memory (MM)
Transfer data (d) to a predetermined address (a) of the main memory (MM) (2), and a reception confirmation signal (c ₆ ) to the control bus (CB) (53). Transfer to the input / output control device (IOC) (4) to be transferred.

The DMA control unit (31) transfers the transmission address (a _S ) transferred via the address bus (AB) (51) to the main memory unit (MM) via the interface control unit (32). ) (2) and activates the address buffer (36) [The activation trigger is the transmission address register (S) in the input / output control unit (IOC) (4).
AR) (461), the target input / output control device (IO)
C) The bus occupation signal (c 4) from ( ₄ ) is transferred to the control bus (C
B) When the effective display signal (c ₅ ) is further transferred in the state of being transferred to (53)], the transmission address (a _S ) is accumulated in the address buffer (36), and then received. In parallel with the transmission of the confirmation signal (c ₆ ), the gate (3
7) is set to the conductive state, and the transmission address (a _S ) already stored in the address buffer (36) is set to the reception address (a _R ).
As a result, the data is transferred to the target input / output control device (IOC) (4) via the address bus (AB) (51).

DM in the input / output control unit (IOC) (4)
The A control unit (DMC) (406) has a control bus (CB)
When the reception confirmation signal (c ₆ ) transferred via (53) is received, the transmission of the transmission address (a _S ) being transmitted to the address bus (AB) (51) is stopped, and the channel controller (CHC). Address bus (AB) (51) from (3)
Only the reception address (a _R ) transferred to the address bus (AB) (51) is transferred to the address bus (AB) (51).

In FIGS. 2 and 3, when the bus occupation signal (c ₄ ) is transferred to the control bus (CB) (53) and the transfer of the valid display signal (c ₅ ) is stopped, the gate ( 465) to receive address register (RAR)
The clock signal is input to the terminal (CP) of (462),
The reception address (a _R ) input to the terminals (D ₀ ) to (D ₁₅ ) is stored in the reception address register (RAR) (46).
2) is accumulated within.

Collating unit (MCH) comprising a plurality of exclusive OR gates (466) and an OR gate (467)
(463) is a transmission address register (SAR) (46
The transmission address (a _S ) stored in ₁ ) is compared with the reception address (a _R ) stored in the reception address register (RAR) (462). If they match, the logical product is obtained. The collation result signal (e) output from the gate (467) is set to the coincidence state (logic “0” in this example), and when they do not coincide, the OR gate (46).
The collation result signal (e) output from 7) is set to the disagreement state (logic "1" in this example).

The processor (MPU) (421) transmits from the decoder (DCR) (423) to the gate (G) (428) when the matching unit (MCH) (463) determines the matching result signal (e). Control the gate signal (g) to set the gate (G) (428) to the conductive state, read the verification result signal (e) via the data bus (DB) of the internal bus (422), and verify the verification result. When the signal (e) indicates the coincidence state, it is determined that the transmission address (a _S ) is normally transferred to the channel controller (CHC) (3), and the word count register (WCR) is stored in the same manner as described above. Subtract the accumulated word count (w) by one word count (w = w-1),
Further, the address (a) stored in the memory address register (MAR) is advanced (a = a + 1), and the operation proceeds to the transfer operation of the next word, but when the collation result signal (e) indicates a mismatched state. Determines that the transmission address (a _S ) has been erroneously transferred to the channel controller (CHC) (3), and the number of words (w) accumulated in the word count register (WCR) as well as the memory address register (MA
Stop updating the address (a) stored in R),
Retry the unsuccessful one-word transfer operation last time.

As is clear from the above description, according to this embodiment, when the data transfer is executed via the input / output bus (5), the channel controller (CHC) (3) transfers the address bus ( The transmission address (a _S ) sent to the AB (51) is temporarily stored in the channel control device (CHC) (3) and then returned to the address bus (AB) (51) as a reception address (a _R ). And the transmission address (a _S ) sent by the input / output control unit (IOC) (4),
The returned address (a _R ) is collated and the normality of data transfer is confirmed based on the collation result signal (e). Therefore, even if no parity bit is added to the transmitted address (a _S ), The normality of data transfer can be confirmed.

It should be noted that FIGS. 2 to 6 are merely embodiments of the present invention until now, and for example, the transmission address holding means (491) is provided.
The collating means (492) and the address returning means (391) are not limited to those shown in the figure.
Many other modifications can be considered, but in any case, the effect of the present invention does not change. Further, the channel control device (300) and the input / output control device (400) to which the present invention is applied.
Is not limited to the illustrated channel controller (CHC) (3) and input / output controller (IOC) (4), and many other variations are considered, but in any case The effect of the invention does not change. Further, it goes without saying that the information processing system to which the present invention is applied is not limited to the one shown in the figure.

[0040]

As described above, according to the present invention, in the information processing system, the normality of the address transferred via the input / output bus can be confirmed without adding an error detection / correction function to the address. The reliability of data transfer in the information processing system is significantly improved by using the existing channel controller, input / output controller and input / output bus.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing an input / output control device according to an embodiment of the present invention.

FIG. 3 is a diagram showing an address confirmation function portion in FIG.

FIG. 4 is a diagram showing a channel controller according to an embodiment of the present invention.

5 is a diagram showing an example of an address buffer in FIG.

FIG. 6 is a diagram showing a data transfer operation according to an embodiment of the present invention.

FIG. 7 is a diagram showing an example of an information processing system to which the present invention is applied.

FIG. 8 is a diagram showing an example of a conventional input / output control device.

FIG. 9 is a diagram showing an example of a conventional channel control device.

FIG. 10 is a diagram showing an example of a conventional data transfer operation.

[Explanation of symbols]

1 central control unit (CC) 2 main memory unit (MM) 3, 300 channel control unit (CHC) 4, 400 input / output control unit (IOC) 5, 500 input / output bus 31 DMA control unit 32 interface control unit 33, 34, 35, 37, 38, 39, 404, 40
5,407,416,417,417,418,427,42
8, 442, 443, 444, 464, 465, 46
6, 467 Gate 36 Address buffer 51 Address bus (AB) 52 Data bus (DB) 53 Control bus (CB) 100 Control device 200 Storage device 391 Address returning means 401 External storage unit (FMU) 402 Buffer memory (BM) 403 Error Detection / correction unit (ECC) 406 DMA control unit (DMC) 411 Input / output address holding unit (IOA) 412, 463 Collation unit (MCH) 413 Program mode control unit (PMC) 414, 423 Decoder (DCR) 415 Register group (REG) ) 421 processor (MPU) 422 internal bus 424 read only memory (ROM) 425 write read memory (RAM) 426 interrupt control unit (IRC) 431 clock generation unit (CKG) 441 refresh unit (REF) 451 fixed data storage unit (CPM) 452 Selector (SEL) 461 Transmission address register (SAR) 462 Reception address register (RAR) 491 Transmission address holding means 492 Collation means

Claims (4)

[Claims] 1. A channel controller (300) and a plurality of input / output controllers (400) are connected by an input / output bus (500), and each of the input / output controllers (400) controls the controller (100). An information processing system for transferring data to and from a storage device (200) via the channel control device (300) and the input / output bus (500). Address return means (3) for holding the address (a) sent from the input / output control device (400) that executes data transfer to the input / output bus (500) and returning it to the input / output bus (500).
91), and a transmission address holding means (491) for holding the address (a) to be sent to the input / output bus (500) when executing the data transfer in each of the input / output control devices (400).
And checking the address (a) held by the transmission address holding means (491) with the address (a) returned from the channel control device (300) to the input / output bus (500), An address confirmation system comprising: a collation unit (492) for confirming the normality of the address (a) transferred via the input / output bus (500) based on the collation result. 2. The address return means (391) transfers the held address (a) to the input / output control device (4).
2. The address confirmation method according to claim 1, wherein the data is returned after the data transfer by (00) is completed. 3. The input / output control device (400) confirms that the address (a) sent to the input / output bus (500) is received by the channel control device (300), and then performs the input / output control. 2. The address confirmation method according to claim 1, wherein the transmission to the bus (500) is stopped. 4. The address confirmation system according to claim 1, wherein the collating means (492) causes the data transfer that could not be confirmed as normal by the collation result to be retried.