JPS6217306B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for processing digital signals.

One problem that arises when transmitting or recording digital signals is the need to synchronize the playback device to the transmitting or recording device. This problem has been solved by using a clock signal that is recorded or transmitted separately from the information signal. However, this solution reduces the effective utilization of bandwidth and is often not a fundamental solution.

Another solution is to use the data signal itself to synchronize the regeneration circuit.
The regeneration circuit synchronizes upon the transition of bit values from one data bit to the next. The problem with this method of synchronization is that the data signal has long digital bits of the same bit value, such as 00000000, with no synchronized bit value transitions.
If it is a string, the circuits that depend on the reproduced digital signal will no longer advance.

A series of data signals received by the playback device is
If it is a long digital bit string with the same bit value, such as 00000000, 11111111,
Another problem arises. The DC component of the digital signal varies significantly between two consecutive data words. If 0 corresponds to 0 volts and 1 corresponds to 1 volt, then the DC component of the digital signal changes from 0 to 1. This change in the DC component causes many problems in regeneration.

The purpose of this invention is to significantly reduce the possibility of long digital bit strings with no bit value transitions, to easily extract the synchronization signal from the data itself, and to suppress fluctuations in the DC component of the digital signal. An object of the present invention is to provide a method for processing digital signals.

The features of this invention will become clear from the following description with reference to the drawings.

One embodiment of the invention will be described in relation to its use with television video signals. However, it will be appreciated that this embodiment is of common use, for example for acoustics. When converting a video signal into digital form, a technique is used that samples the video signal at equal time intervals and converts the sampled signal into a binary number. Assume that the binary number has 8 digits. The binary number “n” chosen is the voltage nq that most closely corresponds to the sampled signal.
It is thought that this causes The quantity "q" is the level difference between one level and the next.

An 8-digit binary number can represent decimal numbers 0 to 255. The decimal number 0 corresponds to the binary number 00000000, and the decimal number 255 corresponds to the binary number 11111111.
If “0” corresponds to 0 volts and “1” corresponds to 1 volt, then for non-return to 0 code (NRZ), the DC component of the digital signal will change from 0 volts to 1 volt.
Transforms into a bolt.

Another problem arises when digital bit strings of the same bit value, eg 00000000, occur. In this case, no transition occurs and the circuit relying on the regenerated clock signal will not step forward.

The method presented in this example is designed on the basis that there is a meaningful correlation between one closely spaced position and another position in a television image limited by sampling. has been done. As will be explained in more detail later, the method shown in this embodiment transmits two words sequentially along one transmission path. One word is complementary to the other word. Preferably, at least some bits of one word are interleaved with some bits of the other word, and the words are associated with spatially adjacent positions in the image. It is assumed that a meaningful correlation exists between the non-complementary data and the binary code selected accordingly.

The basic element transmits a word representing a point adjacent to it along a transmission path, and preferably between the digits of the word are associated with spatially adjacent parts of the image. It is to place digits of other words here and there. What is effectively required is that meaningful and clear correlations be possible between non-complementary data. This would allow the use of the signal one field later, for example.

The two words are usually numerically close to each other. However, this does not guarantee a sufficient number of transfers. To explain this, let's consider two words that represent 127 and 128. These binary numbers are usually represented as 01111111 and 10000000, respectively. The second words would be 01111111 if they were each complementary, so the two words would be 0011111111111111 if they were perfectly combined. This word contains one transition.

This problem is reduced by converting the two words into a suitable code before complementing the bits of one of the two words and holding that code until the critical part of the device has been passed. This problem will be severe for words that are approximately in the 3/8 to 5/8 overall range. Moreover, it additionally requires that the DC component of one word be low.

Parity is often used for error detection and error latency. Preferably, this parity is odd parity for odd numbers of bits. This is achieved by a factor of 2 that adds 3 or 5 bits together. If the total value is 0, the parity is "1", and if the total value is 1, the parity is 0. If such a parity bit is inserted into each word, the minimum number of transitions is increased.

Consider a continuous digital signal representing a television image that is transmitted to a television receiver. Successive digital signals relate to spatially proximate points in the television image, which are considered to be of approximately the same value. That is, the analog signal point
192 would be close to points 193 or 194, and it is physically impossible for point 300 to come next to point 192. Consider consecutive digital words representing points 192 and 193. points 192 and 193
The consecutive digital words representing are 11000000 and 11000001, respectively. Both words contain long digital bit strings of digital zero bits, which causes problems for receivers receiving the two words. In FIG. 2, the codes of the above two words containing parity bits are shown as 101100111 and 101101011, respectively.

If the second word is complemented and the two end bits of each word are swapped, we receive a signal as shown below.

101100101110010100 In this case, the maximum number of consecutive bits in the longest digital bit string with the same bit value is 3. This signal therefore has the effect of synchronizing the receiver clock circuit without causing any of the problems mentioned above.

Referring to FIG. 1, a video input signal is provided to an analog-to-digital converter (A-D converter) 10 through a comb filter. Converter 10 converts the video signal into digital words by sampling the video signal at multiples of the video signal subcarrier frequency. In this embodiment, the video signal is sampled at twice the frequency of the video signal subcarrier. Each word is then applied to code inverter 11. Code inverter 11 converts the binary word into a suitable code, such as that shown in FIG. Preferably, this is accomplished using read-only memory.
After code conversion, a parity bit is inserted into each word by a factor of 2 adding the first three bits of the word using non-alternative OR gates 12a, 12b. The words are then sequentially applied via start word insertion circuit 13 to four word latch circuits 16a-16d. The start word insertion circuit 13
Receives a signal from word generation circuit 13a. The start word generation circuit 13a operates at a line frequency and generates a digital signal to confirm the start of a new scanning line of the video signal. The start word is utilized to allow the playback device (not shown) to synchronize its operations and to aid in error detection and correction. The latches are arranged in pairs, one of each pair passing a word just as it enters the other latch, and the other outputting the complementary word as it enters the latch.

The operation of the portion of the circuit including latch circuits 16a and 16b will now be discussed. The same applies to other circuit parts, but these circuit parts are used selectively.
When the first word is provided through the start word insertion circuit 13, this first word is provided via the output line connected to all latch circuits. Thus, depending on which latch is being clocked, the word will go into one of the word latches.

Assume that the first word is clocked into latch 16a and the second word is clocked into latch 16b. The output signal from latch circuit 16a is indicative of the word applied to latch circuit 16a, and
The output signal from latch 16b corresponds to the complementary word of the word applied to latch circuit 16b. The output signals from latch circuits 16a, 16b are then provided to serialization and interpolation circuit 17a. In insertion circuit 17a, complementary words of the first word and the second word are inserted between each other. The degree of interpolation is predetermined, and in this embodiment only the seventh and eighth bits of each word are interpolated as shown. This is known to give satisfactory results.

The degree of inter-word insertion can vary, but is determined by the code used. For example, the code described above is not intended to be fully interpolated; in fact only the seventh and eighth bits of the word are chosen to be interpolated.

The words inserted between each other are then recorded in the record intensifier 1.
8b to a recording head 18a for recording the digital signal on a recording medium, preferably magnetic tape.

Referring to FIG. 2 in detail, two columns are shown for each number. The first column is the number written as a binary number, and the second column is the code assigned to the binary number, including the parity bits. Examining the second column, we find that 21 and
It becomes clear that for numbers between 234 (including 21 and 234) the maximum stroke length does not exceed 3 at the end of the word and 5 within the word. This is acceptable since statistics show that many words fall between the numbers 21 and 234.

Using the code shown in FIG. 2, the DC component is substantially reduced so that the clock signal is regenerated during playback.

This code can be used for color video signals. Although this code is shown in a recording mode, it can also be used for transmitting digital video signals.

Referring again to FIG. 1, it can be seen that the digital signal is processed in two channels and two recording heads are used, one for each channel. This configuration can be modified by continuously feeding the output signals from the two channels to the signal recording head.

As is clear from the above description, according to the present invention, the generation of long digital bit strings with the same bit value can be greatly reduced in digital signal processing, and the synchronization signal can be extracted from the data itself. Therefore, fluctuations in the DC component of the digital signal can be suppressed to a small level.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus for generating digital signals, and FIG. 2 is a diagram showing the code used in the apparatus of FIG. 9...Filter, 10...Analog-digital converter, 11...Code converter, 13a...Start word generation circuit, 13...Start word insertion circuit, 16a, 16b, 16c, 16d...
. . . word latch circuit, 17a . . . serialization and intercalation circuit, 18a . . . recording head, 18
b... Recording amplification device.

Claims (1)

[Claims] 1. (a) sampling an analog signal; (b) converting the sampled analog signal into consecutive digital words each consisting of a plurality of bits; and (c) the analog values being substantially the same. converting each digital word into a coded word such that the digital words for the analog signal are converted into coded words whose DC components are substantially the same; (d) converting one of the two consecutive coded words into a coded word; (e) converting the coded word in the unchanged form and the coded word in the complementary form to bit serial form; A digital signal processing method characterized by: 2 For every two consecutive coded words, hold in unchanged form, convert to complementary form and bit bit
A method of processing a digital signal according to claim 1, characterized in that the conversion to serial form is performed in a separate channel. 3. selectively inserting bits of the coded word in the unchanged form and the coded word in the complementary form into each other when converting the coded word in the unchanged form and the coded word in the complementary form to bit-serial form; A digital signal processing method according to claim 1, characterized in that: