JPS62172728A - Dielectric isolated wafer - Google Patents

Abstract

PURPOSE:To prevent the failure of a wafer by a method wherein, with the peripheral surface of the wafer shaved off in such a way that the outer diameter of the wafer is reduced, the first surface and second surface of the wafer are shaved off deeper toward the outer periphery of the wafer. CONSTITUTION:With the peripheral surface of a wafer where dielectric isolation has taken place shaved off in such a way that the outer diameter of the wafer is reduced, the first surface and second surface of the wafer are shaved off deeper toward the outer periphery of the wafer. The profile of the final DI wafer section is formed into a wedge from toward the end surface of the wafer. Thereby the DI wafer is not subjected to stress due to the thermal expansion of quartz in a high temperature atmosphere and the warpage and the failure of the DI wafer can be prevented.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to a dielectric isolation wafer (hereinafter referred to as DI wafer).
Regarding.

[Background technology]

Dielectric isolation (hereinafter referred to as DI) is a semiconductor element isolation technology, in which the region where each semiconductor element is made is separated by SiO
, etc., to electrically insulate each semiconductor element.

Conventionally, as shown in Fig. 1, a groove (2) is dug by performing anisotropic etching on a silicon single crystal 100-axis substrate (1) (Fig. 1 (a) ), and several polysilicon layers (3) are stacked on top of it (Figures 1(b) to (d) illustrate this). By cutting off the part indicated by the dashed-dotted line and turning it upside down, an I-wafer as shown in FIG. 1(f) is completed. However, with this method, the growth of polysilicon encloses the original single crystal wafer in the drawing, and even if both sides are polished off, the diameter of the finished DI wafer is 0.0 mm smaller than the diameter of the original single crystal. It becomes larger by about 5 μm. Therefore, DI wafers are placed in quartz jigs (carriers, diffusion furnace boats, etc.) that process single crystal wafers.
quartz is susceptible to stress due to thermal expansion in a high-temperature atmosphere. [Objective of the Invention] This invention makes the outer diameter and peripheral shape of a DI wafer similar to that of commercially available wafers. The aim is to enable processes similar to those for crystal wafers to proceed.

The gist of the present invention is a dielectric-separated wafer characterized in that the t-plane is ground down so that the outer diameter becomes smaller, and the front and back surfaces are ground down toward the outer periphery and deeper. An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

The following steps are added to the steps (a) to (f) in FIG. Similar to conventional commercially available wafers, as shown in Figure 2,
The periphery of the wafer, which has been electrically separated, is scraped off from three directions: the front and back surfaces, and the circumferential surface.

That is, the peripheral surface is ground down so that the outer diameter becomes smaller, and the front and back surfaces are ground down toward the outer periphery and deeper. The final cross-sectional view of the I-wafer (4) is as shown in FIG. 3, and the outline of the cross-section is wedge-shaped toward the end surface, similar to commercially available wafers, and the wafer diameter is also approximately the same as that of commercially available wafers.

〔Effect of the invention〕

The Dr wafer of this invention has a cross-sectional shape and a wafer diameter equivalent to commercially available wafers, so it can be set in the slit of a diffusion furnace boat with plenty of room, so it is less susceptible to stress caused by thermal expansion of quartz in a high-temperature atmosphere. First, the DI wafer will not be warped or damaged.

Also, since it can be set in the quartz carrier with plenty of room, D
No damage occurs when loading and unloading I-wafers. Furthermore, since the blade enters smoothly during dicing, conventional semiconductor manufacturing equipment can be used efficiently, such as reducing damage to the blade, and the Dr wafer will not be damaged.

[Brief explanation of drawings]

1(a) to Cf> are cross-sectional views showing a conventional example of the present invention, and FIGS. 2 and 3 are cross-sectional views showing an embodiment of the present invention. (1)...Substrate, (2)...V groove, (3)...Silicon layer.

Claims (1)

[Claims] (1) A dielectric-separated wafer characterized in that the peripheral surface is ground down so that the outer diameter becomes smaller, and the front and back surfaces are ground down toward the outer periphery and deeply.