JPS62171321A - Oversampling type analog-to-digital converter - Google Patents

Abstract

PURPOSE:To improve an S/N by constituting the 1st quantizer as to quantize the sum signal of the output of the 1st integration circuit and the output of the 2nd integration circuit, and adding the output of the integration circuit of a subordinate loop to the output of the integration circuit of a main loop and then quantizing the main loop. CONSTITUTION:Analog switch SWs 50-1 and 50-3 are turned on and SWs 50-2 and 50-4 are turned off on the main loop side to charge a capacity element 50-5 with an input voltage Vin. Then when the switches are placed in the reverse state, a capacity element 50-7 is charged to the sum of charges of capacity elements 50-5 and 50-12. Simultaneously, a capacity element 50-20 is charged with the output of an operational amplifier 50-6 even on the subordinate loop side and a capacity element 50-22 is charged to the sum of charges of capacity elements 50-20 and 50-27 in a next period. Then, a quantizer which is composed of one voltage comparator and has one-bit resolution quantizes the integration output sum of the main and subordinate loops. Consequently, the high S/N is obtained without using any special operational amplifier.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an oversampling type analog/digital converter that achieves a low conversion product by performing a conversion operation at a very high frequency compared to the signal frequency. This article relates to converters (hereinafter referred to as A/D converters).

[Conventional technology]

When sampling an analog signal, it is known that the original signal can be restored by setting a sampling frequency rB that is at least twice the signal frequency band fBW according to Nyquist's theorem.

Therefore, the sampling frequency fs of a typical Lux converter is selected to be about 2 to 4 times the signal frequency band fBW. On the other hand, the oversampling converter aims to improve conversion accuracy by setting the sampling frequency f8 to a frequency considerably higher than twice the signal frequency band fBW.

FIG. 8 is a block diagram showing the basic configuration of a conventional type, which is called a multi-stage quantization noise shaping type N-type converter capable of high-precision conversion. This circuit is an integral circuit 13
．． 14. A main loop consisting of a delay circuit 15, a feedback D/A circuit 16, and an integrating circuit 22. Quantizer 23
．． It has a two-stage loose loop consisting of a delay circuit 24 and a feedback 0/A circuit 25, 11.12 is a terminal, 26 is a differentiation circuit, 18 is a delay circuit, 17, 20.21
is a subtraction circuit, and 2T is an addition circuit. The analog signal is quantized in the main loop, and the quantization errors that occur at that time are further quantized in the sub loop. The quantization error of the main loop is corrected by adding the output of the sub-loop to the output of the main loop.

If the input signal is Vin, the quantization noise generated by the i-digitizer 14 is v,1, and the quantization noise generated by the quantizer 23 is V□, then the digital output signal is. U is expressed by two functions as shown in equation (1).

Ho is the transfer function of the integrating circuit 13 and the integrating circuit 22, 1/H
8 is the transfer function of the differentiating circuit 26. As is clear from equation (1), the transfer function H8 and I (if l are equal, vl,
Equation (2) is derived by eliminating the term.

In this way, the term of the quantization error v9□ in the main loop is eliminated, leaving only the term v9□. Since the quantization noise vq, l generated by the quantizer 130 is suppressed in the low frequency range by the transfer functions H0 and H8, high conversion accuracy can be obtained.

FIG. 9 is a circuit diagram showing the details of the conventional device, in which thick lines indicate digital signals and thin lines indicate analog signals, and the integration circuit is realized by switched capacitor circuit technology.

In the figure, 50-1 to 50-4.50-8 to 50-1
1, 50-16 to 50-19.50-23 to 50-2
6 is an analog switch constituting the switch circuit, 50-
5.50-7.50-12゜50-20, 50-22
, 50-27 are capacitive elements, 50-6, 50 to 21 are operational amplifiers, and 52.53 are switch control circuits. Therefore, the quantizer 14.23 has voltage ratio regulators 50-13, 5
0-28.

In the lyA converter ti, the switch control circuit 52 controls the switches 50-8.50-9.50-10.50-11 to set the capacitor 50-12 (capacitance value CDI) to v.
nvv 'I11. This is realized by charging the voltage and integrating the charge of the capacitance value CDI into the d-quantity element 50-7 (capacitance value CII). Q, VREF to capacitance value CDI
When charging the voltage, the switch control circuit 52 switches between charging in the positive direction and charging in the negative direction, and the analog voltage value is added to the integral value. In addition, the switch control circuit 53, the switch 50-23.50-24.50-
25.50-26, capacitive element 50-27 (capacitance value C
D2) and the capacitive element 5O-22 (capacitance value CII) operate in the same manner.

In the circuit configured in this way, the operational amplifier 50-6
, 50-21, the transfer function of the integrating circuit and the differentiating circuit is expressed as in equation (3).

It can be seen that if the gain A is very large, the transfer functions H1 and H,3 are almost equal, but if the gain A is small, the term v91 in equation (1) cannot be eliminated. Furthermore, even if the transfer function of 1/mouth is adjusted to Hl, since the differentiating circuit 12 is a digital circuit, the circuit scale will become very large if multiplication is required, and the calculations generally made using integrated circuits, etc. This is not a practical method because the amplifier gain varies. FIG. 10 shows the gain dependence of a conventional pair of amplifiers obtained by simulation using the amplifier gain as a parameter. However, sampling frequency fs=2
．． 048MHz, signal band f! IsV = 4KI(,
+ k-child resolution = 1 bit. When the amplifier gain is 80 dB, S/N deterioration is small, but below 70 dB, the deterioration becomes noticeable. For oversampling converters, it is necessary to set the sampling frequency high.
Since the bandwidth of the operational amplifier is also required to be wide, it is difficult to obtain a good gain. If variations in operational amplifier gain are taken into account, only an even lower amplifier gain can be obtained.

For this reason, the conventional type had a drawback in that it was not possible to obtain a high S.

[Means for solving problems]

In order to solve these drawbacks, the present invention adds the output of the integrator circuit of the sub-loop to the output of the integrator circuit of the main loop, and then quantizes the main loop.

[For production]

The quantization output of the main loop is determined by the integral output of the sub-loop, reducing quantization errors.

[Real example]

FIG. 1 is a block diagram showing one embodiment of the present invention,
The same symbols are used for the same parts as in FIG. 8.

Reference numeral 60 denotes an adder circuit, which inputs the output of the sub-loop integrator circuit to the quantizer 14 in addition to the output of the main-loop integrator circuit. Output in the configuration shown in FIG. ut is expressed by two functions as shown in equation (4).

However, for simplicity, the transfer function is set to H=H3.

Here, it is clear that if we set the transfer function F (8=f), equation (2) is derived as in the conventional form. Therefore,
If the gain of the operational amplifier is very high as in the ideal state, the S/N characteristic will be exactly the same as that of the conventional type.

However, the gain of the operational amplifier is low and the transfer function is H8~
For the case of H1, the conventional formula (1) and the present invention's formula (4)
The difference becomes clear when comparing the second term including v and 1 in the equation.

Since I (1 is the transfer function of the integrating circuit, it has a large gain in the low frequency region of the signal band and 1 (Hl holds true. Therefore, the second terms of equations (1) and (4) are expressed as 1 () Simplifying it as l□, the second term of equation (1) becomes vqyo・(Ha−Hl)
/(f(1-H,) The second term of equation (4) is (V, 1-vq2)・(H3-Hl)/(2H1・H
8). Here, tevq□ is the quantization error that occurs when quantizing the sum of the integrator outputs of the main loop and the sub-loop, and ■9 is the quantization error that occurs when only the integrator output of the sub-loop is quantized. Because of the conversion error, ■4 and v,2 have similar values. Therefore, it can be seen that the second term in equation (4) is smaller than in the conventional type.

FIG. 2 is a circuit diagram showing details of the invention, in which the integrating circuit is realized by switched capacitor circuit technology. The feedback D/A circuit also uses a switched capacitor circuit and performs addition at the virtual ground point of the amplifier.

FIG. 3 is an operation timing diagram when this circuit reaches an equilibrium state, and the operation will be explained with reference to this diagram. 3(a) and 3(b) show the operation of the main loop, and FIGS. 3(C) and 3(d) show the operation of the sub loop.

Capacitive element 50- indicated by symbol “A” in FIG. 3(b)
12 presetting and charging of the capacitive element 50-12 to the capacitive element 50-7, the symbol "
The presetting of the output cables 50-27 indicated by "" is the operation performed in the previous cycle, and the operation after this presetting is completed will be explained.

On the main loop side, first, analog switch (hereinafter referred to as SW) 50-1.50-3 is turned on, sws.

-2 and 50-4 are turned off, and the capacitive element 50-5 is charged with the input voltage ln as shown in the (-) symbol [below].

Next, turn off 5W50-1.50-3, 5W50-2
．． When 50-4 is turned on, capacitive element 50-7, K capacitive element 50-5, and capacitive element 5 are connected as shown by symbol "2".
The sum of charges 0-12 is charged. In parallel, in the sub-loop, the output of the operational amplifier 50-6 (integrated output of the main loop one cycle before) is applied to the capacitive element 50-20 as shown by the symbol "E" in (c). In the next half cycle, the electric charges of capacitive elements 50-20 and 50-27 are multiplied by force g and integrated as shown by the symbol "to" in (e). .

For a long time, a 1-bit resolution Doji converter consisting of a voltage comparator 1@ is used to quantize the sum of the integral outputs of the main loop and the sub-loop. Based on the result, the capacitive element 50-12 is preset as shown by the symbol "G" in (b), and the charge of the capacitive element 50-12 is transferred to the storage element 50-7 as shown by the symbol "C".
A feedback Q/A circuit is realized by dividing the VC bonds. Thereafter, similar operations are repeated.

Since the input signal of the sub-loop is the output of the main loop's integrator circuit minus the output of the feedback A circuit 16, as shown in the timing of FIG. By shifting the integral by half a synchronization, the sub-loop input signal is generated in the first half of the cycle, so at this time, 5W50-16°50-18 is turned on,
7. Capacitive element 50-20 with 50-19 in off state
It is possible to charge. Capacitive element 50-12.5
The capacitor 0-27 charges the reference voltage VREF by changing the polarity according to the output result of the voltage comparator in the switch control circuit, and feeds either of the two values VREF and -vREF back to the integrating circuit VC.Delay Circuit 18 and differentiation circuit 2
Since numeral 6 processes digital signals, it is composed of a delay circuit 18 composed of a latch circuit, etc., 5G-30, and a 1-bit digital counter 50-31.

In the embodiment shown in FIG. 2, the transfer functions H1+H2, H3 are expressed by equation (3) as in the conventional type. Figure 4(a) l
When the amplifier gain and gain are used as parameters in (b), sampling frequency fs = 2.048M[z, signal band tBw
2 shows the S/N vs. amplifier gain dependence of the circuit shown in FIG. 2 when the encoder resolution is 1 bit = 4 KHz.

The simulation was performed under the same conditions as the conventional type, but it can be seen that the deterioration of the pupil is very small compared to the conventional type, and when the input signal level is low, the deterioration of the pupil is very small.

In the case of audio signals, even if the signal deteriorates at a high input level as shown in Figure 4, it cannot be discerned audibly.
Pupil deterioration at high input levels often poses no problem in practice. Thus, it can be seen that the present invention has the favorable characteristics that the S/N deterioration range is small when the input is small, and the deterioration that occurs at a high input level does not pose a practical problem.

FIG. 5 shows the change in S/NtTj characteristic when a DC offset voltage is added to the analog signal input when the amplifier gain is 60 dB in the circuit shown in FIG. It can be seen that even if an offset of 0.01 to 0.05 is added, SIN hardly changes. 6th
The figure shows the relationship between the ratio accuracy and master of the capacitive elements of the switched capacitor circuit when the amplifier gain is 60 dB.
Although similar effects are seen in both cases, FIG. 6 shows the case where the capacitive element 50-27 is varied. When a capacitive element is formed on a capacitor circuit, its relative accuracy is approximately 0.1 to 1.0% without trimming, so it can be seen from Figure 6 that there is almost no deterioration depending on the relative accuracy of the capacitor. Recognize.

Another embodiment of the invention is shown in FIG. The difference from the embodiment shown in FIG. 2 is that the blade calculator 60 at the input of the quantizer 140 is not the embodiment shown in FIG.

If the switching gears of SW50-16 and SW50-17 are swapped, the polarity of the signal will be reversed. Although the voltage comparator 50-13 in FIG. 7 calculates the difference, the octamount element 50-2
By inverting the polarity of the sampling of 0, addition can be realized, and the power-log calculator 60 becomes unnecessary.

〔Effect of the invention〕

As explained above, in this invention, the first quantizer is
The output of the integrating circuit of g1 and the output of the second dividing circuit are connected to each other.
: Since the configuration is such that the quantized signal is quantized, it is possible to realize the pupil without increasing the circuit scale and without using a special multiplier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram thereof, FIG. 3 is a diagram showing operation timing, and FIG.
The figure is a graph showing the S/N vs. gain dependence characteristic of the circuit shown in Fig. 2, Fig. 5 is a graph showing the common vs. offset voltage dependence characteristic, and Fig. 6 is a graph showing the S/N vs. capacitance ratio accuracy dependence characteristic. Graph, FIG. 7 is a circuit diagram showing another embodiment, FIG. 8 is a block diagram showing an example of a conventional device, FIG. 9 is a circuit diagram showing an example of a conventional device, and FIG. 10 is shown in FIG. This is a graph showing the gain dependence characteristics of the circuit. 13.22...Integrator circuit, 14.23...Quantizer, 16.25...Feedback D/A circuit, 26...
・Differential circuit, 17, 20.21...Subtraction circuit, 27
．． 60...addition circuit. Patent applicant: Nippon Telegraph and Telephone Corporation Agent Masaki Yamakawa (#1 person) Figure 1 S/N (dB) ” S/N (dB) S/N (dB) S/N (dB) Figure 8 Figure 10 side (-dB)

Claims (1)

[Claims] a first integrating circuit, a first quantizer that quantizes the output signal of the first integrating circuit and converts it into a digital signal, and a first feedback D/A that converts the output of the first quantizer into an analog signal.
a first loop consisting of a subtraction circuit that subtracts the output of the first feedback D/A circuit from the input signal to input the first feedback D/A circuit, and the output of the first integration circuit and the first feedback D/A circuit; a subtracter for calculating a quantization error, which calculates a quantization error by calculating the difference from the output of circuit A; a second integrating circuit; and a second integrating circuit, which quantizes the output signal of the second integrating circuit and converts it into a digital signal. 2 quantizer, a second feedback D/A circuit that converts the second quantizer output into an analog signal, and a second feedback D/A circuit that subtracts the second feedback circuit output from the quantization error calculation subtracter output. a second loop consisting of a second subtractor that is input to the integrator circuit;
a differentiation circuit that differentiates the output signal of the second quantizer;
In an oversampling analog-to-digital converter consisting of an adder that adds the output of a quantizer and the output of a differentiation circuit, the first quantizer adds the output of the first integration circuit and the output of the second integration circuit. An oversampling type analog-to-digital converter characterized by having a configuration that quantizes a signal obtained by adding outputs.