JP2014146893A - Multi-bit δς modulator and multi-bit a/d converter using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high precision multi-bit ΔΣ modulator.SOLUTION: The multi-bit ΔΣ modulator includes: an integration circuit for sampling at a first period λ1 and integrating differential input signals; an A/D converter 1 for converting output signals of the integration circuit to digital signals D1-Dn at a second period λ2 (=2λ1); a feedback signal generation circuit 2 for converting the digital signals D1-Dn to a binary feedback signal FB; one-bit D/A converters 3, 4 for converting a logic level of the feedback signal FB to voltages at the first period λ1; and a subtraction circuit for subtracting amounts of charge depending on the voltages generated by the D/A converters 3, 4 from integration values of the integration circuit. This dispenses with an effect of a manufacturing variation of an n-bit D/A converter.

Description

  The present invention relates to a multi-bit ΔΣ modulator and a multi-bit A / D converter using the multi-bit ΔΣ modulator, and more particularly to a multi-bit ΔΣ modulator that converts an analog input signal into a multi-bit digital signal sequence, and a multi-bit using the multi-bit ΔΣ modulator The present invention relates to an A / D converter.

  In recent years, the detection accuracy of acceleration sensors and angular velocity sensors using MEMS (Micro Electro Mechanical Systems) technology has improved rapidly, and the S / N (signal-noise) ratio of sensor ASICs (Application Specific Integrated Circuits) used to control them has also improved. It is requested. An A / D (Analog / Digital) converter, which is an input part of the sensor ASIC, also has a circuit configuration capable of realizing a high S / N ratio by increasing the order.

  Patent Document 1 aims to provide a ΔΣ A / D converter capable of realizing a high S / N ratio and a wide input signal band without increasing the actual clock frequency. For this reason, a plurality of sets of comparators, DFFs (D Flip-Flop), and D / A converters are prepared, and the effective oversampling rate is increased by performing an interleaving operation. That is, the resolution is improved by increasing the clock frequency of feedback.

  Patent Document 2 discloses a high-order single-bit ΔΣ modulator that achieves high accuracy. In the ΔΣ A / D converter, when the ΔΣ modulator is a minute AC input or no input, a tone component generated in the quantization noise of the quantized data is prevented from appearing in the output. The five integrators are cascaded, their outputs are added, and the addition result is quantized by the comparator into a 1-bit data signal. The 1-bit D / A converter subtracts the + Vref or −Vref quantization step from the input to the integrator, depending on the polarity of the data signal. By applying a DC offset voltage to the input side of the integrator, the frequency of the tone component of the quantization noise is moved out of the pass band of the digital filter. Therefore, this tone component is filtered by the digital filter and does not appear in the passband due to aliasing or the like. In general, in order to stabilize the operation of a high-order ΔΣ modulator, it is preferable that the built-in feedback D / A converter is multi-bit.

  Patent Document 3 discloses a multi-bit ΔΣ A / D converter that achieves higher accuracy and wider bandwidth without increasing the oversample ratio and the order of the analog integrator. The multi-bit ΔΣ A / D converter includes an analog adder that outputs a difference signal between an analog input signal and an analog feedback signal, an analog integrator that integrates an output signal of the analog adder, and an output signal of the analog integrator The n-bit quantizer that quantizes the signal with multiple bits and the subtracter subtracted the signal obtained by delaying the low-order bits except the most significant bit of the output of the digital subtractor with the delay device from the output of the n-bit quantizer. It comprises a digital processing unit that performs processing for outputting the most significant bit of the signal, and a 1-bit D / A converter that converts the output signal of the digital processing unit into an analog signal and outputs it as an analog feedback signal. Since the most significant bit is fed back, the quantization error generated in the D / A converter is large.

  Patent Document 4 discloses a method for calibrating the non-linearity of a multi-bit ΔΣ modulator in order to improve the accuracy of an A / D converter. The calibration multiplexer supplies a voltage 0 to the ΔΣ modulator (ternary output) during calibration. The outputs of the +1 processor and the compensation circuit are summed in the summation unit. Its value is the digital output of the A / D converter. The output of the -1 processor is compensated based on the coefficient δ in the compensation circuit. The processor includes an accumulator (register and arithmetic unit) that switches between a filter coefficient and a ground voltage. The δ coefficient is calculated by the delta processor during the calibration time. The Δ processor outputs a value to the multiplier. After calibration, the coefficient of δ is frozen and the calibration multiplexer selects the analog input. In the multi-bit ΔΣ modulator, correction is necessary due to the nonlinearity of the built-in D / A converter.

JP-A-6-326610 JP-A-7-143006 JP 2001-156642 A US Pat. No. 5,257,026

  As described above, in order to increase the accuracy of the ΔΣ modulator (A / D converter), it is necessary to increase the order of the ΔΣ modulator and to increase the number of bits of the internal quantizer. In order to increase the order and perform stable operation, it is necessary to increase the number of bits of the internal quantizer, so attention is paid to the internal quantizer. When the number of bits of the quantizer is increased, it is necessary to increase the number of bits of the internal D / A converter, but manufacturing variations occur in the D / A converter itself. For this reason, the accuracy of the built-in D / A converter deteriorates, and there is a problem that the accuracy of the ΔΣ modulator as a whole deteriorates.

  Therefore, a main object of the present invention is to provide a highly accurate multi-bit ΔΣ modulator and a multi-bit A / D converter using the same.

A multi-bit ΔΣ modulator according to the present invention is a multi-bit ΔΣ modulator that converts an analog input signal into an n-bit (where n is an integer of 2 or more) digital signal sequence, and the voltage of the analog input signal A first integration circuit that samples the amount of charge according to the first period, integrates the sampled charge amount, and outputs a voltage signal according to the integration value, and 2 ⁿ times the first period An A / D converter that converts the voltage of the output signal of the first integration circuit into an n-bit digital signal in the second period and outputs the digital signal, and a binary feedback of the digital signal generated by the A / D converter And a feedback signal generation circuit that converts the signal into a signal. The feedback signal is set to the first or second logic level in the first period. The time during which the feedback signal is at the first logic level within the second period indicates the value of the digital signal. The multi-bit ΔΣ modulator further includes a 1-bit D / A converter that converts the logic level of the feedback signal into a voltage in the first period, and an amount corresponding to the voltage generated by the D / A converter. A subtracting circuit that subtracts the electric charge from the integrated value of the first integrating circuit in a first period.

  The multi-bit A / D converter according to the present invention includes a multi-bit ΔΣ modulator and a digital filter that removes noise from the digital signal sequence output from the multi-bit ΔΣ modulator and converts the digital signal into a digital code. It is a thing.

  In the multi-bit ΔΣ modulator according to the present invention, the n-bit digital signal generated by the A / D converter is converted into a binary feedback signal by the feedback signal generation circuit, and the feedback signal is converted into a 1-bit D / A. The voltage is converted into a voltage by the converter at the first period and fed back to the first integrating circuit. Therefore, since the feedback signal generation circuit and the 1-bit D / A converter are provided instead of the n-bit D / A converter, there is no influence of manufacturing variations of the n-bit D / A converter. Therefore, a highly accurate multi-bit ΔΣ modulator can be realized.

1 is a circuit block diagram showing a configuration of a multi-bit ΔΣ modulator according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing a configuration of a feedback signal generation circuit shown in FIG. 1. It is a block diagram which shows the principal part of the multibit delta-sigma modulator by Embodiment 2 of this invention. It is a block diagram which shows the principal part of the multibit delta-sigma modulator by Embodiment 3 of this invention. It is a circuit block diagram which shows the structure of the multibit delta-sigma modulator by Embodiment 4 of this invention. It is a block diagram which shows the structure of the multibit delta-sigma A / D converter by Embodiment 5 of this invention. It is a block diagram which shows the structure of the digital filter shown in FIG.

[Embodiment 1]
As shown in FIG. 1, the multibit ΔΣ modulator according to the first embodiment of the present invention includes input terminals TIP and TIN, switched capacitor circuits SC1 and SC2, a differential amplifier circuit A1, capacitors CL1P and CL1N, and A / D conversion. 1, a feedback signal generation circuit 2, and D / A converters 3 and 4.

  Input terminals TIP and TIN receive differential input signals VIP and VIN, respectively. Each of the differential input signals VIP and VIN is an analog signal. Differential input signals VIP and VIN are applied to switched capacitor circuit SC1. Switched capacitor circuit SC1 includes switches S1 to S8 and capacitors CS1P and CS1N.

  The switch S1, the capacitor CS1P, and the switch S4 are connected in series between the input terminal TIP and the inverting input terminal (−input terminal) of the differential amplifier circuit A1. One terminal of switch S2 is connected to a node between switch S1 and one electrode of capacitor CS1P, and the other terminal of switch S2 receives reference voltage AGND. Reference voltage AGND is, for example, a voltage between the power supply voltage and the ground voltage. One terminal of switch S3 is connected to a node between the other electrode of capacitor CS1P and switch S4, and the other terminal of switch S3 receives reference voltage AGND.

  Similarly, the switch S5, the capacitor CS1N, and the switch S8 are connected in series between the input terminal TIN and the non-inverting input terminal (+ input terminal) of the differential amplifier circuit A1. One terminal of switch S6 is connected to a node between switch S5 and one electrode of capacitor CS1N, and the other terminal of switch S6 receives reference voltage AGND. One terminal of the switch S7 is connected to a node between the other electrode of the capacitor CS1N and the switch S8, and the other terminal of the switch S7 receives the reference voltage AGND.

  The capacitor CL1P is connected between the inverting input terminal and the non-inverting output terminal of the differential amplifier circuit A1. The capacitor CL1N is connected between the non-inverting input terminal and the inverting output terminal of the differential amplifier circuit A1.

  Of the switches S1 to S8, the odd-numbered switches S1, S3, S5, and S7 and the even-numbered switches S2, S4, S6, and S8 are alternately turned on in the first period λ1. When the odd-numbered switches S1, S3, S5, and S7 are turned on, the capacitors CS1P and CS1N are charged to the voltages of the differential input signals VIP and VIN, respectively, and the differential input signals VIP and VIN are respectively input to the capacitors CS1P and CS1N. The amount of electric charge corresponding to the voltage is stored.

  Next, when the even-numbered switches S2, S4, S6 and S8 are turned on, the charges stored in the capacitors CS1P and CS1N are transferred to the capacitors CL1P and CL1N, respectively. The differential amplifier circuit A1 outputs differential signals V1P and V1N having levels corresponding to the voltages across the terminals of the capacitors CL1P and CL1N, respectively.

  That is, the switched capacitor circuit SC1, the differential amplifier circuit A1, and the capacitors CL1P and CL1N circuits constitute an integration circuit. This integrating circuit samples the amount of charge according to the voltages of the differential input signals VIP and VIN at the first period λ1, integrates the sampled amount of charge, and voltage differential signals V1P, V1P, V1N is output.

  The A / D converter 1 uses the difference voltage between the differential signals V1P and V1N as a digital signal D1 to Dn of n bits (where n is an integer equal to or greater than 2, for example, 2) in the second period λ2. Convert to The second period λ2 is 2n times (for example, 4 times) the first period λ1. The feedback signal generation circuit 2 converts the output signals D1 to Dn of the A / D converter 1 into a binary feedback signal FB. The feedback signal FB is set to the “H” level or the “L” level in the first period λ1. Further, the time during which the feedback signal FB is at the “H” level within the second period λ2 indicates the values of the digital signals D1 to Dn. Note that the A / D converter having a small resolution is used as the A / D converter 1.

  FIG. 2 is a block diagram showing a configuration of the feedback signal generation circuit 2. In FIG. 2, the feedback signal generation circuit 2 includes an up counter 10 and a comparator 11. The up counter 10 counts the number of pulses of the clock signal CLK having the first period λ1, and outputs n-bit count signals C1 to Cn indicating the count value. The comparator 11 compares the values of the digital signals D1 to Dn from the A / D converter 1 with the values of the count signals C1 to Cn from the up counter 10 and uses a signal indicating the comparison result as a feedback signal FB. Output.

  When the values of the digital signals D1 to Dn are larger than the values of the count signals C1 to Cn, the feedback signal FB is set to the “H” level, and the values of the digital signals D1 to Dn are less than or equal to the values of the count signals C1 to Cn The feedback signal FB is set to the “L” level.

  For example, when the values of the digital signals D1 and D2 are 0, the values of the count signals C1 and C2 sequentially change to 0, 1, 2, and 3 in the first period λ1, and the feedback signal FB has the second period λ2. It is set to “L” level during the whole period. When the values of the digital signals D1 and D2 are 1, the feedback signal FB is set to “H” level only for the first quarter period of the second period λ2, and “H” is set for the subsequent 3/4 period. To the level.

  When the values of the digital signals D1 and D2 are 2, the feedback signal FB is set to “H” level only for the first ½ period of the second period λ2, and “L” for the subsequent ½ period. To the level. When the values of the digital signals D1 and D2 are 3, the feedback signal FB is set to the “H” level only for the first 3/4 period of the second period λ2, and “L” for the subsequent 1/4 period. To the level.

  The D / A converter 3 converts the logic level of the feedback signal FB into the analog voltage V3 in the first period λ1. When the feedback signal FB is at “H” level, the analog voltage V3 is a predetermined positive voltage VP, and when the feedback signal FB is at “L” level, the analog voltage V3 is the reference voltage AGND.

  The D / A converter 4 converts the logic level of the inverted signal of the feedback signal FB into the analog voltage V4 in the first period λ1. When the feedback signal FB is at “H” level, the analog voltage V4 is a predetermined negative voltage VN, and when the feedback signal FB is at “L” level, the analog voltage V3 is the reference voltage AGND.

  Switched capacitor circuit SC2 includes switches S9 to S12 and capacitors CS2P and CS2N. One electrode of the capacitor CS2P is connected to the reference voltage AGND line via the switch S9 and receives the output voltage V3 of the D / A converter 3 via the switch S10. The other electrode of capacitor CS2P is connected to a node between capacitor CS1P and switch S4.

  One electrode of the capacitor CS2N is connected to the reference voltage AGND line via the switch S11 and receives the output voltage V4 of the D / A converter 4 via the switch S12. The other electrode of capacitor CS2N is connected to a node between capacitor CS1N and switch S8.

  Of the switches S9 to S12, the odd-numbered switches S9 and S11 and the even-numbered switches S10 and S12 are alternately turned on in the first period λ1. When the odd numbered switches S9 and S11 are turned on together with the switches S1, S3, S5 and S7, the voltage between the terminals of the capacitors CS2P and CS2N is reset to 0V.

  Next, when the even-numbered switches S10 and S12 are turned on together with the switches S2, S4, S6 and S8, the charges stored in the capacitors CS1P and CS1N are transferred to the capacitors CS2P and CS2N, respectively.

  That is, the switched capacitor circuit SC2 constitutes a subtraction circuit. This subtraction circuit subtracts an amount of charge corresponding to the voltages V3 and V4 generated by the D / A converters 3 and 4 from the integration value of the integration circuit in a first period λ1.

  Next, the operation of the multi-bit ΔΣ modulator shown in FIGS. 1 and 2 will be briefly described. The odd numbered switches S1, S3, S5, S7, S9, S11 and the even numbered switches S2, S4, S6, S8, S10, S12 are alternately turned on at a predetermined first period λ1. In the integrating circuit composed of the switched capacitor circuit SC1, the differential amplifier circuit A1, and the capacitors CL1P and CL1N, an amount of charge corresponding to the voltages of the differential input signals VIP and VIN is sampled at the first period λ1 and sampled. The obtained charge amount is integrated, and differential signals V1P and V1N having voltages corresponding to the integrated value are output.

The voltages of the differential signals V1P and V1N are converted by the A / D converter 1 into n-bit digital signals D1 to Dn with a second period λ2 (= 2 ⁿ λ1). In other words, the A / D converter 1 outputs a sequence of digital signals D1 to Dn.

  Further, the digital signals D1 to Dn are converted by the feedback signal generation circuit 2 into the feedback signal FB having the first period λ2. The feedback signal FB is a binary signal having a pulse width corresponding to the values of the digital signals D1 to Dn. The feedback signal FB is converted into analog voltages V3 and V4 by 1-bit D / A converters 3 and 4. The switched capacitor circuit SC2 subtracts an amount of charge corresponding to the voltages V3 and V4 from the integration value of the integration circuit in the first period λ1. In this way, the voltages of the differential input signals VIP and VIN are converted into a sequence of digital signals D1 to Dn.

  Next, the effect of this Embodiment 1 is demonstrated. In a conventional multi-bit ΔΣ modulator, an integration operation is performed on an input voltage by an integrator, and an output voltage of the integrator is quantized by a subsequent multi-bit A / D converter. The output signal of the A / D converter is converted into an analog voltage by a multi-bit D / A converter and subtracted by an integrator. An error due to manufacturing variations also occurs in the A / D converter, but this error is subject to noise shaping in the ΔΣ modulator, moves to a high frequency band, and is consequently removed by a subsequent digital filter. However, the influence of manufacturing variations of the multi-bit D / A converter is not subject to noise shaping, and as a result, the S / N ratio is greatly reduced.

  On the other hand, in the first embodiment, the digital signals D1 to Dn generated by the A / D converter 1 are converted into binary feedback signals FB by the feedback signal generation circuit 2. The pulse width of the feedback signal FB changes according to the values of the digital signals D1 to Dn. The switched capacitor circuit SC2 is caused to subtract the value of the feedback signal FB from the integration value of the integration circuit. This operation is the same as subtracting the values of the data signals D1 to Dn converted into analog voltages by the multi-bit D / A converter from the integration result.

  Further, there is no multi-bit D / A converter corresponding to the resolution of the built-in A / D converter 1 which is a quantizer, and the feedback signal generation circuit 2 and the built-in D / A converters 3 and 4 having a resolution of 1 bit are provided. Because it is provided, it is not affected by manufacturing variations. As a result, there is an unprecedented remarkable effect that the resolution is not lowered due to the influence of the manufacturing variation regardless of the multi-bit ΔΣ modulator.

[Embodiment 2]
FIG. 3 is a block diagram showing the main part of the multi-bit ΔΣ modulator according to the second embodiment of the present invention, which is compared with FIG. Referring to FIG. 3, this multi-bit ΔΣ modulator is different from the multi-bit ΔΣ modulator of the first embodiment in that feedback signal generation circuit 2 is replaced with feedback signal generation circuit 15. The feedback signal generation circuit 15 includes an up counter 10, a down counter 16, a multiplexer 17, and a comparator 11.

  As described with reference to FIG. 2, the up counter 10 counts the number of pulses of the clock signal CLK having the first period λ1, and outputs n-bit count signals C1 to Cn indicating the count value. For example, when n = 2, the values of the count signals C1, C2 increase in synchronization with the clock signal CLK as 0, 1, 2, 3, 0, 1, 2, 3, 0,. Next to the maximum value is reset to 0 (minimum value or initial value).

  The down counter 16 counts the number of pulses of the clock signal CLK having the first period λ1, and outputs n-bit count signals C1 to Cn indicating the count value. For example, when n = 2, the values of the count signals C1, C2 decrease in synchronism with the clock signal CLK as 3, 2, 1, 0, 3, 2, 1, 0,. ) Is reset to 3 (maximum value or initial value).

  Output signals C 1 to Cn of the up counter 10 and the down counter 16 are given to the multiplexer 17. The multiplexer 17 selects and passes the output signals C1 to Cn of the up counter 10 when the switching signal φS is at “H” level, and the output signal of the down counter 16 when the switching signal φS is at “L” level. C1 to Cn are selected and passed. For example, switching signal φS is alternately set to the “H” level and the “L” level in a cycle that is an even multiple of second cycle λ2.

  The comparator 11 compares the values of the digital signals D1 to Dn from the A / D converter 1 with the values of the count signals C1 to Cn that have passed through the multiplexer 17, and uses a signal indicating the comparison result as a feedback signal FB. Output.

  When the values of the digital signals D1 to Dn are larger than the values of the count signals C1 to Cn, the feedback signal FB is set to the “H” level, and the values of the digital signals D1 to Dn are less than or equal to the values of the count signals C1 to Cn The feedback signal FB is set to the “L” level.

  When the up counter 10 is selected, it is as described with reference to FIG. Here, a case where the down counter 16 is selected will be described. For example, when the values of the digital signals D1 and D2 are 0, the values of the count signals C1 and C2 sequentially change to 3, 2, 1, 0 in the first period λ1, and the feedback signal FB has the second period λ2. It is set to “L” level during the whole period. When the values of the digital signals D1 and D2 are 1, the feedback signal FB is set to the “L” level during the first 3/4 period of the second period λ2, and is set to “H” only during the subsequent 1/4 period. To the level.

  When the values of the digital signals D1 and D2 are 2, the feedback signal FB is set to the “L” level during the first ½ period of the second period λ2, and “H” during the subsequent ½ period. To the level. When the values of the digital signals D1 and D2 are 3, the feedback signal FB is set to the “L” level only for the first quarter period of the second period λ2, and the subsequent 3/4 period is “H”. To the level.

  Since other configurations and operations are the same as those in the first embodiment, description thereof will not be repeated. Also in this second embodiment, the same effect as in the first embodiment can be obtained.

[Embodiment 3]
FIG. 4 is a block diagram showing the main part of the multi-bit ΔΣ modulator according to the third embodiment of the present invention, which is compared with FIG. Referring to FIG. 4, this multibit ΔΣ modulator is different from the multibit ΔΣ modulator of the first embodiment in that feedback signal generation circuit 2 is replaced with feedback signal generation circuit 20. The feedback signal generation circuit 20 includes DFFs 21 and 22 and an adder 23.

  The DFF 21 captures the n-bit digital signals D1 to Dn generated by the A / D converter 1 in the first period λ1, and holds and outputs the captured digital signals D1 to Dn. The DFF 22 captures the n-bit digital signal output from the adder 23 in the first period λ1, and holds and outputs the captured digital signal.

  The adder 23 adds the n-bit digital signals D1 to Dn output from the DFF 21 and the n-bit digital signal output from the DFF 22, and outputs an n-bit digital signal to the DFF 22 as an addition result. A 1-bit carry-out signal is output as a feedback signal FB. The length of time during which the feedback signal FB is at the “H” level in the second period λ2 indicates the values of the digital signals D1 to Dn, and becomes shorter as the values of the digital signals D1 to Dn are smaller. The larger the value, the longer. Therefore, as a result, the feedback signal generation circuit 20 performs the same operation as the primary digital ΔΣ modulator.

  Since other configurations and operations are the same as those in the first embodiment, description thereof will not be repeated. In the third embodiment, the same effect as in the first and second embodiments can be obtained. In the third embodiment, the circuit scale can be reduced as compared with the first and second embodiments, and a highly accurate feedback signal FB can be generated.

[Embodiment 4]
FIG. 5 is a circuit block diagram showing the configuration of the multi-bit ΔΣ modulator according to the fourth embodiment of the present invention, which is compared with FIG. Referring to FIG. 5, this multibit ΔΣ modulator is different from the multibit ΔΣ modulator of the first embodiment in that another stage of integration is provided between differential amplifier circuit A 1 and A / D converter 1. This is a point where a circuit is inserted. This integrating circuit includes a switched capacitor circuit SC3, a differential amplifier circuit A2, and capacitors CL2P and CL2N. Switched capacitor circuit SC3 includes switches S21 to S28 and capacitors CS3P and CS3N.

  The switch S21, the capacitor CS3P, and the switch S24 are connected in series between the non-inverting output terminal of the differential amplifier circuit A1 and the inverting input terminal (−input terminal) of the differential amplifier circuit A2. One terminal of switch S22 is connected to a node between switch S21 and one electrode of capacitor CS3P, and the other terminal of switch S22 receives reference voltage AGND. One terminal of switch S23 is connected to a node between the other electrode of capacitor CS3P and switch S24, and the other terminal of switch S23 receives reference voltage AGND.

  Similarly, the switch S25, the capacitor CS3N, and the switch S28 are connected in series between the inverting output terminal of the differential amplifier circuit A1 and the non-inverting input terminal (+ input terminal) of the differential amplifier circuit A2. One terminal of switch S26 is connected to a node between switch S25 and one electrode of capacitor CS3N, and the other terminal of switch S26 receives reference voltage AGND. One terminal of switch S27 is connected to a node between the other electrode of capacitor CS3N and switch S28, and the other terminal of switch S27 receives reference voltage AGND.

  The capacitor CL2P is connected between the inverting input terminal and the non-inverting output terminal of the differential amplifier circuit A2. The capacitor CL2N is connected between the non-inverting input terminal and the inverting output terminal of the differential amplifier circuit A2.

  Of the switches S21 to S28, the odd-numbered switches S21, S23, S25, and S27 and the even-numbered switches S22, S24, S26, and S28 are alternately turned on in the first period λ1. The switches S21, S23, S25, S27 are turned on / off together with the switches S1, S3, S5, S7, S9, S11. The switches S22, S24, S26, S28 are turned on / off together with the switches S2, S4, S6, S8, S10, S12.

  When the odd numbered switches S21, S23, S25, and S27 are turned on, the capacitors CS3P and CS3N are charged to the voltages of the differential output signals V1P and V1N of the differential amplifier circuit A1, respectively, and the capacitors CS3P and CS3N are different from each other. An amount of electric charge corresponding to the voltages of the motion signals V1P and V1N is stored.

  Next, when the even-numbered switches S22, S24, S26, and S28 are turned on, the charges stored in the capacitors CS3P and CS3N are transferred to the capacitors CL2P and CL2N, respectively. The differential amplifier circuit A2 outputs differential signals V2P and V2N having levels corresponding to the voltages across the terminals of the capacitors CL2P and CL2N, respectively.

  That is, switched capacitor circuit SC3, differential amplifier circuit A2, and capacitors CL2P and CL2N constitute an integrating circuit. This integrating circuit samples the amount of charge corresponding to the voltages of the differential input signals V1P and V1N at the first period λ1, integrates the sampled amount of charge, and voltage differential signals V2P, V2P, V2N is output.

  The A / D converter 1 converts the difference voltage between the differential signals V2P and V2N into n-bit digital signals D1 to Dn in the second period λ2. Since other configurations and operations are the same as those in the first embodiment, description thereof will not be repeated.

  In the fourth embodiment, since a two-stage integration circuit is provided, a second-order multi-bit ΔΣ modulator is obtained, so that noise shaping capability is improved and resolution can be improved.

  In the fourth embodiment, two stages of integration circuits are provided, but three or more stages of integration circuits may be provided.

[Embodiment 5]
FIG. 6 is a block diagram showing a configuration of a multi-bit ΔΣ A / D converter according to the fifth embodiment of the present invention. In FIG. 6, the multi-bit ΔΣ A / D converter includes a multi-bit ΔΣ modulator 25 and a digital filter 26.

  The multi-bit ΔΣ modulator 25 is shown in any one of the first to fourth embodiments (for example, 4), and the differential input signals VIP and VIN are arranged in a sequence of digital signals D1 to Dn. Convert. The digital filter 26 removes high-frequency noise from the column of the digital signals D1 to Dn, further converts the digital signal into a digital code having a desired resolution, and outputs the digital code.

  FIG. 6 is a block diagram illustrating the configuration of the digital filter 26. In FIG. 6, the digital filter 26 includes a sinc filter of the order of the number obtained by adding 1 to the number of integration circuits in the multi-bit ΔΣ modulator 25. In FIG. 6, a third-order Sinc filter is shown. The sinc filter includes three stages of cumulative integrators 31 to 33, a decimator 34, and three stages of difference units 35 to 36 that are cascode-connected. Each of the accumulators 31 to 33, the decimator 34, and the differentiators 35 to 36 operates in synchronization with the clock signal MCLK having the second period λ2. The sequence of digital signals D1 to Dn is supplied to the first-stage cumulative integrator 31.

  Each of the accumulators 31 to 33 includes an adder and a DFF array, accumulates and adds the input digital signals D1 to Dn, and outputs them to the next stage. The decimator 34 thins out the digital signal from the cumulative integrator 33 to 1 / M. M is 16, for example. Each of the subtractors 35 to 37 includes a DFF array and a subtracter, and subtracts the previous digital signal from the current digital signal and outputs the result to the next stage. Thereby, high frequency noise can be removed from the sequence of digital signals D1 to Dn, and further converted into a digital code with a desired resolution and output.

  Since other configurations and operations are the same as those in the first embodiment, description thereof will not be repeated. In the fifth embodiment, the same effect as in the first to fourth embodiments can be obtained.

  In the fifth embodiment, the case where the digital filter 26 is configured as a sinc filter has been described. However, the present invention is not limited to this, and the digital filter 26 may be a FIR (Finit-duration Impulse Response) filter, An IIR (Infinite-duration Impulse Response) filter may be used.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 A / D converter, 2, 15, 20 Feedback signal generation circuit, 3, 4 D / A converter, 10 up counter, 11 comparator, 16 down counter, 17 multiplexer, 21, 22 DFF, 23 adder, 25 Multi-bit ΔΣ modulator, 26 Digital filter, 31-33 Cumulative integrator, 34 Decimator, 35-36 Differential, A1, A2 Differential amplifier, CL1P, CL1N, CL2P, CL2N, CS1P, CS1N, CS2P, CS2N , CS3P, CS3N capacitors, S1-S12, S21-S28 switches, SC1-SC3 switched capacitor circuits, TIP, TIN input terminals.

Claims (6)

A multi-bit ΔΣ modulator that converts an analog input signal into a digital signal sequence of n bits (where n is an integer of 2 or more),
A first integration circuit that samples an amount of charge according to the voltage of the analog input signal in a first period, integrates the sampled charge amount, and outputs a signal of a voltage according to an integration value;
An A / D converter that converts the voltage of the output signal of the first integration circuit into an n-bit digital signal and outputs it in a second period that is 2 ⁿ times the first period;
A feedback signal generation circuit that converts the digital signal generated by the A / D converter into a binary feedback signal;
The feedback signal is set to a first or second logic level in the first period;
The time during which the feedback signal becomes the first logic level in the second period indicates the value of the digital signal,
A 1-bit D / A converter for converting the logic level of the feedback signal into a voltage in the first period;
A multi-bit ΔΣ modulator comprising: a subtracting circuit that subtracts an amount of electric charge corresponding to the voltage generated by the D / A converter from an integrated value of the first integrating circuit in the first period. The feedback signal generation circuit includes:
A counter that counts the number of pulses of the clock signal in the first period, outputs an n-bit count signal indicating the count value, and is reset in the second period;
The multi-bit ΔΣ modulator according to claim 1, further comprising a comparator that compares the value of the digital signal with the value of the count signal and outputs a signal indicating a comparison result as the feedback signal. The feedback signal generation circuit includes:
An up-counter that counts the number of pulses of the clock signal in the first period, outputs an n-bit up-count signal indicating the count value, and is reset in the second period;
A down counter that counts the number of pulses of the clock signal in the first period, outputs an n-bit down count signal indicating the count value, and is reset in the second period;
A multiplexer that selects one of the up-count signal and the down-count signal;
A comparator that compares the value of the digital signal with the value of the up-count signal or the down-count signal selected by the multiplexer and outputs a signal indicating a comparison result as the feedback signal. The multi-bit ΔΣ modulator according to 1. The feedback signal generation circuit includes first and second signal holding circuits and an adder,
The first signal holding circuit captures the n-bit digital signal generated by the A / D converter in the first period, holds and outputs the captured digital signal,
The second signal holding circuit captures the n-bit digital signal output from the adder in the first period, holds and outputs the captured digital signal,
The adder adds n-bit digital signals output from the first and second signal holding circuits and outputs the sum to the second signal holding circuit, and outputs a carry-out signal as the feedback signal. The multi-bit ΔΣ modulator according to claim 1. Furthermore, the charge is inserted between the first integration circuit and the A / D converter, and an amount of charge corresponding to the voltage of the output signal of the first integration circuit is sampled in the first period, A second integration circuit that integrates the sampled charge amount and outputs a voltage signal corresponding to the integration value;
5. The A / D converter according to claim 1, wherein the A / D converter converts a voltage of an output signal of the second integration circuit into an n-bit digital signal in the second period and outputs the n-bit digital signal. The multi-bit ΔΣ modulator according to item. A multi-bit ΔΣ modulator according to any one of claims 1 to 5,
A multi-bit A / D converter comprising a digital filter that removes noise from the digital signal sequence output from the multi-bit ΔΣ modulator and converts the digital signal into a digital code.

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