JPS6217105B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a measuring device for automobile control. As an example of a measuring device for automobile control, a technology for measuring engine rotational speed by counting pulses synchronized with engine rotation is disclosed in US Patent No.
It is disclosed in No. 3744854, No. 3757167, and No. 3885137. In the conventional measurement method, a counter for counting pulses and a counter for measuring the measurement time of the pulses are provided as completely independent circuits. For this reason, when circuits are integrated, the chip area becomes extremely large. SUMMARY OF THE INVENTION An object of the present invention is to provide a measuring device for automobile control having a pulse counting circuit that can be integrated into a small chip area. In the present invention, the time measurement counter for measuring pulse measurement time and the rotation synchronous pulse counter for counting rotation synchronous pulses have a first counter that holds the count value of the time measurement counter and the count value of the rotation synchronous pulse counter, respectively. a second count value holding circuit; an incrementer that increases the value of the input data by 1 based on the increment signal; and further sets the value of the input data to zero based on the reset signal; and the first and second counters. The count values respectively held in the numerical value holding circuits are selectively added to the incrementer as input data based on time pulses generated at a predetermined time period, and the output of the incrementer is held as the first and second count values. The present invention is characterized in that it is comprised of a selection circuit that re-inputs each to the circuit, and an increment controller that applies an increment signal to the incrementer in synchronization with the operation of the selection circuit based on the generation of the rotation synchronization pulse and the clock pulse. . This reduces the chip area required for the integration of the time measuring counter and the rotationally synchronous pulse counter. Now, FIG. 1 is a block diagram showing the main structure of a comprehensive control system for an automobile engine. The flow rate of the air taken in through the air cleaner 12 is measured by an air flow meter, and an output QA representing the air flow rate is input from the air flow meter 14 to the control circuit 10. The air flow meter 14 is provided with an intake temperature sensor 16 for detecting the temperature of intake air, and an output TA representing the temperature of the intake air is input to the control circuit 10. The air that has passed through the air flow meter 14 passes through the throttle chamber 18 and is then
The air is drawn into the combustion chamber 34 of the engine 30 from the manifold 26 via the intake valve 32. The amount of air drawn into the combustion chamber 34 is controlled by varying the opening degree of a throttle valve 20 located within the throttle chamber in mechanical conjunction with the accelerator pedal 22. The opening degree of the throttle valve 20 is determined by detecting the position of the throttle valve 20 by the throttle position detector 24, and the signal QTH representing the position of the throttle valve 20 is detected by the throttle position detector 24.
4 to the control circuit 10. The throttle chamber 18 is provided with an idle bypass passage 42 and an idle adjust screw 44 for adjusting the amount of air passing through the bypass passage 42. When the engine is operating in an idling state, the throttle valve 20 is in a fully closed position. air flow
Intake air from meter 14 flows through bypass passage 42 and is drawn into combustion chamber 34 . Therefore, the amount of intake air during idling operation can be changed by adjusting the idle adjust screw. The energy generated in the combustion chamber is almost determined by the amount of air flowing from the bypass passage 42, so by adjusting the idle adjust screw 44 and changing the amount of air taken into the engine, the engine rotation speed during idling can be adjusted to an appropriate level. can be adjusted to a suitable value. The throttle chamber 18 is further provided with a further bypass passage 46 and an air regulator 48. Air regulator 48 is control circuit 1
The amount of air passing through the passage 46 is controlled in accordance with the output signal NIDL of zero, and the engine speed is controlled during warm-up operation and an appropriate amount of air is supplied to the engine when the throttle valve 20 suddenly changes. Additionally, the air flow rate during idling operation can be changed as necessary. Next, the fuel supply system will be explained. The fuel stored in the fuel tank 50 is sucked into the fuel pump 52 and pumped to the fuel damper 54. The fuel damper 54 absorbs pressure pulsations in the fuel from the fuel pump 52 and sends fuel at a predetermined pressure to the fuel pressure regulator 62 via the fuel filter 56. Fuel from the fuel pressure regulator is fed under pressure to a fuel injector 66 via a fuel pipe 60, and the fuel injector 66 is opened by the output INJ from the control circuit 10 to inject fuel. The amount of fuel injected from the fuel injector 66 is determined by the valve opening time of the injector 66 and the pressure difference between the pressure of the fuel fed to the injector and the pressure of the intake manifold 26 into which the fuel is injected. However, it is desirable that the fuel injection rate from the fuel injector 66 is dependent only on the valve opening time determined by the signal from the control circuit 10. Therefore, the pressure of the fuel fed to the fuel injector 66 is controlled by the fuel pressure regulator 62 so that the difference between the fuel pressure to the fuel injector 66 and the manifold pressure of the intake manifold 26 is always constant. Intake manifold pressure is applied to the fuel pressure regulator 62 via a conductive pipe 64, and when the fuel pressure in the fuel pipe 60 exceeds a certain level with respect to this pressure, the fuel pipe 6
0 and the fuel return pipe 58 are in communication with each other, and the fuel corresponding to the excess pressure is transferred to the fuel tank 50 via the fuel return pipe 58.
be returned to. In this way, the difference between the fuel pressure in the fuel pipe 60 and the manifold pressure in the intake manifold is always kept constant. The fuel tank 50 is further provided with a pipe 68 and a canister 70 for absorbing vaporized fuel gas, and an atmosphere opening 7 is provided during engine operation.
4, and the absorbed vaporized fuel gas is guided to the intake manifold through a pipe 72 and then to the engine 30. As explained above, fuel is injected from the fuel injector, and the intake valve 32 is connected to the piston 74.
The combustion chamber 34 opens in synchronization with the movement of the combustion chamber 34, and a mixture of air and fuel is introduced into the combustion chamber 34. This mixture is compressed,
By combusting the air-fuel mixture with spark energy from the spark plug 36, the combustion energy of the air-fuel mixture is converted into kinetic energy that moves the piston. The combusted air-fuel mixture is exhausted as exhaust gas from an exhaust valve (not shown) to the atmosphere via an exhaust pipe 76, a catalytic converter 82, and a muffler 86. exhaust pipe 76
is the exhaust gas recirculation pipe 78 (hereinafter referred to as EGR pipe).
A portion of the exhaust gas is guided to the intake manifold 26 through this pipe. That is, part of the exhaust gas is recirculated to the intake side of the engine. This recirculation amount is determined by the valve opening amount of the exhaust gas recirculation device 28. This valve opening amount is the output of the control circuit 10.
Controlled by EGR and further exhaust gas recirculation device 28
The valve position is converted into an electrical signal and input to the control circuit 10 as a signal QE. A λ sensor 80 is provided in the exhaust pipe 76 and detects the mixture ratio of the air-fuel mixture sucked into the combustion chamber 34. Specifically O ₂ sensor (oxygen sensor)
is generally used to detect the oxygen concentration in the exhaust gas and generate a voltage Vλ according to the oxygen concentration. The output Vλ of the λ sensor 80 is input to the control circuit 10. The catalytic converter 82 is provided with an exhaust temperature sensor 84, and an output TE corresponding to the exhaust temperature is input to the control circuit 10. The control circuit 10 is provided with a negative power terminal 88 and a positive power terminal 90. Further, the control circuit 10 applies the above-described signal IGN to the primary coil of the ignition coil 40 to control the spark generation of the ignition plug 36, and the high voltage generated in the secondary coil is passed through the power distributor 38 to the ignition plug 36. is applied to generate sparks for combustion within the combustion chamber 34. More specifically, the ignition coil 40 is provided with a positive power supply terminal 92, and the control circuit 10 is further provided with the ignition coil 40.
A power transistor is provided for controlling the primary coil current of zero. A series circuit of the primary coil of the ignition coil 40 and the power transistor is formed between the positive power supply terminal 92 of the ignition coil 40 and the negative power supply terminal 88 of the control circuit 10, and when the power transistor becomes conductive, ignition is started. Electromagnetic energy is stored in the coil 40, and when the power transistor is cut off, the electromagnetic energy is converted into energy having a high voltage and sent to the spark plug 36.
applied to. The engine 30 is provided with a water temperature sensor 96,
The temperature of engine cooling water 94 is detected, and a signal TW corresponding to this temperature is input to control circuit 10. Further, the engine 30 is provided with an angle sensor 98 that detects the rotational position of the engine, and this sensor 98 generates a reference signal PR every 120 degrees, for example, in synchronization with the rotation of the engine. degree) Angle signal every time it rotates
Generate PC. These signals are input to the control circuit 10. A negative pressure sensor may be used in place of the air flow meter 14 in FIG. A negative pressure sensor 100 indicated by a dotted line in the figure inputs a voltage VD corresponding to the negative pressure of the intake manifold 26 to the control circuit 10. Specifically, a semiconductor negative pressure sensor can be considered as the negative pressure sensor 10. The boost pressure of the intake manifold is applied to one side of the silicon chip, and atmospheric pressure or constant pressure is applied to the other side.
In some cases, a vacuum may be used. With such a structure, a voltage VD corresponding to the manifold pressure is generated due to the piezoresistance effect, etc., and is applied to the control circuit 10. FIG. 2 is an operational diagram illustrating the ignition timing and fuel injection timing with respect to the crank angle of a six-cylinder engine. A represents the crank angle, and a reference signal PR is output from the angle sensor 98 every 120 degrees of crank angle. In other words, the crank angle is 0.
The reality signal PR is input to the control circuit 10 at every angle of 120°, 240°, 360°, 480°, 600°, and 720°. In the figure, B, C, D, H, H, and G are the first cylinders, respectively.
5th cylinder, 3rd cylinder, 6th cylinder, 2nd cylinder, 4th cylinder
Represents the operation of the cylinder. Further, J1-J6 represent the opening positions of the intake valves of each cylinder. As shown in Fig. 2, the valve opening positions of each cylinder are shifted by 120° in terms of crank angle. Although the valve opening position and valve opening width differ somewhat depending on the structure of each engine, they are approximately as shown in the figure. In the diagram, A1 to A5 are fuel injectors 6
6 represents the valve opening time, that is, the fuel injection timing.
The time width JD of each injection period A1 to A5 represents the opening time of the fuel injector 66. This time width JD can be considered to represent the fuel injection amount of the fuel injector 66. A fuel injector 66 is provided corresponding to each cylinder, and these injectors are each connected in parallel to a drive circuit within the control circuit 10. Therefore, in response to the signal INJ from the control circuit 10, the fuel injectors corresponding to each cylinder open simultaneously and inject fuel. The first cylinder shown in FIG. 2B will be explained. crank angle 360
In synchronization with the reference signal INTIS generated at
is applied to the injector 66. As a result, fuel is injected for the time JD calculated by the control circuit 10 as shown by A2. However, since the intake valve of the first cylinder is closed, the injected fuel is held near the intake port of the first cylinder and is not sucked into the cylinder. Next, a signal is again sent from the control circuit to each fuel injector 66 in response to the reference signal INTIS generated at a crank angle of 720 degrees, and fuel injection indicated by A3 is performed. Almost simultaneously with this injection, the intake valve of the first cylinder opens, and with this opening, both the fuel injected at A2 and the fuel injected at A3 are sucked into the combustion chamber. The same can be said for other cylinders.
That is, in the fifth cylinder shown in C, the fuel injected at A2 and A3 is taken in at the opening position J5 of the intake valve. In the third cylinder shown in D, the intake valve is at the opening position J3.
A part of the fuel injected at A2, a part of the fuel injected at A3, and a part of the fuel injected at A4 are inhaled. The sum of the part of the fuel injected at A2 and the part of the fuel injected at A4 becomes the injection amount for one injection. Therefore, in each intake stroke of the third cylinder, two injection amounts are taken in, respectively.
The 6th, 2nd, and 4th cylinders shown in E, H, and G similarly inhale two injections from the fuel injector in one intake stroke. As can be seen from the above explanation, the fuel injection amount specified by the fuel injection signal INJ from the control circuit 10 is half of the fuel required for intake, and the fuel injector 66
The required amount of fuel corresponding to the air taken into the combustion chamber 34 can be obtained by one injection. In FIG. 2, G1 to G6 indicate ignition timings corresponding to the first to sixth cylinders. By cutting off the power transistor provided in the control circuit 10, the primary coil current of the ignition coil 40 is cut off.
Next, a high voltage is generated in the coil. This high voltage is generated at the ignition timings G1, G5, G6, G2, and G4, and is distributed by the power distributor 38 to the spark plugs provided in each cylinder. As a result, each spark plug is ignited in the order of the first cylinder, the fifth cylinder, the third cylinder, the sixth cylinder, the second cylinder, and the fourth cylinder, and the mixture of fuel and air is combusted. The detailed circuit configuration of the control circuit 10 in FIG.
As shown in the figure. A positive power supply terminal 90 of the control circuit 10 is connected to a positive terminal 110 of the battery, and a voltage VB is supplied to the control circuit 10. The power supply voltage VB is set to a constant voltage PVCC, for example, 5 [V] by the constant voltage circuit 112.
is held constant. This constant voltage PVCC is supplied to a central processor (hereinafter referred to as CPU), random access memory (hereinafter referred to as RAM), and read-only memory (hereinafter referred to as ROM).
Furthermore, the output PVCC of the constant voltage circuit 112 is also input to the input/output circuit 120. The input/output circuit 120 includes a multiplexer 122, an analog/digital converter (hereinafter referred to as an A/D converter) 124, a pulse output circuit 126, a pulse input circuit 128, and a discrete input/output circuit 130.
etc. Analog signals are input to the multiplexer 122 , and one of the input signals is selected based on a command from the CPU 114 and input to the A/D converter 124 . As analog input signals, each sensor shown in FIG.
The air flow meter QA outputs an analog signal TW representing the engine cooling water temperature, an analog signal TA representing the intake air temperature, an analog signal TE representing the exhaust gas temperature, an analog signal QTH representing the throttle opening, and an analog signal representing the exhaust gas recirculation system. An analog signal QE representing the valve open state, an analog signal Vλ representing the excess air ratio of the intake mixture, and an analog signal QA representing the intake air amount are sent to the filters 132 to 144.
is input to multiplexer 122 via. However, the output Vλ of the λ sensor 80 is input to the multiplexer via an amplifier 142 having a filter circuit. In addition, an analog signal VPA representing atmospheric pressure is input from the atmospheric pressure sensor 146 to the multiplexer. Also, from the positive power supply terminal 90, resistors 150, 15
The voltage VB is supplied to the 2,154 series circuits through a resistor 160, and the terminal voltage of the series circuit of the resistors is kept constant by a Zener 148. Voltage VH at connection points 156 and 158 of resistors 150 and 152 and resistors 152 and 154, respectively.
and VL are input to the multiplexer 122. CPU114, RAM116, and ROM1 mentioned above
18 and the input/output circuit 120 are connected by a data bus 162, an address bus 164, and a control bus 166, respectively. Furthermore, from the CPU 114, RAM 116, ROM 118, input/output circuit 120
A clock signal E is applied to each of them, and data is transmitted via the data bus 162 in synchronization with the clock signal E. The multiplexer 122 of the input/output circuit 120 has water temperature TW, intake air temperature TA, exhaust gas temperature TE, throttle opening QTH, exhaust recirculation amount QE, λ sensor output Vλ, atmospheric pressure VPA, intake air amount QA, reference voltage VH, Negative pressure VD is input instead of VL and intake air amount QA. These inputs are in ROM11
Based on the instruction program stored in 8.
The address of the CPU 114 is specified via the address bus, and the analog input of the specified address is taken in. This analog input is sent from the multiplexer 122 to the A/D converter 124, and the digitally converted value is held in a register corresponding to each input, and is sent to the CPU 114 via the control bus 166 as necessary.
CPU114 or RAM11 based on instructions from
6. A reference pulse PR and an angle signal PC are input from the angle sensor 98 to the pulse input circuit 128 in the form of a pulse train via a filter 168.
Further, a pulse PS having a frequency corresponding to the vehicle speed is input from the vehicle speed sensor 170 to the pulse input circuit 128 via the filter 172 in the form of a pulse train. The signal processed by CPU 114 is held in pulse output circuit 126. Pulse output circuit 12
The output from 6 is applied to a power amplifier circuit 188, and the fuel injector is controlled based on this signal. Reference numerals 188, 194, and 198 are power amplification circuits that control the primary coil current of the ignition coil 40, the opening degree of the exhaust gas recirculation device 28, and the air regulator 4, respectively.
8 is controlled according to the output pulse from the pulse output circuit 126. The discrete input/output circuit 130 receives signals from a switch 174 that detects that the throttle valve 20 is fully closed, a starter switch 176, and a gear switch 178 that indicates that the transmission gear is the top gear. 182, 18
4 and hold it. Furthermore, it holds processing signals from the central processor CPU 114. The signals related to the discrete input/output circuit 130 are signals whose contents can be displayed with one bit. Next, the power amplifier circuits 196, 200,
Signals are sent from the discrete input/output circuit to 202 and 204, respectively, and the exhaust gas recirculation device 28
closes to stop exhaust gas recirculation, controls the fuel pump, indicates abnormal catalyst temperature, and indicates engine overheating. FIG. 4 shows a specific circuit of the pulse output circuit 126, and a register group 470 is a reference register group, which holds data processed by the CPU 114 or data indicating a predetermined constant value. hold. This data is sent from CPU 114 via data bus 162. The register to be held is specified via the address bus 164, and the above data is input to the specified register and held. The register group 472 is a momentary register group and holds the instantaneous state of the engine and the like. Instantaneous register group 472, latch circuit 476, and incrementer 4
78 exhibits a so-called counter function. The output register group 474 includes, for example, a register 430 that holds the rotational speed of the engine and a register 432 that holds the vehicle speed. These values are obtained by reading the values of instantaneous registers when certain conditions are met. Output register group 47
The data held in CPU 114 is sent to a related register by a signal sent from CPU 114 via address bus 164, and is sent from this register to CPU 114 via data bus 162. Comparator 480 receives reference data from a selected register of the group of reference registers and instantaneous data from a selected register of the group of instantaneous registers at inputs 482 and 484, respectively, and performs a comparison operation. The comparison result is output from the output terminal 486. The output terminal is set in a predetermined register in the first comparison output register group 502 which functions as a comparison result holding circuit. Furthermore, it is then set in a predetermined register of the second comparison output register group 504. Reference register group 470, instantaneous register group 47
2. Read and write operations of the output register group 474, incrementer 478 and comparator 480
The operations of setting the output to the first comparison output register 502 and the second comparison output register 504 are processed within a certain predetermined time. Further, various processes are performed in a time-sharing manner according to the stage order of the stage counter 572. For each stage, a predetermined register in each of the reference register group 470, instantaneous register group 472, first and second comparison result register groups, and, if necessary, a predetermined register in the output register group 474 is selected. . Also, incrementer 478 and comparator 4
80 is commonly used. FIG. 5 is a diagram for explaining the timing of FIG. 4. A clock signal E is supplied from the CPU 114 to the input/output circuit 120. This signal is shown in A. From this clock signal E, a circuit 574 generates two non-overlapping clock signals φ1 and φ2. This signal is shown in (b) and (c). The circuit shown in FIG. 4 operates according to these clock signals φ1 and φ2. FIG. 5D is a stage signal, which is switched at the rising edge of clock signal φ2, and processing of each stage is performed in synchronization with φ2. In Figure 5
THROUGH indicates that the latch circuit or register circuit is enabled, and indicates that the output of these circuits is dependent on the input. Also
LATCH indicates that these circuits hold certain data and the output of this circuit does not depend on the input. The stage signal shown in (d) becomes a readout signal for the reference register 470 and instantaneous register 472, and the contents are read out from a certain selected predetermined register. E and F show the operation of reference register 470 and instantaneous register 472, respectively. This operation is performed in synchronization with the clock φ. The operation of latch circuit 476 is shown in FIG. This circuit enters the THROUGH state when φ2 is at a high level, writes data in a specific register read from the instantaneous register group 472, and clocks φ2.
When 2 becomes low level, it becomes LATCH state. In this way, the data of a predetermined register in the instantaneous register group corresponding to that stage is held. The data held in the latch circuit 476 is
Incrementer 478 not synchronized to clock signal
modified based on external conditions. Here, the incrementer 478 has the following functions based on the signal from the incrementer controller 490. The first function is an increment function that increases the value indicated by the input data by one. Second
The function is a non-increment function, which allows the input to pass through without increasing it. The third function is a reset function, which changes all inputs to data indicating a value of 0. Looking at the data flow of the instantaneous registers, one register in the instantaneous register group 472 is selected by the stage counter 572, and its held data is input to the comparator 480 via the latch circuit 476 and the incrementer 478. Additionally, a closed loop is created from the output of incrementer 478 back to the originally selected register. Therefore, when the incrementer functions to increase data by one, this closed loop functions as a counter. However, in this closed loop, if a situation occurs in which the data of the instantaneous register group is output from a specific selected register while the data is looped around and input, malfunction occurs. Therefore, a latch circuit 476 is provided to cut off the data. The latch circuit 476 enters the THROUGH state in synchronization with clock φ2, while the THUOUGH state in which the input is written to the instantaneous register is synchronized with clock φ1. Therefore, data is cut between clocks φ2 and φ1. In other words, even if the value of a specific register in the register 472 is changed, the latch circuit 47
The output of 6 remains unchanged. Comparator 480, like incrementer 476, also operates out of synchronization with the clock signal. The input of the comparator 480 is transmitted through a latch circuit and an incrementer for the data held in one reference register selected from the reference register group 470 and the data held in one register selected from the instantaneous register group. received data. The ratio result of this data is synchronized with clock signal φ1.
It is set to the first comparison result register group 502 which enters the THROUGH state. Furthermore, this data is set in the second comparison result register group 504 which enters the THROUGH state at clock φ2. The output of this register 504 becomes a signal for controlling each function of the incrementer, and a drive signal for the fuel injector, ignition coil, exhaust gas recirculation device, etc. Also, based on this signal, the measurement results of the engine rotational speed and vehicle speed at each stage are written from the instantaneous register group to the output register group 474.
Now, for example, when writing the engine rotation speed, the second signal indicating that a certain period of time has elapsed is
It is held in the comparison result register RPMWBF552,
At the RPM stage in Table 1, which will be described later, data held in the instantaneous register 462 is input to the register 430 of the output register group based on the output of this register 552. At this time, the second comparison result register
If the signal indicating that a certain period of time has elapsed is not held in the RPMWBF 552, the operation of inputting the data held in the register 462 to the register 430 is not performed even in the RPM stage. On the other hand, based on the signal held in the second comparison result register VSPWBF 556, data in the instantaneous register 468 is inputted to the output register 432 as data representing the vehicle speed at the timing of the stage VSP. Writing of data representing the engine rotational speed RPM and vehicle speed VSP to the output register group 474 is performed as follows. In FIG. 5, the stage signal STG is RPM or VSP, and the data in the instantaneous register 462 or 468 is at the high level of the clock φ2, and the latch circuit 476 is activated.
It becomes THROUGH state and is written, and the clock φ
2 becomes low level, the above data becomes
LATCHed. The data held in this way is stored in the register RPMWBF552 or
Based on the signal from the VSPWBF556, the output register group 474 enters the THROUGH state as shown in FIG.
be done. When the CPU 114 reads data held in the output register group 474, the CPU 114 specifies the register via the address bus 164, and the data is taken in in synchronization with the clock signal E shown in FIG. 5A. FIG. 6 shows a generation circuit for the stage signal STG. The stage counter SC570 is counted up by the signal φ1 from the circuit 574, and the outputs C0 to C6 of the stage counter SC570 and the output of the T register in FIG. 4 are input to the stage decoder SDC. The stage decoder SDC writes signals 01 to 017 as outputs to the stage latch circuit STGL in synchronization with the clock φ2. The stage latch STGL reset input has a fourth
When the ^20- bit signal GO of the MODE register shown in the figure is input and the ^20- bit GO signal of the MODE register becomes low level, all outputs of STGL become low level and all processing operations are stopped. On the other hand, when the GO signal becomes high level, the stage signal STG is outputted again in a fixed order, and processing is performed based on it. The above stage decoder SDC can be easily realized by using read-only memory or the like. The detailed contents of stages 00 to 6F of the stage signal STG, which is the output of the stage latch STGL, are shown in Table 1.

【table】

[Table] First, the general reset signal GR is input to the reset terminal of the stage counter SC570 shown in FIG. 6, so that the counter outputs C0 to C6 all become 0. This general reset signal is sent from the CPU when this control circuit is activated. When clock signal φ2 is input in this state, at the rising edge of φ2,
EGFP stage signal STG is output. EGRP processing is performed based on this stage signal. Next, the stage counter SC570 counts up by one at clock φ1, and INTL of the stage signal STG is output at clock φ2. This stage signal
INTL is output. This stage signal
INTL processing is performed based on INTLSTG. Next, the stage signal CYLSTG is output and CYL processing is performed, and then the stage signal
ADV is output and ADV processing is performed. When the stage counter SC570 continues to count up in synchronization with φ1 in this manner, a stage signal STG is output in synchronization with φ2, and processing is performed in accordance with this signal. When C0 to C6 of stage counter SC570 all become 1, stage signal INJSTG is output.
The INJ process is performed and all the processes in Table 1 are completed. With the next clock signal φ1, all C0 to C6 of the stage counter SC570 become 0, and with the clock signal φ2, the stage signal EGRPSTG is output, and STG processing is performed. In this way the first
Repeat table processing. Table 2 shows the processing contents of each stage shown in Table 1.

【table】

[Table] Output from the stage latch circuit STGL in Figure 6
The STG0 and STG7 signals are circuits for synchronizing the input input from the outside with the internal clock signal of the input/output circuit 120.
Output STG7 is the stage counter
It is output when C0 to C2 of SC570 are all 1. External signals include, for example, a reference signal PR generated in synchronization with engine rotation, an angle signal PC, and a vehicle speed pulse PS generated in synchronization with wheel rotation. The periods of these pulses change greatly, and as they are, they are not synchronized with the clock signals φ1 and φ2. Therefore, it is not possible to determine whether to increment at the ADVSTG stage, VSPSTG stage, or RPMSTG stage in Table 1. Therefore, it is necessary to synchronize external pulses, such as pulses from a sensor, with the stages of the input/output circuit. Furthermore, in order to improve detection accuracy, the angle signal PC and vehicle speed signal PS need to be synchronized with the stage with respect to the rise and fall of their input pulses. Reference signal PR
For this, it is sufficient to synchronize it with the rise. Output STG of stage latch circuit STGL in Figure 6
FIG. 7 shows a circuit that uses STG7 and STG7 to generate the synchronized signal at φ2 timing. Further, the operation timing is shown in FIG. External input pulses such as sensor output, such as reference pulse PR, angle signal PC, vehicle speed signal PS
are latched by the STG0 output shown in FIG. 6 to latch circuits 600, 602, and 604 shown in FIG. 7, respectively. In Figure 8, A is the clock signal φ2, B is the clock signal φ1, and C and D are the stage signals STG7 and STG.
It is 0. This stage signal is generated in synchronization with φ2, as explained in FIG. The signal shown in E is the output pulse from the angle sensor or vehicle speed sensor and is the reference pulse PR or angle pulse PC.
Alternatively, it indicates the vehicle speed pulse PS, and the generation timing, pulse duty, and period of this signal are irregular, and are inputted regardless of the stage signal. Now, a signal as shown in FIG.
Assuming that the pulses are input to 00, 602, and 604, they are latched by the stage signal STG0 (pulse shown in the figure). Therefore, as shown in FIG. 8, the level becomes high at the time point. Furthermore, since the input signals PR, PC, and PS are at high level in the stage signal STG0 indicated by wo, the latch circuits 600, 602, and 60
The high level is latched at 4. However, in the stage signal STG0 shown by w, the input signal PR,
Since PC and PS are at low level, low level is latched. Therefore, the latch circuit 600,6
The outputs A1, A2, and A3 of 02,604 are as shown in F. Latch circuit 606, 608, 610
outputs A1, A2, and A3 as stage signals, respectively.
It latches at STG7 force, so it starts up from the point indicated by yo. Furthermore, the stage signal STG7 also latches at a high level, so it continues to be at a high level. Therefore, the output signals B1, B2, and B3 of the latch circuits 606, 608, and 610 are as shown in FIG. The signal A1 and the signal B1 sent through the inverter 608 are input to the NOR circuit 612, and a synchronized reference signal PRS is generated as shown in FIG. This synchronized reference signal PRS catches the rising edge of the reference signal PR and has the pulse width of the stage signals STG0 to STG7. The EXCLUSIVELYOR circuits 614 and 616 receive signals A2 and B2, and signals A3 and B3, respectively, and the rising edge of the signals PC and PV generates the signal shown in (i), and the falling edge of the signals PC and PV generates the signal (g). do. The duty of signals R and G is the same as the duty shown in C, and the duty of the stage signal STG
Determined by 0 and STG7. In the above explanation, it was determined that the signals PR, PC, and PS were input at the same time with the same duty, but in reality, these signals are not input at the same time and their duties are different. Furthermore, even when looking at the same signal itself, its period and duty differ each time. However, due to FIG. 7 and the synchronization circuit, the pulse has a constant width. This pulse width is the stage signal STG
It is determined by the time difference between STG 0 and STG7. Therefore, latch circuits 600, 602, 604 and 606, 608, 6
By changing the stage signal applied to 10, the pulse width can be adjusted and changed. This pulse width is determined in relation to the timing of the stages in Table 1. In other words, as shown in Table 1, the INTL stage has a stage counter (C0~
C2, C3 to C6) are assigned in the state of (1, 0), and further (1, 1), (1, 2), (1, 3)
...and are assigned to each 8th stage. Since each stage is set to one microsec, an INTL stage is assigned every eight microsecs. In the INTL stage, it is necessary to detect the angle signal PC and control the incrementer, so when the output PC of the angle sensor 98 is applied to the synchronization circuit shown in FIG. Create such a synchronization pulse, and based on this synchronization pulse PCS
Control the incrementer controller in the INHL stage. This synchronized angle signal PCS is also detected in stages ADV and RPM. This stage ADV
The RPM is assigned each time the values of C3 to C6 count up by one when the stage counters C0 to C2 are at 3 and 6, respectively. The assigned stage rotates in a cycle of 8 microseconds. The STG0 signal in Figure 7 is the C of the stage counter.
Output when the value of 0 to C2 is 0, while STG7
is output when C0 to C2 have a value of 7. This output is produced independently of C3-C6. Therefore, the eighth
As can be seen from the figure, the synchronized angle signal PCS always has a varying pulse width from a value of 0 to a value of 6 for the stage counter outputs C0 to C2, and this pulse is detected by the stages INTLADV and RPM to control the incrementer controller. do. Detect synchronized correction PRS as above
CYL stage is stage counter output C0~C
When the reference pulse PR is input from the angle sensor 98, which is always assigned when the value of 2 is 2, the synchronized reference pulse PRS is always assigned to this input when the stage counter C0 to C2 is 2.
It is necessary for this to occur. The circuit in Figure 7 is STG
Since the pulse width is between 0 and STG7, this information is fully satisfied. Next, the VSP stage for detecting the wheel speed is assigned when the stage counter outputs C0 to C2 always have a value of 5. Therefore, it is sufficient that the synchronized PSS signal is output when the value of C0 to C2 is 5. In the circuit shown in FIG. 7, the values of C0 to C2 range from 0 to 6, so this value is satisfied. In figure 7
Instead of the STG0 signal, create a signal STG4 that always appears when the value of C0 to C2 is 4, and use this signal, and in addition to the signal STG7, a signal that always appears when the value of C0 to C2 is 6. STG6 may also be used. In this case, when the signal PS is input, the synchronization signal PSS is the output C0 of the stage counter
It will always be output when the value of C2 is 4 and 5. The stage cycle will now be explained.
In Table 1, stage counter outputs C0 to C6
128 types of stage signals with values from 0 to 127 are created, and when all of these signals have been generated, the large cycle is completed and a new large cycle begins again. This large cycle is further composed of 16 small cycles, and this small cycle is composed of 8 types of stage signals. This small cycle corresponds to the values of stage counter outputs C0 to C2 from 0 to 7, respectively, and is completed in 8 microseconds. The pulse outputs PR, PC, and PS from the sensor are reliably synchronized, and the synchronized pulses PRS, PCS, and PSS are
In order to reliably generate this, it is necessary that the output from the sensor has a pulse width longer than this short cycle. For example, the duty of the angular pulse becomes narrower as the engine rotates faster. For example, at 9000 rpm, it will be about 9 microseconds. Therefore, in order to achieve sufficient synchronization with respect to 9000 revolutions per minute, it is necessary to make this small cycle shorter than this, and in this embodiment it is 8 microseconds. Next, the operation of incrementer 478 shown in FIG. 4 will be explained. A detailed circuit of incrementer 478 is shown in FIG. As mentioned above, this incrementer has three functions: the first function is to increase the input data by a value of 1, the second function is to reset the input data, and the third function is to increase the input data by a value of 1. The function is a function that outputs input data as is. The increment function is performed by the ICNT signal, and the reset function is performed by the IRST signal.
When ICNT signal is high level, increment function, when low level, non-increment function,
When the IRST signal is high level, it becomes a reset function and the IRST signal has priority over the ICNT signal. The conditions may be selected based on the stage signals commanded by each process. The conditions include synchronized external input and the register group 504 of the second comparison result.
This is the output of Further, the conditions for transferring and writing data to the output register 474 are also similar to the conditions for the incrementer. FIG. 10 is a diagram explaining the processing of the fuel injection signal INJ. Since the start of injection differs depending on the number of cylinders, a register 442 acting as a CYL counter counts the initial angular pulse INTLD generated from the reference signal PRS, and stores the result as a value related to the number of cylinders. CYL
CYL of the first group of registers 502 when compared with register 404 and is greater than or equal to
FF 506 is set to 1, and CYLBF 508 of the second register group 504 is set to 1.
When CYL BF=1, the CYL counter 442 is reset. Also, when CYL BF=1, the INJ timer 450 that measures the injection time is reset. It is always unconditionally incremented by time, and when it is compared with the INJD register 412 in which the injection time is set, when it is greater than or equal,
1 is set in INJ FF 522 of the first register group. Also, INJ BF52 of the second register group
4 is set to 1. When INJ BF=1, increment by time is prohibited. this
The reverse output of INJ BF becomes the fuel injection time width,
This is the fuel injector valve opening time. FIG. 11 is a diagram illustrating processing of signals that control ignition. By the initial angular pulse INTLD,
The register 452, which acts as an ADV counter, is reset and incremented by the synchronized angle pulse PC being high.
Then, it is compared with the ADV register 414 that holds the ignition angle from INTLD, and if the angle is greater than or equal, the ADV of the first register 502 is
The FF 526 is set to 1, and the ADV BF 528 of the second register 504 is set to 1. With ADVD indicating the rise of this ADL BF,
Reset the DWL counter 454 at the start of energization,
Incremented by synchronized angle pulse PC being high level. It also maintains the angle at which energization starts from the previous ignition position.
Compare with DWL register 416 and when greater or equal, DL FF5 of first register 502
30 is set to 1, and the second register 50 is set to 1.
4's DWL BF532 is set to 1. this
The output of DWL BF532 becomes the ignition control signal ING1. FIG. 12 is a diagram explaining EGR (NIDL) processing. Since these are all proportional solenoids, they perform duty control. maintain the cycle
Holds EGRP register 418 and on time
There are two EGRD registers 420 and a timer that is measured by an EGR timer 456. In processing, during EGRP STG processing, the data held in the EGRP register 418 and the EGR tire 456 are compared, and if they are greater or equal, 1 is set in the EGRP FF 534 of the first register group 502. Set. Furthermore, the EGRP of the second register group 504
BF536 is set to 1. During EGRD STG processing, the EGR timer 456 is unconditionally non-incremented, and when EGRP BF=1, the EGR timer 456 is reset. EGRDFF538
compares EGRD register 420 and EGR timer 456, and if the results are greater than or equal,
EGRD_BF540 is set to 1. The inverted output of this EGRD BF540 is EGR
is the control signal. The operation is similar to NIDL. Figure 13 shows the engine speed RPM (and vehicle speed).
FIG. The measurement method is to determine a certain measurement time width using the RPMW timer 460 and count the synchronized angle pulses PC within that time width. The RPMW timer 460, which measures the time width, is incremented unconditionally and the RPMW BF
When 552=1, it is reset. RPMW
The FF 550 is set to 1 when the RPMW register 426 holding the time width and the RPMW timer 460 are compared and the results are greater than or equal. By RPMWD indicating the rise of RPMW BF552, the contents of the RPM counter 462 that counted the PC are transferred to the RPM register 430 of the output register 474.
Transfer to and write. Also, RPMW BF552
=1, RPM counter 462 is reset. VSP STG processing is also similar to RPM. Table 3 shows the functions of each register.

【table】

【table】

【table】

【table】

[Table] Next, a method for setting reference data in the reference register 470 will be explained. Register 402,4
04, 406, and 410 are set when the device of this embodiment is started. Once set, these values do not change. Next, data set in register 408 is performed by program processing. Data INJD representing the opening time of the fuel injector 66 is input to the register 412. This data INJD is determined, for example, as follows. Air flow meter 14 output signal
QA is taken through multiplexer 122 to analog-to-digital converter 124 . Here, it is converted into digital data and held in a register (not shown). The load data TP is obtained from the data representing the intake air amount and the data held in the register 430 in FIG. 4 through calculation processing or information stored in a map form. In addition, intake temperature sensor 1
6. Digitally convert the outputs of the water temperature sensor and atmospheric pressure sensor, and make corrections based on this data and the engine operating status. Let this correction coefficient be K1. Furthermore, the battery voltage is also digitized, and correction is performed according to this data. This correction factor is TS
shall be. Next, correction is made to λ by sensor 80. Let this correction coefficient be α. In other words, data INJD is expressed as follows. In this way, the opening time of the fuel injector is determined.
However, the method shown here is just one example, and it is of course possible to define it using other methods. The register 414 contains data representing the ignition timing.
ADV is set. This data ADV is created, for example, as follows. Map-shaped ignition data θ with the above load data TP and rotation speed as factors
IG is held in the ROM 118 and determined from this map. Furthermore, starting correction, water temperature correction,
Add acceleration correction etc. In this way the data
ADV is created. The register 416 contains data DWL as data for controlling the primary current charging time of the ignition coil.
is set. This data DWL is the above data
It is calculated from the ADV value and the digital value of battery voltage. Data EGRP representing the period of signal EGR and data NIDLP representing the period of signal NIDL are set in registers 418 and 422, respectively. These data are predetermined. Data EGRD representing the energization width of the EGR valve (exhaust gas recirculation device) is set in the register 420. As this crest width increases, the valve opening ratio of the exhaust gas recirculation device increases, and the exhaust gas recirculation rate increases. For example, the data EGRD is stored in ROM1 in a map state using the load data TP and rotational speed as factors.
18. Furthermore, this data is corrected based on water temperature, etc. Data NIDLD representing the energization width of the air regulator 48 is set in the register 424.
This data is subjected to feedback control such that, for example, the rotational speed of the engine in a no-load state becomes a predetermined rotational speed, and is determined as the amount of feedback. Data RPMW and VSPW representing fixed time periods are set in registers 426 and 428, respectively, when the circuit of this embodiment is activated. In the above explanation, the output of the air flow sensor is used as an input factor to control the fuel injection amount, ignition advance angle, exhaust gas recirculation amount, etc. However, it is possible to use a sensor other than this air flow sensor as a sensor that indicates the state of the intake air. For example, a pressure sensor that detects intake manifold pressure may be used. According to the embodiment of the comprehensive control system for an automobile engine according to the present invention, since pulse signals irregularly input to the stage cycle are synchronized, accurate detection can be performed. Furthermore, in the embodiment described above, the stage cycle is divided into a large cycle and a small cycle, so the detection cycle can be shortened depending on the accuracy, and the stage for detecting the synchronization signal can be included in the small cycle configuration. Therefore, accurate detection is possible even at high engine speeds. According to the embodiment described above, a reference register group, an instantaneous register group, and a comparison result holding register group are provided, and each predetermined register of the register group is connected to the comparison circuit based on the stage counter, so that many engine control functions can be achieved. Despite this, the circuit has the effect of being relatively simple. Next, the main parts of the present invention will be explained. In the function of measuring engine speed and vehicle speed by performing the basic operations described above, RPMW is used to set the measurement time width.
Register 426 (VSPW register 4 for VSP function)
The data in 28) may change depending on the engine speed. For example, the measurement time width data is made large at low rotations and small at high rotations. 14th
The figure is an explanatory diagram of the operation of each register and timer when the data in the RPMW register 426 (or VSPW register 428) is reduced, and since the VSP function is exactly the same, the RPMW function will be mainly explained below. In the figure, the solid line shows the operation when the data in the register 426 is not changed, and the broken line shows the operation when the data in the RPMW register 426 is changed at time _t0 . Now, when the measurement time width data of the RPMW register 46 is changed, the RPM register 430
When measurement data transfer signal RPMWD is generated to
A reset signal for RPMC register 462 is also output. ) and the data change timing are not synchronized, the time from data change t ₀ to t ₁ when measurement data is first established, that is, the dead time, is
The measurement time after data change is added to the time for one or two cycles of RPMWSTG. Here, the measurement time refers to the time from time t ₁ '' to time t ₁ in the figure. The dead time reaches its maximum before the data change time t ₀ and t ₀ ' coincide. Especially when the vehicle speed is With the VSP function that measures
The period of VSPSTG is set large due to the number of register bits. Therefore, the period of VSPSTG has a large effect on the dead time until measurement data is established. Therefore, it is desirable to reduce this dead time as much as possible. In this embodiment, in order to minimize the dead time described above, the RPMWT register 4 that first arrives from time _t0 when data is changed, as shown by the broken line in FIG.
Signal to reset 60 and RPMC462
By providing a means for generating RPMRST (or VSPRST in the case of the VSP function), it is possible to make the dead time at most one cycle of RPMSTG plus the measurement time. That is, it is possible to reduce the dead time by one cycle of RPMSTG. An embodiment of the circuit for generating the reset signal RPMRST or VSRPST shown in FIG. 14 is shown in FIG. 15, and its time chart is shown in FIG. 16. In Fig. 15, 664 is an address decoder, and the CPU 11
4 via the address bus 164, it generates an address signal for regulating the operating state of a specific register. The RPM reset signal generation circuit 700 is composed of an SR flip-flop circuit 701, latch circuits 702 and 703, and a VSP reset signal generation circuit 710.
Similarly, the SR flip-flop circuit 711,
It is composed of latch circuits 712 and 713. The set terminals S of the flip-flop circuits 701 and 711 are connected to the output terminals X ₁ and X ₂ of the address decoder 664, and the reset terminal R is connected to the latch circuit 7.
They are connected to terminals 03 and 713, respectively. Furthermore, the output terminals Q of the flip-flop circuits 701 and 711 are connected to the input terminals of OR circuits 704 and 714, and are logically summed with the signals RPMWBF and VSPWBF, respectively, and the output thereof is sent to the reset function section 901 of the incrementer shown in FIG. The signal is configured to be sent to an AND-OR circuit. Now, when the CPU 114 executes a new measurement time data write command, the address bus 16
4. Address signals PRMWADDR and VSPWADDR of the reference register are outputted via the address decoder 664. These address signals are input
The RPM reset signal generation circuit 700 and the VSP reset signal generation circuit 710 each generate a reset signal whose pulse width is determined at the rising edge of the address signal RPMWADDR and the signal STG7, or the address signal VSPWADDR and the signal STG7.
RPMRST and VSRPST are connected to the OR circuits 704 and 71.
4 to each input terminal. The OR circuits 704 and 714 each receive the reset signal.
RPMPST, VSPRST and signal RPMWBF,
An output signal obtained by ORing with VSPWBF is sent to the reset function section 901. Furthermore, based on the OR output signal, the reset function unit 901 sets the reference registers (RPMW register, VSPW register) and instantaneous registers (RPMC register, VSPC register) to each stage RPMWSTG, RPMSTG,
In order to reset VSPWSTG and VSPSTG, a reset signal is sent to the reference register and instantaneous register at a predetermined timing. In addition, in FIG. 14, the case where the data of the RPMW register 426 is changed to the instantaneous value of the RPMWT register 460 or less is explained, but if the data is the instantaneous value of the RPMWT register 460 or more, the data is changed to the data before the data change. On the other hand, regardless of the size, new measurement data is established within the measurement time after the data is changed, so as in the case described above with reference to Figures 14 and 15, the dead time is at most one cycle of RPMWSTG. It is necessary to consider only the time by adding the measurement time after data change to the time of . The correspondence relationship between one embodiment of the above description and the configuration of the invention described in the claims is as follows.

[Table] According to the embodiment described above, when the measurement time is changed when measuring engine speed or vehicle speed, the count value is immediately reset, so the time from the time the measurement time is changed to the establishment of data is shortened. . According to the present invention, the chip area required for integrating the time measurement counter and the rotation synchronous pulse counter is reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the main configuration of a comprehensive control system for an automobile engine, Fig. 2 is an operation explanatory diagram for explaining the operation of Fig.
4 is a detailed diagram of a portion of the input/output circuit of FIG. 3, FIG. 5 is an explanatory diagram of the operation of FIG. 4, and FIG. 6 is a detailed diagram of the stage counter of FIG. 4. Figure 7 is a detailed diagram of the synchronization circuit, and Figure 8 is a detailed diagram of the synchronization circuit.
Figure 9 is a detailed diagram of the incrementer controller, Figure 10 is a diagram explaining the operation of fuel injection signal processing, Figure 11 is a diagram explaining the operation of ignition timing control, and Figure 12 is the signal EGR or NIDL. Fig. 13 is an explanatory diagram of the processing of the engine rotation speed signal.
Diagram explaining the operation of RPM or vehicle speed signal VSP detection,
Figure 14 shows the RPM register 426 (or VSPW
Figure 15 is an explanatory diagram of the operation of each register and timer when the data in register 428) is reduced.
Reset signals RPMRST and VSPRST shown in Figure 4
FIG. 16 is a time chart of FIG. 15, showing an example of a circuit for generating . 10...Control circuit, 12...Air cleaner, 14
...air flow meter, 16...intake temperature sensor,
18... Throttle chamber, 20... Throttle valve, 22... Accelerator pedal, 24... Throttle position detector, 26... Intake manifold, 28... Exhaust gas recirculation device, 30... Engine, 32... Intake valve, 34... Combustion chamber, 36...spark plug, 38...distributor, 40...ignition coil, 42...
Bypass passage, 44...Idle adjust screw, 46...Bypass passage, 48...Air regulator, 50...Fuel tank, 52...Fuel pump, 54...Fuel damper,
56...Fuel filter, 58...Fuel return pipe, 60...Fuel pipe, 62
...Burning pressure regulator, 64... Impulse pipe, 66... Fuel injector, 68... Pipe, 70... Canister, 72... Pipe, 74... Piston, 76
...Air distribution pipe, 78...Exhaust gas recirculation pipe (EGR pipe), 8
0...λ sensor, 82...catalytic converter, 84...exhaust temperature sensor, 86...muffler, 88...negative power supply terminal,
90... Positive power terminal, 92... Positive power terminal, 94... Cooling water, 96... Water temperature sensor, 98... Angle sensor,
PR...Reference signal, PC...Angle signal, 110
... battery positive terminal, 112 ... constant voltage circuit (output voltage PVCC), 114 ... (CPU) central processor, 116 ... (RAM) random access memory, 118 ... (ROM) read-only memory, 1
20...I/O circuit, 122...Multiplexer, 1
24...A/D converter, 126...pulse output circuit,
128...Pulse input circuit, 130...Discrete input/output circuit, 132...Filter, 134...Filter, 136...Filter, 138...Filter, 1
40...Filter, 142...Amplifier, 144...Filter, 146...Atmospheric pressure sensor, 148...Zena,
150, 152, 154...Resistance, 156, 158
...Connection point, 160...Resistor, 162...Data bus,
164... Address bus, 166... Control bus, 168... Filter, 170... Speed detector, 172... Filter, 174... Throttle switch (fully closed), 176... Starter switch, 17
8... Gear switch, 180, 182, 184... Filter, 186... Power amplification circuit (fuel injection),
188...Power amplification circuit (ignition circuit), 194...
Power amplification circuit (EGR), 196...Power amplification circuit (EGR OFF), 198...Power amplification circuit (NIDLE), 200...Power amplification circuit (fuel pump), 202...Power amplification circuit (catalyst alarm), 20
4...Power amplification circuit (overheat), 206...
Fuel pump, 208... Lamp (catalyst alarm), 21
0... Lamp (overheat), 402... Register, 404... Register, 406... Register, 40
8...Register, 410...Register, 412...Register, 414...Register, 416...Register, 4
18...Register, 420...Register, 422...Register, 424...Register, 426...Register,
428...Register, 430...Register, 432...
register, 442... register, 444... register, 446... register, 448... register, 45
0...Register, 452...Register, 454...Register, 456...Register, 458...Register, 4
60...Register, 462...Register, 464...Register, 468...Register, 470...Reference register group (RF0), 472...Momentary register group (RF
1), 474...Output register group (RF2), 476
...Latch circuit, 478...Incrementer, 480
...Comparator, 482...Comparator input terminal, 484...Comparator input terminal, 486...
Comparator output terminal, 490... Incrementer controller, 502... First comparison output register group (FFM), 504... Second comparison output register group (FFS), 506... Register (CYL), 508... Register (CYL), 510 ...Register (INTL), 5
12...Register (INTL), 514...Register (INTV), 516...Register (INTV), 518...
Register (ENST), 520...Register (EMST), 522...Register (INJ), 524...
Register (INJ), 526...Register (ADV), 5
28...Register (ADV), 530...Register (DWL), 532...Register (DWL), 534...
Register (EGRP), 536...Register (EGRP), 538...Register (BGRD), 540
...Register (BGRD), 524...Register (NIDLP), 544...Register (NIDLP), 546
...Register (NIDLD), 548...Register (NIDLD), 550...Register (PPMW), 552
...Register (PPMW), 554...Register (VSPW), 556...Register (VSPW), 570
...stage counter, 572...stage decoder, 664...address decoder, 700...RPM
System reset signal generation circuit, 710...VSP system reset signal generation circuit, 701, 711...SR flip-flop circuit, 702, 703, 712, 713
...Latch circuit, 901...Reset function section.

Claims (1)

[Scope of Claims] 1. An analog sensor that generates an analog signal for controlling the automobile, a rotation sensor that generates a rotation synchronization pulse in synchronization with engine rotation or wheel rotation, and a digital sensor based on the analog signal. a digital computer that calculates a control value for the vehicle based on a digital signal based on the signal and the rotation synchronization pulse, and an actuator that controls the vehicle based on the control value of the digital computer, the rotation synchronization pulse generated by the rotation sensor; The conversion circuit that converts the rotation synchronization pulses into a digital signal includes a counting time holding circuit that holds the counting time for counting the rotation synchronization pulses, and a time measurement counter that counts the clock pulses that are generated at regular intervals to measure the counting time. and a rotation synchronous pulse counter that counts the rotation synchronous pulses, and when the count value of the time measurement counter reaches the counting time held by the counting time holding circuit, the count value of the rotation synchronous pulse counter is counted by the rotation synchronous pulse counter. In the device that outputs a digital signal based on pulses, the time measurement counter and the rotation synchronous pulse counter have first and second count values that respectively hold the count value of the time measurement counter and the count value of the rotation synchronous pulse counter. a holding circuit, an incrementer that increases the value of the input data by 1 based on the increment signal and further sets the value of the input data to zero based on the reset signal, and the first and second count value holding circuits, respectively. The held count value is selectively added to the incrementer as input data based on a time pulse generated at a predetermined time period, and the output of the incrementer is re-inputted to the first and second count value holding circuits, respectively. and an increment controller that applies an increment signal to the incrementer in synchronization with the operation of the selection circuit based on the generation of the rotation synchronization pulse and the clock pulse. . 2. The measuring device for automobile control according to claim 1, wherein the increment controller applies a reset signal to the incrementer when the counting time held in the counting time holding circuit is changed.