JPS6224617B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic control device for an internal combustion engine. Recently, microprocessors have become very popular, and trials of computer control are also being conducted in the field of automobile engines. For example, it is disclosed in Japanese Patent Application Laid-Open No. 50-90826. In computer engine control, the calculation section of a computer has been miniaturized, but the miniaturization of the pulse conversion circuit that converts the output of the computer into pulses has not progressed at all. The basic configuration of the pulse conversion circuit is a register, a counter, and a comparator. Conventionally, a combination circuit of the register, counter, and comparator has been provided for each type of generated pulse. For this reason, each circuit is independent, making it difficult to miniaturize. As a method of solving this problem, there is an application, Japanese Patent Application No. 52-114048, which was filed almost at the same time as the present application, which proposes a system in which the above-mentioned comparators are commonly used. The invention of this application uses a common comparator and switches the comparison target using a high-speed switching circuit. In order to improve engine controllability, it is necessary to increase the switching speed of this switching circuit. However, this has its limits. An object of the present invention is to provide an engine control device with high engine controllability. A feature of the present invention is that, as described above, the pulse output circuit that converts computer output into pulses is composed of a plurality of registers, a comparator, and at least one counter, and this comparator is commonly used for a plurality of registers. In the present invention, each of the plurality of registers does not use the comparator at the same frequency, but can be used with priority. For this purpose, a periodic signal generation circuit that generates a plurality of periodic signals is provided, and one register and the other register of the plurality of registers are selected at different periods. As a result, registers selected in short cycles have higher priority than other registers. Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a system diagram showing the main configuration of an electronic engine control device. The flow rate of the air taken in through the air cleaner 12 is measured by an air flow meter, and an output QA representing the air flow rate is input from the air flow meter 14 to the control circuit 10. The air flow meter 14 is provided with an intake temperature sensor 16 for detecting the temperature of intake air, and an output TA representing the temperature of the intake flow rate is input to the control circuit 10. The air that has passed through the air flow meter 14 passes through the throttle chamber 18 and is then
The air is drawn into the combustion chamber 34 of the engine 30 from the manifold 26 via the intake valve 32. The amount of flow sucked into the combustion chamber 34 is controlled by varying the opening of a throttle valve 20 located within the throttle chamber in mechanical conjunction with the accelerator pedal 22. The opening degree of the throttle valve 20 is determined by detecting the position of the throttle valve 20 by the throttle position detector 24, and the signal QTH representing the position of the throttle valve 20 is detected by the throttle position detector 24.
4 to the control circuit 10. The throttle chamber 18 is provided with an idle bypass passage 42 and an idle adjust screw 44 for adjusting the amount of air passing through the bypass passage 42. When the engine is operating in an idling state, the throttle valve 20 is in a fully closed position. air flow
Intake air from meter 14 flows through bypass passage 42 and is drawn into combustion chamber 34 . Therefore, the amount of intake air during idling operation can be changed by adjusting the idle adjust screw. The energy generated in the combustion chamber is almost determined by the amount of air flowing from the bypass passage 42, so by adjusting the idle adjust screw 44 and changing the amount of air taken into the engine, the engine rotation speed during idling can be adjusted to an appropriate level. can be adjusted to a suitable value. The throttle chamber 18 is further provided with a further bypass passage 46 and an air regulator 48. Air regulator 48 is control circuit 1
The amount of air passing through the passage 46 is controlled in accordance with the output signal NIDL of zero, and the engine speed is controlled during warm-up operation and an appropriate amount of air is supplied to the engine when the throttle valve 20 suddenly changes. Additionally, the air flow rate during idling operation can be changed as necessary. Next, the fuel supply system will be explained. Fuel stored in the fuel tank 50 is sucked into the fuel pump 52 and pumped to the fuel damper 54. The fuel damper 54 absorbs the pressure pulsations of the fuel from the fuel pump 52 and transfers the fuel at a predetermined pressure to the fuel filter 5.
6 to the fuel pressure regulator 62. Fuel from the fuel pressure regulator is fed under pressure to a fuel injector 66 via a fuel pipe 60, and the fuel injector 66 is opened by the output INJ from the control circuit 10 to inject fuel. The amount of fuel injected from the fuel injector 66 is determined by the valve opening time of the injector 66 and the pressure difference between the pressure of the fuel fed to the injector and the pressure of the intake manifold 26 into which the fuel is injected. However, it is desirable that the fuel injection rate from the fuel injector 66 is dependent only on the valve opening time determined by the signal from the control circuit 10. Therefore, the pressure of the fuel fed to the fuel injector 66 is controlled by the fuel pressure regulator 62 so that the difference between the fuel pressure to the fuel injector 66 and the manifold pressure of the intake manifold 26 is always constant. Intake manifold pressure is applied to the fuel pressure regulator 62 via a pressure guiding pipe 64, and when the fuel pressure in the fuel pipe 60 exceeds a certain level with respect to this pressure, the fuel pipe 6
0 and the fuel return pipe 58 are in communication with each other, and the fuel corresponding to the excess pressure is transferred to the fuel tank 50 via the fuel return pipe 58.
be returned to. In this way, the difference between the fuel pressure in the fuel pipe 60 and the manifold pressure in the intake manifold is always kept constant. The fuel tank 50 is further provided with a pipe 68 and a canister 70 for absorbing vaporized fuel gas, and an atmosphere opening 7 is provided during engine operation.
4, and the absorbed vaporized fuel gas is guided to the intake manifold through a pipe 72 and then to the engine 30. As explained above, fuel is injected from the fuel injector, the intake valve 32 opens in synchronization with the movement of the piston 74, and a mixture of air and fuel is introduced into the fuel chamber 34. This air-fuel mixture is compressed and combusted by the spark energy from the spark plug 36, thereby converting the combustion energy of the air-fuel mixture into kinetic energy that moves the piston. The combusted air-fuel mixture is exhausted as exhaust gas from an exhaust valve (not shown) to the atmosphere via an exhaust pipe 76, a catalytic converter 82, and a muffler 86. exhaust pipe 76
is the exhaust gas recirculation pipe 78 (hereinafter referred to as EGR pipe).
A portion of the exhaust gas is guided to the intake manifold 26 through this pipe. That is, part of the exhaust gas is recirculated to the intake side of the engine. This recirculation amount is determined by the valve opening amount of the exhaust gas recirculation device 28. This valve opening amount is the output of the control circuit 10.
Exhaust valve gas recirculation device 2 controlled by EGR
The valve position of 8 is converted into an electrical signal and inputted to the control circuit 10 as a signal QE. A λ sensor 80 is provided in the exhaust pipe 76 and detects the mixture ratio of the air-fuel mixture sucked into the combustion chamber 34. Specifically O ₂ sensor (oxygen sensor)
is generally used to detect the oxygen concentration in the exhaust gas and generate a voltage Vλ according to the oxygen concentration. The output Vλ of the λ sensor 80 is input to the control circuit 10. The catalytic converter 82 is provided with an exhaust temperature sensor 84, and an output TE corresponding to the exhaust temperature is input to the control circuit 10. The control circuit 10 is provided with a negative power terminal 88 and a positive power terminal 90. Further, the control circuit 10 applies the above-described signal IGN to the primary coil of the ignition coil 40 to control the spark generation of the ignition plug 36, and the high voltage generated in the secondary coil is passed through the power distributor 38 to the ignition plug 36. is applied to generate a spark for combustion within the combustion chamber 34. More specifically, the ignition coil 40 is provided with a positive power supply terminal 92, and the control circuit 10 is further provided with the ignition coil 4.
A power transistor is provided for controlling the primary coil current of zero. A series circuit between the primary coil of the ignition coil 40 and the power transistor is formed between the positive power terminal 92 of the ignition coil 40 and the negative power terminal 88 of the control circuit 10, and the power transistor is electrically connected. The ignition coil 40
Electromagnetic energy is accumulated in the spark plug 36, and when the power transistor is cut off, the electromagnetic energy is applied to the spark plug 36 as energy having a high voltage. The engine 30 is provided with a water temperature sensor 96,
The temperature of engine cooling water 94 is detected, and a signal TW corresponding to this temperature is input to control circuit 10. Further, the engine 30 is provided with an angle sensor 98 that detects the rotational position of the engine, and this sensor 98 generates a reference signal PR every 120 degrees, for example, in synchronization with the rotation of the engine. degree) Angle signal every time it rotates
Generate PC. These signals are input to the control circuit 10. A negative pressure sensor may be used in place of the air flow meter 14 in FIG. A negative pressure sensor 100 indicated by a dotted line in the figure inputs a voltage VD corresponding to the negative pressure of the intake manifold 26 to the control circuit 10. Specifically, a semiconductor negative pressure sensor can be considered as the negative pressure sensor 10. The boost pressure of the intake manifold is applied to one side of the silicon chip, and atmospheric pressure or constant pressure is applied to the other side.
In some cases, a vacuum may be used. With such a structure, a voltage VD corresponding to the manifold pressure is generated due to the piezoresistance effect, etc., and is applied to the control circuit 10. FIG. 2 is an operational diagram illustrating ignition tamping and fuel injection timing with respect to the crank angle of a six-cylinder engine. A represents the crank angle, and a reference signal PR is output from the angle sensor 98 every 120 degrees of crank angle. In other words, the crank angle is 0.
A reference signal PR is input to the control circuit 10 at every angle of 120°, 240°, 360°, 480°, 600°, and 720°. In the figure, B, C, D, H, H, and G are the first cylinders, respectively.
5th cylinder, 3rd cylinder, 6th cylinder, 2nd cylinder, 4th cylinder
Represents the operation of the cylinder. Further, J1 to J6 represent the opening positions of the intake valves of each cylinder. As shown in Fig. 2, the valve opening positions of each cylinder are shifted by 120° in terms of crank angle. Although the valve opening position and valve opening width differ somewhat depending on the structure of each engine, they are approximately as shown in the figure. In the diagram, A1 to A5 are fuel injectors 66
This represents the valve opening timing, that is, the fuel injection timing. The time width JD of each injection timing A1 to A5 is fuel
It represents the opening time of the injector 66. This time width JD can be considered to represent the fuel injection amount of the fuel injector 66. A fuel injector 66 is provided corresponding to each cylinder, and these injectors are each connected in parallel to a drive circuit within the control circuit 10. Therefore, in response to the signal INJ from the control circuit 10, the fuel injectors corresponding to each cylinder open simultaneously and inject fuel. The first cylinder shown in FIG. 2B will be explained. crank angle 360
In synchronization with the reference signal INTIS generated at
is applied to the injector 66. As a result, fuel is injected for the time JD calculated by the control circuit 10 as shown by A2. However, since the intake valve of the first cylinder is closed, the injected fuel is held in the atmosphere of the intake port of the first cylinder and is not sucked into the cylinder. Next, a signal is again sent from the control circuit to each fuel injector 66 in response to the reference signal INTIS generated at a crank angle of 720 degrees, and fuel injection indicated by A3 is performed. Almost simultaneously with this fuel, the first
The intake valve of the cylinder opens, and with this valve opening, both the fuel injected at A2 and the fuel injected at A3 are sucked into the combustion chamber. The same can be said for other cylinders. That is, in the fifth cylinder shown in C, the fuel injected at A2 and A3 is taken in at the opening position J5 of the intake valve. In the third cylinder shown in D, a part of the fuel injected at A2, a part of the fuel injected at A3, and a part of the fuel injected at A4 are taken in at the opening position J3 of the intake valve. Some of the fuel injected at A2 and A
Adding the part of the fuel injected in step 4, it becomes the injection amount for one injection. Therefore, in each intake stroke of the third cylinder, two injection amounts are taken in, respectively. 6th cylinder, 2nd cylinder, 4th cylinder shown in E, H, G
Similarly, in the cylinder, two injections from the fuel injector are inhaled in one intake stroke. As can be seen from the above explanation, the fuel injection signal from the control circuit 10
The fuel injection amount specified by INJ is half of the fuel required for intake, and fuel injector 6
The required amount of fuel corresponding to the air taken into the combustion chamber 34 can be obtained by two injections of No. 6. In FIG. 2, G1 to G6 indicate ignition timings corresponding to the first to sixth cylinders. By cutting off the power transistor provided in the control circuit 10, the primary coil current of the ignition coil 40 is cut off, and a high voltage is generated in the secondary coil. This high voltage is generated at the ignition timings G1, G5, G6, G2, and G4, and is distributed by the power distributor 38 to the spark plugs provided in each cylinder. This allows the first
The spark plugs are ignited in the order of cylinder, fifth cylinder, third cylinder, sixth cylinder, second cylinder, and fourth cylinder, and the mixture of fuel and air is combusted. The detailed circuit configuration of the control circuit 10 in FIG.
As shown in the figure. A positive power supply terminal 90 of the control circuit 10 is connected to a positive terminal 110 of the battery, and a voltage VB is supplied to the control circuit 10. The power supply voltage VB is maintained at a constant voltage PVCC, for example [V], by a constant voltage circuit 112. This constant voltage PVCC is supplied to a central processor (hereinafter referred to as CPU), random access memory (hereinafter referred to as RAM), and read-only memory (hereinafter referred to as ROM). Furthermore, the output PVCC of the constant voltage circuit 112 is also input to the input/output circuit 120. The input/output circuit 120 includes a multiplexer 122, an analog/digital converter 124, a pulse output circuit 126, a pulse input circuit 128, a discrete input/output circuit 130, and the like. Analog signals are input to the multiplexer 122, and one of the input signals is input based on a command from the CPU.
is selected and input to the analog-to-digital converter 124. As analog input signals, each sensor shown in FIG. From QA respectively,
Analog signal TW representing engine cooling water temperature,
Analog signal TA representing intake temperature, analog signal TE representing exhaust gas temperature, analog signal QTH representing throttle opening, analog signal QE representing valve opening status of exhaust gas recirculation device, analog signal representing excess air ratio of intake mixture The signal Vλ and the analog signal QA representing the amount of intake air are sent to the filter 132~
144 to multiplexer 122. However, the output Vλ of the λ sensor 80 is input to the multiplexer via an amplifier 142 having a filter circuit. In addition, an analog signal VPA representing atmospheric pressure is input from the atmospheric pressure sensor 146 to the multiplexer. Also, from the positive power supply terminal 90°, resistor 150, 15
Voltage VB is supplied to the 2,154 series circuits through a resistor 160, and the terminal voltage of the series circuit of the resistors is held constant by a zener 148. The values of voltages VH and VL at junctions 156 and 158 between resistors 150 and 152 and resistors 152 and 154 are input to multiplexer 122. CPU114, RAM116, and ROM1 mentioned above
18 and the input/output circuit 120 are connected by a data bus 162, an address bus 164, and a control bus 166, respectively. Furthermore, from the CPU
A clock signal E is applied to each of the RAM, ROM, and input/output circuit 120, and data is transmitted via the data bus 162 in synchronization with this clock signal E. The multiplexer 122 of the input/output circuit 120 has water temperature TW, intake air temperature TA, exhaust gas temperature TE, throttle opening QTH, exhaust recirculation amount QE, λ sensor output Vλ, atmospheric pressure VPA, intake air amount QA, and reference voltage.
Negative pressure VD is input instead of VH, VL, and intake air amount QA. These inputs are in ROM118
CPU based on the instruction program stored in
114 is designated with its address via the address bus, and the analog input of the designated address is taken in. This address input is multiplexer 1
22 to the analog-to-digital converter 124, the digitally converted values are held in registers corresponding to each input, and are sent to the CPU via the control bus 166 as necessary.
CPU 114 or
It is taken into RAM116. A reference pulse PR and an angle signal PC are input from the angle sensor 98 to the pulse input circuit 128 in the form of a pulse train via a filter 168.
Furthermore, a pulse PS having a frequency corresponding to the vehicle speed is input from the vehicle speed sensor 170 to the pulse input circuit 128 via the filter 172 in the form of a pulse train. The signal processed by CPU 114 is held in pulse output circuit 126. Pulse output circuit 12
The output from 6 is applied to a power amplifier circuit 188, and the fuel injector is controlled based on this signal. Reference numerals 188, 194, and 198 are power amplification circuits that control the primary coil current of the ignition coil 40, the opening degree of the exhaust gas recirculation device 28, and the air regulator 4, respectively.
8 is controlled according to the output pulse from the pulse output circuit 126. The discrete input/output circuit 130 receives signals from a switch 174 that detects that the throttle valve 20 is in a fully closed state, a starter switch 176, and a gear switch 178 that indicates that the tranmission gear is a top gear, respectively, through a filter 180, 182,184
Receive and hold via. Furthermore, it holds processing signals from the central processor CPU 114. The signals related to the discrete input/output circuit 130 are signals whose contents can be displayed with one bit. Next, the power amplifier circuits 196, 200,
Signals are sent from the discrete input/output circuit to 202 and 204, respectively, and the exhaust gas recirculation device 28
closes to stop exhaust gas recirculation, controls the fuel pump, indicates abnormal catalyst temperature, and indicates engine overheating. FIG. 4 shows a specific circuit of the pulse output circuit 126. A register group 470 is the reference register group mentioned above, and is used to hold data processed by the CPU 114 or to store data at a predetermined constant level. Holds data indicating the value. This data is CPU
114 via the data bus 162.
The register to be held is specified via the address bus 164, and the above data is input to the specified register and held. The register group 472 is a momentary register group and holds the instantaneous state of the engine and the like. Instantaneous register group 472, latch circuit 476, and incrementer 4
78 exhibits a so-called counter function. The output register group 474 includes, for example, a register 430 that holds the rotational speed of the engine and a register 432 that holds the vehicle speed. These values are obtained by reading the values of instantaneous registers when certain conditions are met. Output register group 47
The data held in CPU 162 is sent to a related register by a signal sent from the CPU via the address bus, and sent from this register to the CPU 114 via the data bus 162. Comparator 480 receives reference data from a selected register of the group of reference registers and instantaneous data from a selected register of the group of instantaneous registers at inputs 482 and 484, respectively, and performs a comparison operation. The comparison result is output from the output terminal 486. The output terminal is set in a predetermined register in the first comparison output register group 502 which functions as a comparison result holding circuit. Furthermore, it is then set in a predetermined register of the second comparison output register group 504. Reference register group 470, instantaneous register group 47
2. Read and write operations of the output register group 474, incrementer 478 and comparator 480
The operations of setting the output to the first comparison output register 502 and the second comparison output register 504 are processed within a certain predetermined time. Further, various processes are performed in a time-sharing manner according to the stage order of the stage counter 572. For each stage, a predetermined register of each of the reference register group 470, instantaneous register group 472, first and second comparison result register groups, and if necessary, a predetermined register of the output register group 472 is selected. . In addition, the inklinter 478 and the comparator 48
0 is commonly used. FIG. 5 is a diagram for explaining the timing of FIG. 4. A clock signal E is supplied from the CPU 114 to the input/output circuit 120. This signal is shown in A. From this clock signal E, a circuit 574 generates two non-overlapping clock signals φ1 and φ2. This signal is shown in (b) and (c). The circuit shown in FIG. 4 operates according to these clock signals φ1 and φ2. In FIG. 5, d is a stage signal, which is switched at the rise of the clock signal φ2, and the processing of each stage is performed in synchronization with φ2. In Figure 5
THROUGH indicates that the latch circuit or register circuit is enabled, and indicates that the output of these circuits is dependent on the input. Also
LATCH indicates that these circuits hold certain data and the output of this circuit does not depend on the input. The stage signal shown in (d) becomes a readout signal for the reference register 470 and instantaneous register 472, and the contents are read out from a certain selected predetermined register. E and F show the operation of reference register 470 and instantaneous register 472, respectively. This operation is performed in synchronization with the clock φ. The operation of latch circuit 476 is shown in FIG. This circuit enters the THROUGH state when φ2 is at a high level, writes data in a specific register read from the instantaneous register group 472, and clocks φ2.
When 2 becomes low level, it becomes LATCH state. In this way, the data of a predetermined register in the instantaneous register group corresponding to that stage is held. The data held in the latch circuit 476 is
Incrementer 478 not synchronized to clock signal
modified based on external conditions. Here, it has the following functions based on the signal from the incrementer controller 490. The first function is an increment function that increases the value indicated by the input data by one. The second function is a non-increment function, which allows the input to pass through without being increased. The third function is a reset function, which changes all inputs to data indicating a value of 0. Looking at the data flow of the instantaneous registers, one register in the instantaneous register group 472 is selected by the stage counter 572, and its held data is input to the comparator 480 via the latch circuit 476 and the incrementer 478. Additionally, a closed loop is created from the output of incrementer 478 back to the originally selected register. Therefore, when the incrementer functions to increase data by one, this closed loop functions as a counter. However, in this closed loop, if a situation occurs in which the data of the instantaneous register group is output from a specific selected register while the data is looped around and input, malfunction occurs. Therefore, a latch circuit 476 is provided to cut off the data. The latch circuit 476 enters the THROUGH state in synchronization with clock φ2, while the THROUGH state in which the input is written to the instantaneous register is synchronized with clock φ1. Therefore, data is cut between clocks φ2 and φ1. In other words, even if the value of a specific register in the register 472 is changed, the latch circuit 47
The output of 6 remains unchanged. Comparator 480, like incrementer 476, also operates out of synchronization with the clock signal. The input of the comparator 480 is transmitted through a latch circuit and an incrementer for the data held in one reference register selected from the reference register group 470 and the data held in one register selected from the instantaneous register group. received data. The result of this data comparison is synchronized with clock signal φ1.
It is set to the first comparison result register group 502 which enters the THROUGH state. Furthermore, this data is set in the second comparison result register group 504 which enters the THROUGH state at clock φ2. The output of this register 504 becomes a signal for controlling each function of the incrementer, and a drive signal for the fuel injector, ignition coil, exhaust gas recirculation device, etc. Also, based on this signal, the measurement results of the engine rotational speed and vehicle speed at each stage are written from the instantaneous register group to the output register group 474.
Now, for example, when writing engine rotation speed, a signal indicating that a certain period of time has passed is held in the second comparison result register RPMWBF552, and in the RPM stage of Table 1, which will be described later, the instantaneous register is written based on the output of this register 552. 462
The held data is stored in the register 430 of the output register group.
is input to. At this time, the second comparison result register
If the signal indicating that a certain period of time has elapsed is not held in the RPMWBF 552, the operation of inputting the data held in the register 462 to the register 430 is not performed even in the RPM stage. On the other hand, based on the signal held in the second comparison result register VSPWBF 556, data in the instantaneous register 468 is inputted to the output register 432 as data representing the vehicle speed at the timing of the stage VSP. Writing of data representing the engine rotational speed RPM and vehicle speed VSP to the output register group 474 is performed as follows. In Figure 5,
The stage signal STG is RPM or VSP, and the data in the instantaneous register 462 or 468 is at the high level of the clock φ2, and the latch circuit 476 is activated.
It becomes THROUGH state and is written, and the clock φ
2 becomes low level, the above data becomes
LATCHed. The data held in this way is stored in the register RPMWBF552 or
Based on the signal from the VSPWBF556, the output register group 474 enters the THROUGH state as shown in FIG.
be done. When the CPU 114 reads data held in the output register group 474, the CPU 114 specifies the register via the address bus 164, and the data is taken in in synchronization with the clock signal E shown in FIG. 5A. FIG. 6 shows a generation circuit for the stage signal STG. The stage counter SC570 is counted up by the signal φ1 from the circuit 574, and the outputs C0 to C6 of the stage counter SC570 and the output of the T register in FIG. 4 are input to the stage decoder SDC. The stage decoder SDC writes signals 01 to 017 as outputs to the stage latch circuit STGL in synchronization with the clock φ2. The stage latch STGL reset input has a fourth
When the ^20- bit signal GO of the MODE register shown in the figure is input and the ^20- bit GO signal of the MODE register becomes low level, all outputs of STGL become low level and all processing operations are stopped. On the other hand, when the GO signal becomes high level, the stage signal STG is outputted again in a fixed order, and processing is performed based on it. The above stage decoder SDC is READ, ONLY,
This can be easily achieved by using MEMORY etc. Table 1 shows the detailed contents of stage signal STG, which is the output of stage latch STGL, from 00 to 6F.

【table】

[Table] First, the general reset signal GR is input to the reset terminal of the stage counter SC570 shown in FIG. 6, so that the counter outputs C0 to C6 all become 0. This general reset signal is sent from the CPU when this control circuit is activated. When clock signal φ2 is input in this state, at the rising edge of φ2,
EGRP stage signal STG is output. EGRP processing is performed based on this stage signal. Next, the stage counter SC570 counts up by one at clock φ1, and INTL of the next stage signal STG is output at clock φ2. INTL processing is performed based on this stage signal INTLSTG. Furthermore, next, a stage signal CYLSTG is output and CYL processing is performed, and next, a stage signal ADV is output and ADV processing is performed.
In this way, the stage counter SC570 becomes φ
When the count-up continues in synchronization with φ2, a stage signal STG is output in synchronization with φ2, and processing is performed in accordance with this signal. When C0 to C6 of stage counter SC570 all become 1, stage signal INJSTG is output.
The INJ process is performed and all the processes in Table 1 are completed. With the next clock signal φ1, all C0 to C6 of the stage counter SC570 become 0, and with the clock signal φ2, the stage signal EGRPSTG is output, and STG processing is performed. In this way the first
Repeat table processing. Table 2 shows the processing contents of each stage shown in Table 1.

【table】

[Table] Output from the stage latch circuit STGL in Figure 6
The STG0 and STG7 signals are circuits for synchronizing the input input from the outside with the internal clock signal of the input/output circuit 120.
Output STG7 is the stage counter
It is output when all of C0 to C2 of SC570 are 1. External signals include, for example, a reference signal PR generated in synchronization with engine rotation, an angle signal PC, and a vehicle speed pulse PS generated in synchronization with wheel rotation. The periods of these pulses change greatly, and as they are, they are not synchronized with the clock signals φ1 and φ2. Therefore, it is not possible to determine whether to increment at the ADVSTG stage, VSPSTG stage, or RPMSTG stage in Table 1. Therefore, it is necessary to synchronize external pulses, such as pulses from a sensor, with the stages of the input/output circuit. Furthermore, in order to improve detection accuracy, the angle signal PC and vehicle speed signal PS need to be synchronized with the stage with respect to the rise and fall of their input pulses. Reference signal PR
For this, it is sufficient to synchronize it with the rise. Output STG of stage latch circuit STGL in Figure 6
0 and STG7 to create the above synchronized signal at φ2 timing. The circuit is shown in FIG. Further, the operation timing is shown in FIG. External input pulses such as sensor output, such as reference pulse PR, angle signal PC, vehicle speed signal PS
are latched by the STG0 output shown in FIG. 6 to latch circuits 600, 602, and 604 shown in FIG. 7, respectively. In Figure 8, A is the clock signal φ2, B is the clock signal φ1, and C and D are the stage signals STG7 and STG.
It is 0. This stage signal is generated in synchronization with φ2, as explained in FIG. The signal shown in E is a signal pulse from the angle sensor or vehicle speed sensor, and is the reference pulse PR or angle pulse PC.
Alternatively, it indicates the vehicle speed pulse PS, and the generation timing, pulse duty, and period of this signal are irregular, and are inputted regardless of the stage signal. Now, a signal as shown in FIG.
Assuming that the pulses are input to 00, 602, and 604, they are latched by the stage signal STG0 (pulse shown in the figure). Therefore, as shown in FIG. 8, the level becomes high at the time point. Furthermore, since the input signals PR, PC, and PS are at high level in the stage signal STG0 indicated by wo, the latch circuits 600, 602, and 60
The high level is latched at 4. However, in the stage signal STG0 shown by w, the input signal PR,
Since PC and PS are at low level, low level is latched. Therefore, the latch circuit 600,
Outputs A1, A2, and A3 of 602 and 604 are as shown in F. Latch circuit 606, 608, 61
Since outputs A1, A2, and A3 are each latched by the stage signal STG7, 0 rises from the point indicated by y. Furthermore, the stage signal STG7 also latches at a high level, so it continues to be at a high level. Therefore, the latch circuits 606, 608, 610
The output signals B1, B2, and B3 are as shown in FIG. The signal A1 and the signal B1 sent through the inverter 608 are input to the NOR circuit 612, and a synchronized reference signal PRS is generated as shown in FIG. This synchronized reference signal PRS catches the rising edge of the reference signal PR and has the pulse width of the stage signals STG0 to STG7. The EXCLUSIVELYOR circuits 614 and 616 receive signals A2 and B2, and signals A3 and B3, respectively, and the rising edge of the signals PC and PV generates the signal shown in (i), and the falling edge of the signals PC and PV generates the signal (g). do. The duty of signals R and G is the same as the duty shown in C, and the duty of the stage signal STG
Determined by 0 and STG7. In the above explanation, it is assumed that the signals PR, PC, and PS are input at the same time with the same duty, but in reality, these signals are not input at the same time and their duties are also different. Furthermore, even when looking at the same signal itself, its period and duty differ each time. However, due to FIG. 7 and the synchronization circuit, the pulse has a constant width. This pulse width is the stage signal STG
It is determined by the time difference between STG 0 and STG7. Therefore, latch circuits 600, 602, 604 and 606, 608, 6
By changing the stage signal applied to 10, the pulse width can be adjusted and changed. This pulse width is determined in relation to the timing of the stages in Table 1. In other words, as shown in Table 1, the INTL stage has stage counters C0 to C.
2, C3 to C6 are allocated in the state of (1, 0), and are further allocated in the order of (1, 1), (1, 2), (1, 3), etc. every 8th stage. Since each stage is set to one microsec, an INHL stage is assigned every eight microsecs. In the INTL stage, the angle signal
Since it is necessary to detect the PC and control the incrementer, when the output PC of the angle sensor 98 is applied to the synchronization circuit shown in FIG. Make a pulse and based on this synchronized pulse PCS
Control the incrementer controller in the INTL stage. This synchronized angle signal PCS is also detected in stages ADV and RPM. This stage ADV
RPM is assigned each time the values of C3 to C6 count up by one in the states of stage counters C0 to C2, 3 and 6, respectively. The assigned stage rotates in a cycle of 8 microsecs. The STG0 signal in Figure 7 is the C of the stage counter.
Output when the value of 0 to C2 is 0, while STG7
is output when C0 to C2 have a value of 7. This output is produced independently of C3-C6. Therefore, the eighth
As can be seen from the figure, the synchronized angle signal PCS always has a varying pulse width from the value of 0 to the value of 6 for the stage counter outputs C0 to C2, and this pulse is detected by the stages INTL, ADV, and RPM, and the increment controller control. Detect synchronized reference PRS as above
CYL stage is stage counter output C0~C
When the reference pulse PR is input from the angle sensor 98, which is always assigned when the value of 2 is 2, the synchronized reference pulse PRS is always assigned to this input when the stage counter C0 to C2 is 2.
It is necessary for this to occur. The circuit in Figure 7 is STG
Since the pulse width is between 0 and STG7, this information is fully satisfied. Next, the VSP stage for detecting the wheel speed is assigned when the stage counter outputs C0 to C2 always have a value of 5. Therefore, it is sufficient that the synchronized PSS signal is output when the value of C0 to C2 is 5. In the circuit shown in FIG. 7, the values of C0 to C2 range from 0 to 6, so this value is satisfied. In figure 7
Instead of the STG0 signal, create a signal STG4 that always appears when the value of C0 to C2 is 4, and use this signal, and in addition to the signal STG7, a signal that always appears when the value of C0 to C2 is 6. STG6 may also be used. In this case, when the signal PS is input, the synchronization signal PSS is always output when the values of the stage counters C0 to C2 are 4 and 5. The stage cycle will now be explained.
In Table 1, stage counter outputs C0 to C6
128 types of stage signals with values from 0 to 127 are created, and when all of these signals have been generated, the large cycle is completed and a new large cycle begins again. This large cycle is further composed of 16 small cycles, and this small cycle is composed of 8 types of stage signals. This small cycle corresponds to the values of stage counter outputs C0 to C2 from 0 to 7, respectively, and is completed in 8 microsecs. The pulse outputs PR, PC, and PS from the sensor are reliably synchronized, and the synchronized pulses PRS, PCS, and PSS are
In order to reliably generate this, it is necessary that the output from the sensor has a pulse width longer than this short cycle. For example, the duty of the angular pulse becomes narrower as the engine rotates faster. For example, at 9000 rpm, it will be about 9 microsecs. Therefore, in order to achieve sufficient synchronization with respect to 9000 revolutions per minute, it is necessary to make this small cycle shorter than this, and in this embodiment it is 8 microsecs. Next, the operation of incrementer 478 shown in FIG. 4 will be explained. A detailed circuit of incrementer 478 is shown in FIG. As mentioned above, this incrementer has three functions: the first function is to increase the input data by a value of 1, the second function is to reset the input data, and the third function is to increase the input data by a value of 1. The function is a function that outputs input data as is. The incrementer function is performed by the ICNT signal, and the reset function is performed by the IRST signal.
When ICNT signal is high level, increment function, when low level, increment function,
When the IRST signal is high level, it becomes a reset function and the IRST signal has priority over the ICNT signal. The conditions may be selected based on the stage signals commanded by each process. The conditions include synchronized external input and the register group 504 of the second comparison result.
This is the output of Further, the conditions for transferring and writing data to the output register 474 are also similar to the conditions for the incrementer. FIG. 10 is a diagram explaining the processing of the fuel injection signal INJ. Since the start of injection differs depending on the number of cylinders, a register 442 acting as a CYL COUNTER counts the initial angular pulse INTLD generated from the reference signal PRS, and stores the result as a value related to the number of cylinders. There is
When compared with the CYL register 404 and when they are greater than or equal, the first register group 502 is
CYL FF 506 is set to 1, and CYLBF 508 of the second register group 504 is set to 1. With this CYL BF=1, CYL COUNTER44
2 is reset. Also, when CYL BF=1, the INJ TIMER 450 that measures the injection time is reset. Always unconditionally incremented by time, injection time set
Compare with INJD register 412, and if greater or equal, INJ FF522 of the first register group
is set to 1. Also, the second register group
INJ BF524 is set to 1. This INJ BF
When =1, increment by time is prohibited. This reversed output of INJ BF becomes the fuel injection time width, which becomes the valve opening time of the fuel injector. FIG. 11 is a diagram illustrating processing of signals that control ignition. By the initial angular pulse INTLD,
Register 452 acts as ADV COUNTER
is incremented by resetting and synchronized angle pulse PC being high. Then, compare it with the ADV register 414 that holds the ignition angle from INTLD, and if it is greater or equal, the first register 502
ADV FF 526 is set to 1, and ADV BF 528 of the second register 504 is set to 1. ADVD indicating the rise of ADV BF resets the DWL COUNTER 454, which starts energization, and is incremented when the synchronized angle pulse PC is at a high level. Then, it is compared with the DWL register 416 that holds the angle at which energization starts from the previous ignition position, and if the angle is greater or equal, the first register 502 is set.
The DWL FF 530 is set to 1, and the DWL BF 532 of the second register 504 is set to 1. The output of this DWL BF532 becomes the ignition control signal ING1. FIG. 12 is a diagram explaining EGR (NIDL) processing. Since these are all proportional solenoids, they perform duty control. maintain the cycle
Holds EGRP register 418 and on time
There are two EGRD registers 420, and
The TIMER is measured by EGR TIMER456. In processing, when processing the EGFP STG, the data held in the EGRP register 418 and the EGR TIMER 456 are compared, and if they are greater or equal, 1 is set in the EGRP FF 534 of the first register group 502. Set. Furthermore, the second register group 504
EGRP BF 536 is set to 1. When processing EGRD STG, unconditional non-increment or EGR with EGPR BF=1.
TIMER 456 is reset. EGRDFF5
38 is the EGRD register 420 and EGR TIMER4
56 and if the result is greater than or equal, it is set to 1 and EGRD_BF 540 is set to 1. The inverted output of this EGRD BF540 is the EGR control signal. The operation is similar to NIDL. Figure 13 shows the engine speed RPM (and vehicle speed).
FIG. The measurement method uses a certain measurement time width as RPMW.
It is determined by the TIMER 460 and obtained by counting the synchronized angle pulses PC within that time width. RPMW TIMER460, which measures time width,
is unconditionally incremented and also RPMW
It is reset when BF552=1. R.P.W.
BF550 is set to 1 because the RPMW register 426 that holds the time width and the RPMW
This is when the TIMER 460 is compared and the result is greater than or equal. RPMWD indicating the rise of RPMW BF552 causes the contents of RPM COUNTER 462 that counted the PC to be sent to RPM register 4 of output register 474.
Transfer to 30 and write. Also, RPMW BF5
When 52=1, RPM CONTER 462 is reset. VSP STG processing is also similar to RPM. Table 3 shows the functions of each register.

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【table】

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【table】

[Table] Next, a method for setting reference data in the reference register 470 will be explained. Register 402,4
04, 406, and 410 are set when the device of this embodiment is started. Once set, these values do not change. Next, data set in register 408 is performed by program processing. Data INJD representing the opening time of the fuel injector 66 is input to the register 412. This data INJD is determined, for example, as follows. Air flow meter 14 output signal
QA is taken through multiplexer 122 to analog-to-digital converter 124 . Here, the data is converted into digital data and held in a register (not shown). This data representing the amount of intake air and the fourth
Load data TP is obtained from the data held in the register 430 shown in the figure through calculation processing or information stored in a map form. Furthermore, the outputs of the intake air temperature sensor 16, water temperature sensor, and atmospheric pressure sensor are converted into digital data, and correction is performed based on this data and the operating state of the engine. Let this correction coefficient be K1. Furthermore, the battery voltage is also digitized, and correction is performed according to this data. This correction factor
Let it be TS. Correction is then performed by the λ sensor 80. Let this correction coefficient be α. In other words, data INJD is expressed as follows. In this way, the opening time of the fuel injector is determined.
However, the method shown here is just one example, and it is of course possible to define it using other methods. The register 414 contains data representing the ignition timing.
ADV is set. This data ADV is created, for example, as follows. Map-shaped ignition data θ with the above load data TP and rotation speed as factors
IG is held in the ROM 118 and determined from this map. Furthermore, starting correction, water temperature correction,
Add acceleration correction etc. In this way the data
ADV is created. The register 416 contains data DWL as data for controlling the primary current charging time of the ignition coil.
is set. This data DWL is the above data
It is calculated from the ADV value and the digital value of battery voltage. Data EGRP representing the period of signal EGR and data NIDLP representing the period of signal NIDL are set in registers 418 and 422, respectively. These data are predetermined. Data EGRD representing the energization width of the EGR valve (exhaust gas recirculation device) is set in the register 420. As the energization width increases, the valve opening ratio of the exhaust gas recirculation device increases, and the exhaust gas recirculation rate increases. For example, the data EGRD is in the ROM11 in a map state that factors the load data TP and rotation speed.
8. Furthermore, this data is corrected based on water temperature, etc. Data NIDLD representing the energization width of the air regulator 48 is set in the register 424.
This data is subjected to feedback control such that, for example, the rotational speed of the engine in a no-load state becomes a predetermined rotational speed, and is determined as the amount of feedback. Data RPMW and VSPW representing fixed time periods are set in registers 426 and 428, respectively, when the circuit of this embodiment is activated. In the above explanation, the output of the air flow sensor is used as an input factor to control the fuel injection amount, ignition advance angle, exhaust gas recirculation amount, etc. However, it is possible to use a sensor other than this air flow sensor as a sensor that indicates the state of the intake air. For example, a pressure sensor that detects intake manifold pressure may be used. Next, Table 4 shows the correspondence between the configurations of the invention described in the claims and the embodiments. It should be noted that this correspondence relationship is provided to aid understanding of the invention, and is not intended to limit the concept of the invention to one embodiment.

[Table] According to the present invention, when comparing the processing results of the computer with the counter value using a commonly used comparator, the frequency of use of the comparator is changed based on the influence of the output of the computer on the engine, etc. It is. As a result, sufficient control responsiveness can be ensured even though the comparators are commonly used. According to the embodiment described above, it further includes a reference register group, an instantaneous register group, and a comparison result holding register group, and connects each predetermined register of the register group to the comparison circuit based on the stage counter, and is used in many engines. Although it has a control function, it has the effect of making the circuit relatively simple.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram showing the positions of sensors and actuators in one embodiment of the present invention, FIG. 2 is an operation explanatory diagram for explaining the operation of FIG. 1, and FIG. 3 is an illustration of the control circuit of FIG. 1. Detailed diagram, Figure 4 is a partial detailed diagram of the input/output circuit in Figure 3, Figure 5 is an explanatory diagram of the operation of Figure 4,
Fig. 6 is a detailed diagram of the stage counter in Fig. 4, Fig. 7 is a detailed diagram of the synchronization circuit, Fig. 8 is an explanatory diagram of the operation of Fig. 7, Fig. 9 is a detailed diagram of the incrementer controller, and Fig. 10 is a detailed diagram of the stage counter in Fig. 4. Figure 11 is a diagram explaining the operation of fuel injection signal processing, Figure 11 is a diagram explaining the operation of ignition timing control, Figure 12 is a diagram explaining the operation of EGR or NIDL processing, and Figure 13 is a diagram explaining the operation of engine rotation speed RPM or vehicle speed VSP detection. It is an operation explanatory diagram. 10...Control circuit, 12...Air cleaner, 14
...air flow meter, 16...intake temperature sensor,
18... Throttle chamber, 20... Throttle valve, 22... Accelerator pedal, 24... Throttle position detector, 26... Intake manifold, 28... Exhaust gas recirculation device, 30... Engine, 32... Intake valve, 34... Combustion chamber, 36...spark plug, 38...distributor, 40...ignition coil, 42...
Bypass passage, 44...Idle adjust screw, 46...Bypass passage, 48...Air regulator, 50...Fuel tank, 52...Fuel pump, 54...Fuel damper,
56...Fuel filter, 58...Fuel return pipe, 60...Fuel pipe, 62
... Fuel pressure regulator, 64 ... Impulse pipe, 66 ... Fuel injector, 68 ... Pipe, 70 ... Canister, 72 ... Pipe, 74 ... Piston, 76
...Exhaust pipe, 78...Exhaust recirculation pipe (EGR pipe), 8
0...λ sensor, 82...catalytic converter, 84...exhaust temperature sensor, 86...muffler, 88...negative power supply terminal,
90... Positive power terminal, 92... Positive power terminal, 94... Cooling water, 96... Water temperature sensor, 98... Angle sensor,
PR...Reference signal, PC...Angle signal, 110
... battery positive terminal, 112 ... constant voltage circuit (output voltage PVCC), 114 ... (CPU) central processor, 116 ... (RAM) random access memory, 118 ... (ROM) read-only memory, 1
20...I/O circuit, 122...Multiplexer, 1
24...Analog-digital converter, 126...Pulse output circuit, 128...Pulse input circuit, 130...
Discrete input/output circuit, 132...filter,
134...filter, 136...filter, 138...
Filter, 140... Filter, 142... Amplifier,
144...Filter, 146...Atmospheric pressure sensor, 14
8...Tsena, 150,152,154...Resistance, 1
56, 158...Connection point, 160...Resistance, 162...
Data bus, 164... Address bus, 166... Control bus, 168... Filter, 170... Speed detector, 172... Filter, 174... Throttle switch (fully open), 176... Starter switch, 178... Gear switch, 180, 182,
184... Filter, 186... Power amplification circuit (fuel injection), 188... Power amplification circuit (ignition circuit),
194...Power amplification circuit (EGR), 196...Power amplification circuit (EGR OFF), 198...Power amplification circuit (NIDLE), 200...Power amplification circuit (fuel pump), 202...Power amplification circuit (catalyst alarm),
204...Power amplifier circuit (overheat), 20
6... Fuel pump, 208... Lamp (catalyst alarm),
210... Lamp (overheat), 402... Register, 404... Register, 406... Register, 4
08...Register, 410...Register, 412...Register, 414...Register, 416...Register,
418...Register, 420...Register, 422...
register, 424... register, 426... register, 428... register, 430... register, 43
2...Register, 442...Register, 444...Register, 446...Register, 448...Register, 4
50...Register, 452...Register, 454...Register, 456...Register, 458...Register,
460...Register, 462...Register, 464...
Register, 468...Register, 470...Reference register group (RF0), 472...Momentary register group (RF1), 474...Output register group (RF2), 47
6... Latch circuit, 478... Incrementer, 48
0...Comparator, 482...Comparator input terminal, 484...Comparator input terminal, 486
...Comparator output terminal, 490...Incrementer controller, 502...First comparison output register group (FFM), 504...Second comparison output register group (FFS), 506...Register (CYL), 508...Register (CYL), 510...Register (INTL), 5
12...Register (INTL), 514...Register (INTV), 516...Register (INTV), 518...
Register (ENST), 520... Register (ENST), 522... Register (INJ), 524... Register (IBJ), 526... Register (ADV), 52
8...Register (ADV), 530...Register
DWL), 532...Register (DWL), 534...Register (EGRP), 536...Register (EGRP),
538...Register (BGRD), 540...Register (BGRD), 542...Register (NIDLP), 544
...Register (NIDLP), 546...Register (NIDLD), 548...Register (NIDLD), 550
...Register (PPMW), 552...Register (PPMW), 554...Register (VSPW), 556
...Register (VSPW), 570...Stage counter, 572...Stage decoder.

Claims (1)

[Claims] 1 A calculation circuit that outputs digitally calculated data based on the state of the engine, a pulse output circuit that outputs pulses based on the data, and a control mechanism that controls the engine based on the pulses, The output circuit includes a plurality of holding means that hold electrical signals based on the above data;
at least one counter; a comparison means for comparing an electrical signal held in the holding means with an electrical signal representing the count value of the counter; A switching circuit that selectively applies one of the electrical signals to the comparison means and a periodic signal generation circuit that generates a plurality of periodic signals are provided, and the switching circuit selects one of the plurality of periodic signals for each one of the plurality of periods. One of the plurality of electrical signals held in the holding means is applied to the comparison means, and the other of the plurality of electrical signals is added to the comparison means every other period of the plurality of periods. An electronic control device for an internal combustion engine characterized by being added to comparison means.