JPS62168486A - Scramble decoder device - Google Patents

Abstract

PURPOSE:To make a clock pulse which is made a reference for a random number signal on decoder-side coincide in a number of pieces at all time with a clock pulse generating a random number signal on encoder-side by counting the clock pulse at timing of a horizontal synchronizing signal. CONSTITUTION:A scrambled video signal added to a signal line 31 is supplied to a synchronizing separator circuit 32, a descrambler circuit 33, and a data separator circuit 34. The circuit 32 separates a horizontal synchronizing signal 35 and a vertical synchronizing signal 36, and supplies a signal 39 synchronizing with the horizontal synchronizing signal 35 to a clock pulse generator 40. A pulse 42 generated by the generator 40 is supplied o a random number generator 43 as a clock pulse for generating a random number signal, but at the same time supplied to a counter which is reset by the vertical synchronizing signal. By the output of this counter 41, the number of pulses generated by the generator 40 is so controlled as coming to be equal to that of the clock pulses generating random numbers on encoder-side.

Description

Detailed Description of the Invention [Technical Field 1 of the Invention] The present invention relates to a scramble decoder device that descrambles a scrambled video signal into an original normal video signal, and in which the synchronization signal in the scrambled video signal is inaccurate due to noise or the like. Even if it cannot be extracted, the 117 reading information for descrambling can be reliably reproduced.

[Technical background of the invention ξ1] In recent years, with the development of new broadcasting media, teletext, still image broadcasting, high-definition television broadcasting, and multi-channel broadcasting using digital signals have become possible. ：With the advancement of broadcasting media, the types of transmission of broadcast programs are becoming more diverse.

Then, the broadcasting station charges for a specific program, and allows subscribers other than those who have signed a contract with the broadcasting station to agitate the transmitted signal, performing so-called scrambling and viewing the program. Paid broadcasting is performed for paid programs, which prevents the content from being scrambled and allows subscribers to view the programs by canceling the scrambling.

When descrambling and viewing such scrambled (encrypted) information, the subscriber will be required to use public information called AIA (T1) along with the subscriber's unique identification code (ID). The program is reserved and notified to the broadcasting station. This gives the subscriber the key to unscrambling. On the other hand, on the broadcasting station side, W? to unscramble the ID information and Ti information. By keeping the reading information confidential and downloading it to the subscriber side, the subscriber can use this secret information to obtain the key to unscrambling, that is,
Generate the same information as the decoding information from the broadcasting station and darken it]
In other words, it is possible to convert digitized information into plain text.

The above-mentioned encryption methods include methods such as synchronous compression, synchronous offlet, video inversion, and line swapping, but the circuit described below will be explained using a circuit that uses line swapping.

FIG. 4 shows an example of the configuration of an encoder that encrypts a video signal, and a video signal that is a pay broadcast signal is introduced into the signal fQ1.

This video signal is input to the sync separation circuit 2 and also to the scramble circuit 3. In the synchronization separation circuit 2, a horizontal synchronization signal 4 included in the video signal is used to generate a clock signal that serves as a reference for scrambling processing.
is extracted. This horizontal synchronization signal 4 is supplied to a counter 6 which receives a basic clock signal 5. counter 6
The output cuff is input to a clock pulse generation circuit 8 which generates a clock pulse 10 for generating a predetermined random number signal from a random number generator 9 at a subsequent stage.

The random number generator 9 is constituted by, for example, a pseudo-random pulse generation circuit such as a PN signal, and is supplied with initial value data 12 from an initial value generator 11 that provides the initial value. Therefore, by setting the data 12 from the initial value generator 11 as the initial value of the random number generator 9, the random number generator 9 can control the scrambling control that changes randomly according to the initial I'lII value data. The low value 13 is supplied to the scrambling circuit 3.

The specific configuration of the scramble circuit 3 is, for example, when the input video signal is low analog, the input analog 1Δ
A converter that converts the signal into a digital signal, an image memory into which the signal from this converter is sequentially input (ρ) in units of one line, and a control signal from the random number generator 9 to determine the order in which the image memory is read out. 4111 consists of a translation address generator, etc. that randomly changes the address based on the address. thus,
A scrambled video signal is output from the scramble circuit 3.

The output 14 of the scramble circuit 3 is the data superimposition circuit 15
It is assumed that one of the inputs is J. Initial value data 12 from the initial value generator 11 is input to the other input of the f-event superimposing circuit 15 as decoding information for descrambling, and the data superimposing circuit 15
includes scrambled video signal and initial value data /υ
It sends out pay broadcast signals (scrambled video signals).

On the other hand, on the receiving side, a scramble decoder as shown in FIG. 5 is configured.

FIG. 5 shows an example of a conventional decoder, and 16 is a signal line to which a scrambled video signal (from the transmitting side) is supplied. The received scrambled video signal from the signal line 16 is sent to the synchronous separation circuit 17J3 and the descrambling circuit 1.
8 and is also supplied to a data mantissa calculation circuit 19 that handles initial value data from the scrambled video signal. A synchronization separation circuit 17 extracts a horizontal synchronization signal 20 from the scrambled video signal and supplies its output 20 to a counter 21 . A reference clock signal 22 that matches the clock timing on the transmitting side is input to the counter 21, and the counter 21 counts this reference clock signal 22 a predetermined number of times per horizontal scanning period and sends an output 21a to the clock pulse generation circuit 23. input. The clock pulse generation circuit 23 supplies its output pulse 24 to a random number generator 25.

Further, the data separation circuit 19 to which the scrambled video signal is input handles initial value data 26 from the scrambled video signal and supplies this data 26 to the random number generator 25. As a result, the control signal 2 for desk simple on the decoder side
7 is generated by the random number generator 25. By introducing this control signal 27 into the descrambling circuit 18, the scrambled video signal is descrambled and output.

FIGS. 6(A) and 6(8) are explanatory diagrams showing the operation of FIG. 4, and FIGS. 6(A) and 6(B) collectively show a time chart 17 of the operation for a predetermined field.

(a) shows a vertical synchronization signal, in which the interval between vertical synchronization pulses Vp is one field. (b) shows the horizontal synchronization signal obtained from the synchronization separation circuit 17, and (C) shows the clock pulse 21a from the counter 21 obtained by using the horizontal synchronization signal (b) as a ret pulse. In this way, the counter 21 obtains a clock pulse 24 whose phase is synchronized with the horizontal synchronizing signal of the sent scrambled video signal. When this clock pulse 24 is supplied to the random number generator 25, it is a descrambling control signal with a period of a predetermined number of fields based on the initial value data extracted from the data separation circuit 19, which is preset in the random number generator 25. 27 is generated. Figure (d) shows the control signal 27, and shows a signal for one cycle of a predetermined number of fields from the first field after initialization. That is, the first field is, for example, [01011...10
10'', the signal in the next field is rol
"lo..." signals are generated sequentially. Of course, this signal coincides with the scramble control signal 13 on the transmitting side.

[Problems in the background art] In conventional circuits, if the transmitted signal can be treated as a synchronous signal or if noise etc. occur, the number of clock pulses 24 on the decoder side generated during one field period is smaller than that on the encoder side. As a result, a problem arises in that the random numbers generated from the random number generator 25 are different on the transmitting side and the receiving side. If the number of clock pulses that serve as the reference for the random number signal differs between the encoder and decoder sides, it will not be possible to correctly descramble the video until the next initialized field. The video of the field period and the video signal of the next field are disturbed one after another.

Figure 6(e) shows the random number signal on the decoder side when the horizontal synchronization signal can be handled in the first field where initialization is performed, as shown by the dotted line in Figure (b), and Figure (C) shows the random number signal on the decoder side. As shown in J, since the horizontal synchronization signal is centered, the number of pulses from the clock pulse generator 23 decreases, and the random number signal shown in Figure (CI) and the random number signal shown in Figure (e) no longer match. .

[Object of the Invention] The present invention has been made in view of the above-mentioned points, and even if a scrambled video signal has a synchronization signal removed due to noise or the like or a pseudo synchronization signal increases, the encoder side can An object of the present invention is to provide a scramble decoder that can generate a clock pulse for random number generation that matches the following.

[Summary of the Invention] In order to achieve the above object, the present invention generates an encoder-side random number signal for scrambling using a clock pulse that is generated a specified number of times in each field, and generates a scrambled video signal based on this random number signal. In a scramble loader device that encodes data according to a random number signal generated on the decoder side, the clock serving as a reference for the random number signal on the decoder side is determined at the timing of the vertical synchronization signal from the synchronization separation means that separates the synchronization signal from the scrambled video signal. The generated pulses from the pulse generating means are sent to Curran 1, and if this count (direct) is different from the specified number that matches the number of clock pulses for generating a random number signal on the encoder side, the output is output from the pulse generating means. The number of pulses is adjusted to a specified number.

[Embodiments of the invention] Hereinafter, the present invention will be described with reference to illustrated embodiments.

FIG. 1 is a circuit block diagram showing one embodiment of a scramble decoder according to the present invention, FIG. 2 is a circuit diagram showing details of FIG. 2, and FIG. 3 is an explanatory diagram showing the operation of FIG. 1. It is.

In FIG. 1, reference numeral 31 indicates a signal line not shown in FIG. 3 to which a scrambled video signal from a scramble encoder is supplied, and the signal from this signal line 31 is transmitted to a synchronization signal separation circuit 32. The signal is supplied to a descrambling circuit 33 and a data separation circuit 34.

The synchronization separation circuit 32 handles a vertical synchronization signal 36 from the scrambled video signal other than the horizontal synchronization signal stand 35, and the horizontal synchronization signal 35 is obtained by counting and inputting the reference clock signal 37 via the fall detection circuit 71. This signal is supplied to the first counter 38 as a reset signal. As a result, the first counter 38 outputs a signal 39 that is phase-synchronized with the horizontal synchronization signal of the video signal on the transmitting side, and is supplied to the clock pulse generator 40 at the next stage. The pulse 42 generated from the clock pulse generator 40 is used as a clock pulse for generating a random number signal.
3. Note that the clock pulse generator 40
is driven by the reference clock signal 37.

On the other hand, the vertical synchronization signal 36 obtained from the synchronization signal separation circuit 32 is supplied as a reset signal to the second counter 41 provided in this embodiment via the rise detection circuit 72. The second counter 41 is clocked with pulses 42 from the clock pulse generator 40, and the output 45 of the second counter 41 that counts the pulses 42 is the number of pulses generated by the clock pulse generator 40. is input to a pulse number control circuit 46 that controls the pulse number. Further, the output of the rise detection circuit 72 is also supplied to the pulse number control circuit 46.

The pulse number control circuit 46 registers in advance the number of clock pulses specified for one field, for example, and the set pulse number n□ and the second counter 41
Comparing the pulse error r1 indicated by the output 45 from
If n > nl, a signal 47 is supplied to the clock pulse generator 40 to compensate for the deficiency in the number of clock pulses 42. On the other hand, when n = n1, the signal 4
8, the second counter 41J3 and the random number generator 4
The supply of clock pulses 42 to 3 is prohibited. Also, n
If o'<nl, the clock pulse 42 is decreased by the increment.

Note that the data separation circuit 34 handles initial value data 49 set on the transmitting side, which is included in the scrambled video signal, and supplies this data 49 to random number generation 2:43. The random number generator 43 generates a random number signal 50 whose cycle is a predetermined number of field periods based on the data 49, and supplies this to the descrambling circuit 33 as a control signal for descrambling.

FIG. 2 is a circuit diagram showing in detail the connection configuration of the clock pulse generator 40 and pulse number control circuit 46 of FIG. 1.

The clock pulse generation circuit 40 is composed of a decoder 73 and a logic circuit 74. The decoder 73 decodes the output 39 of the first counter 38 (creates the base of fiQ42). Gate 75,2
It is composed of a human power gate 76 and three human power or gates 77. The pulse number control circuit 46 also includes a D flip-flop 78. The output terminal of the decoder 79 is connected to the input terminal of a D flip-flop 78 via a Nantes gate 80, 81, and one output terminal of the flip-flop 78 is connected to the
0, and the other end is connected to the other input end of an OR gate 82 whose one input end is supplied with the vertical synchronizing signal 36. Here, the output of the D flip-flop 78 corresponds to the signal 48, and when this signal 48 passes through the OR gate 82, a signal 47 is output from the same gate 82, and this signal 47 has one input terminal connected to the reference clock signal 37.
is input to the other input terminal of the Nant gate 76 to which is supplied, and is also input to one input terminal of the AND gate 75. With this configuration, the reference clock signal 37 and the clock pulse 42 are selected according to the signal 47.

The output of this Nant gate 76 is supplied to one input terminal of an OR gate 77 at the subsequent stage. The OR gate 77 receives a signal from the AND gate 75 which outputs the AND of the signal from the decoder 73 and the signal 47 at its other input terminal, and the D flip-flop 78 at its remaining input terminal.
A signal 48 from . As a result, orgate 7
7 performs enable/disable control for the signals selected by the preceding circuits 75 and 76. Note that the signal input from the rising edge detection circuit 72 to the pulse number control circuit 46 is input to the Nandogoo 1.81.

The present invention is constructed as described above, and its operation will be explained next.

FIGS. 3(A) and 3(B) are waveform diagrams illustrating the operation when a horizontal synchronizing signal can be handled in the above embodiment;
A) and (B) collectively show waveforms for a predetermined field.

The diagrams commonly shown in each of (A) and (B) (a> indicates the vertical synchronization signal, field period 52 indicates the first field of the period of the random number signal on the transmitting side, and 53 indicates the next field. , 54 further indicates the following fields.
) indicates a horizontal synchronizing signal, and the horizontal synchronizing signal is missing in the field period 52 (see dotted line). Diagram (C)
shows the pulse 42 generated by the clock pulse generator 40, and FIG. 3(d) shows the signal 48 generated by the pulse number control circuit 46. Also, figure (e) shows the signal 47, figure (f) shows the random number signal 50 on the decoder side, figure (
a) shows the random number signal 13 on the encoder side. Note that 55 indicates a period one field before the initial field 52.

Before the period 52, if there is no abnormality in the number of synchronization signals, the second counter 41 generates the same number of count outputs as the first counter 38, so the pulse number control circuit 46 internally When it is detected that the number matches the specified number set in , a pulse 56 shown in FIG. 4(d) is generated in the signal 48. This pulse 56 is shown in FIG.
As is clear from comparison with b), it begins to occur immediately after the end of the last horizontal synchronizing pulse 57 of one field, and continues until the vertical synchronizing pulse VP of the next field ends. While this pulse 56 is being generated, the clock pulse generation circuit 40 outputs the pulse 42.
can be controlled so that it does not occur.

The random number goes around and reaches the first field 52, and J5 is in this field, and there are 3 missing horizontal synchronizations, so 58
Assuming that the clock pulse generating circuit 40 generates the clock pulse 42, the clock pulse generating circuit 40 generates three or one less clock pulses 42 than the specified number. By counting this pulse 42 G:L by the second counter 41'c, the pulse number control circuit 46 detects that there is a shortage of three pulses. This causes the control circuit 46 to control the signal 47
When these five pulses are supplied, the clock pulse generator 40 generates three pulses 6 as shown in FIG.
0 during the vertical synchronization pulse, and the random number generator 43
send to. Therefore, the random number generator 43 generates a random number signal different from that on the encoder side in the field where the horizontal synchronizing pulse occurs, but the missing pulse 60 is compensated for in the vertical synchronizing signal period, so that the next field (53 )
Therefore, the decoder side random number signal can be generated in the same pattern as the encoder side random number signal pattern. Here, when the pulse number control circuit 46 detects that the number of pulses is less than the specified number, it outputs a signal 48.
The last horizontal pulse 56 of
Pulse 5 after 0 is stiffened by pulse generation 'r: i40
6 is generated. 61 indicates this delayed pulse.

The above describes the operation when the horizontal synchronization signal can be handled. However, if the horizontal synchronization signal increases artificially due to noise, etc., pulse 5 due to signal 48, etc.
It is sufficient to set 1 to advance the time of 6.

In this way, the present invention can accurately descramble a scrambled video even when the l'i'1111Il signal cannot be obtained accurately due to synchronization signal distortion or noise.

13. The above embodiment describes an example of application to a scrambling method using random replacement of scanning lines.
It is also applicable to other scrambling methods, for example, when synchronous compression is controlled using a random number signal.

[Effects of the Invention] As described above, according to the present invention, even if there is an abnormality in the number of synchronization signals of a scrambled video signal, descrambling can be performed accurately.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a scramble decoder device according to the present invention, FIG. 2 is a detailed circuit diagram of FIG. 1, FIG. 3 is an explanatory diagram showing the operation of FIG. 1, and FIG. The figure is a circuit block diagram showing a scramble encoder device related to the present invention, FIG. 5 is a circuit block diagram showing a conventional scramble decoder device, and FIG. 6 is a circuit block diagram showing the operation of FIG. 4.
It is an explanatory diagram. 32... Synchronization separation circuit, 33... Descrambling circuit, 34... Data separation circuit, 38.41... Counter, 40... Clock pulse generator, 43... Random number generator, 46 ...Pulse number control circuit.

Claims (1)

[Claims] An encoder side random number signal for scrambling is generated by a specified number of clock pulses generated in each field, and a video signal scrambled based on this random number signal is generated according to a random number signal generated on the decoder side. In the scramble decoder device for decoding, a synchronization separation means separates a synchronization signal from the scrambled video signal; a reference clock is counted at the timing of the synchronization signal outputted by the synchronization separation means, and a reference clock is used as a reference for the decoder-side random number signal. pulse generating means for generating a clock pulse, counter means for counting pulses from the pulse generating means in field periods, and an output from the counter means being input, and a counted value of the counter means for one field period. is compared with a preset number that matches the number of pulses in one field period of the encoder side random number signal, and a control signal to be generated according to the comparison result is supplied to the pulse generating means to generate the pulse. A scramble decoder device comprising: pulse number control means for adjusting the number of pulses to the specified value; and random number generation means driven by clock pulses from the pulse generation means to generate the decoder side random number signal.