JP2001069136A - Video signal processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal processing system for scrambling or descrambling the analog transmitted video information. SOLUTION: As for an analog component video signal including a Y/U/V signal component, the analog video signal is enciphered by exchanging signals between respective signal components and inverting the polarities of respective signal components. Scramble information showing timing of exchange or polarity inversion between signal components (which signal components is exchanged and when or which timing the signal component is exchanged or polarity is inverted) is placed on the enciphered analog video signal while utilizing a synchronizing signal (vertical blanking interval VBI). On the basis of the scramble information (descramble keys (a)-(f) in the VBI), the respective signal components of the enciphered analog video signal are deciphered into the original analog video signal by exchanging signals and/or inverting polarities.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing system for preventing a video program requiring copyright protection from being illegally used or illegally copied.

[0002] In particular, video which performs scrambling and descrambling which can cope with an analog video signal (progressive analog component video signal, etc.) in a form in which a conventional analog video copy protection system (such as a macrovision system) cannot be used. The present invention relates to a signal processing system.

[0003]

2. Description of the Related Art In the industry dealing with a new generation video / audio program (AV program) such as DVD video or DVD audio, as a method for preventing illegal use or illegal copy of video information including audio information,
Digital signal encryption methods have been proposed.

A typical example of the digital signal encryption method is as follows. That is, when video information including audio information reproduced by a DVD video player or a DVD audio player is transmitted to another device using IEEE 1394, a) is involved in mutual authentication processing between devices on a network using IEEE 1394. Exchange of encryption keys for "encryption or decryption";b> Transmission of digital video information encrypted with the above encryption keys, thereby preventing unauthorized use or unauthorized copying by other devices connected to the network. Can be performed.

Further, a cable T employing a billing system
In analog signal transmission used in V and the like, a scrambled (encrypted) analog signal is delivered to all data distribution destinations. In such a cable TV system, key information for decrypting a code is sent to a household that has made a billing contract by using a different route (such as mailing) from the analog signal transmission cable. By using this key information, only households that have made a billing contract can enjoy descrambled (restored) clean video (audio).

[0006]

A) The process of encrypting and restoring digital information is complicated and expensive.

For example, when transmitting encrypted digital video information according to IEEE 1394, very high-level encryption processing is performed so as not to be easily decrypted. For this reason, the circuit scale for performing the encryption and the restoration and the exchange of the encryption key becomes large, and the equipment cost jumps.

[0008] B) It is necessary to newly provide a digital terminal in the conventional video equipment having an analog video terminal as standard equipment.

That is, most video equipment such as existing TVs, VCRs and video cameras (camcorders) have analog video terminals (RCA type terminals) for composite video signals or luminance and color signals as input / output connection terminals. The S terminal for separate video signal which is separated from the standard is provided as standard.

However, in order to use an existing digital signal encryption technology such as transmission of encrypted information according to IEEE 1394, a new digital signal input / output terminal must be added to a conventional video device. Increases costs.

C) The reliability of security for analog signal encryption is low.

In an existing system (cable TV or the like) for transmitting an encrypted analog signal, the encryption key information must be sent to the contract partner through an individual route such as mailing, which requires a great deal of transmission of the encryption key information. costly.
In addition, the reliability of encryption key information delivery is low, for example, the encryption key information may be lost during mailing.

Further, in the above-mentioned mailing method of the encryption key information, it is difficult to frequently deliver the encryption key information, so that the same encryption key information may be used for a long time. Then, it becomes possible for a hacker to take a long time to decrypt the code, and once the code is decrypted, there is a problem that the code is illegally used or copied for a long period of time.

The object of the present invention is also applicable to analog video equipment having no digital signal input / output terminal, so that separate mailing of encryption key information is not required, and IEEE1394 is not required.
It is an object of the present invention to provide a video signal processing system capable of performing scrambling or descrambling of video information transmitted in analog without increasing the circuit scale as in the case of (1).

[0015]

In order to achieve the above object, a video signal processing system according to the present invention uses a component video signal (Y / U / V signal; Y / Cb / Cr signal; Y / Pb / Pr signal). ) Or three primary color signals (R / G
/ B signal), a signal is exchanged (shuffled) between each signal component (Y / U / V) and / or each signal component (Y / U) for an analog video signal including a plurality of signal components.
/ V), the analog video signal is encrypted (scrambled / encoded) by inverting one or more polarities.

A synchronizing signal (VBI) for synchronizing the signal components (Y / U / V) forms the signal component (Y / U / V).
V).

The scramble information indicating the timing of switching between signal components or the timing of reversing the polarity (which signal component was switched or inverted at what timing and when) is provided by a synchronization signal (vertical blanking period VBI).
, And can be added to the encrypted analog video signal.

Each signal component (Y / U / V) of the encrypted analog video signal can be received in synchronization with the synchronizing signal (to prevent Y / U / V from being received at different timings). .

Further, each signal component (Y / U / V) of the encrypted analog video signal is synchronized with the synchronization signal based on the scramble information (scramble descramble keys a to f in VBI). At the timing, the signals are exchanged (reverse shuffle) and / or the polarity is inverted, and restored (descrambled / decoded) to the original analog video signal.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video signal processing system according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram for explaining an outline of a video signal processing system according to an embodiment of the present invention.

In FIG. 1, an analog signal information processing apparatus 1 means a key station for transmitting an analog video signal, and represents, for example, the inside of a cable transmission station of a cable TV or a wireless TV broadcasting station.

The analog signal information processing device 30
It shows a device in which a TV receiver or STB (Set Top Box) and a TV for screen display are integrated. The analog signal information processing device 30 includes an analog signal information processing device 4.
0 is connected.

The analog signal information processing device 40 is a device such as an optical disk device or a VCR capable of recording and reproducing.
It is composed of an analog video signal recording device. In the analog signal information processing device 40, the encrypted analog signal is recorded as it is.

The analog signal information processing apparatus 30 is connected to another analog signal information processing apparatus A51 and an analog signal information processing apparatus B52 via an analog signal information transmission path 46.

An analog signal information processing apparatus 1 which is a cable transmitting station of a cable TV or a wireless TV broadcasting station
The video signal to be broadcast is extracted from the analog video signal generator 2, encrypted by the analog signal encryption unit 3, and transferred to the analog signal information / command information synthesis unit 6.

The scramble signal (scramble information) used for the encryption at this time is generated by the scramble signal generator 4. At the same time, the scramble signal generator 4
Then, information necessary for performing key decoding (restoration) of an analog signal in the analog signal information processing device 30 is created from the generated scrambled signal, and transferred to the command information processing unit 5.

The command information processing section 5 converts the transferred information necessary for key decoding (restoration) into a command format for transmission. The command information created here is combined on the time axis with the previously encrypted analog video signal information in the combining section 6 for analog signal information and command information.

The information obtained by combining the encrypted analog video signal information and command information is transmitted from the transmission / reception switching unit 8 via the analog signal transmission unit 11 in the analog signal information transmission unit 7 to the analog signal information transmission path. 9 and delivered to the analog signal information processing device 30.

The analog signal information transmission path 9 is a CATV
In the case of such a wired connection, a coaxial cable or an optical cable is used. In the case of wireless, the analog signal information transmission path 9 is a wireless broadcast path such as a terrestrial wave or a satellite broadcast wave.

The analog signal information transmission path 9 is a one-way or two-way communication path.

When the analog signal information transmission path 9 is bidirectional, the transmission / reception switching unit 8 switches the transmission system and the reception system for the analog signal information transmission path 9 by time division.

The transmission / reception switching unit 8 transmits the analog signal information transferred from the analog signal transmission unit 11 at the time of transmission, and transmits the command-related information returned along the analog signal information transmission path 9 at the time of reception. Transfer to the extraction unit 10.

The command information extracting unit 10 decodes the information sent from the transmission / reception switching unit 8, extracts a return value (status) for the command, or sends the command from the analog signal information processing device 30. The command contents and its parameters are interpreted, and the result is transferred to the command information processing unit 5.

In the command information processing unit 5, based on the information sent from the command information extraction unit 10, the current status (status) of the analog signal information processing device 30 and the contents of the request from the analog signal information processing device 30 (command)
The processing is performed according to.

If necessary according to the processing situation, the command information processing unit 5 creates a new command for the analog signal information processing device 30 and combines the created command information with the analog information signal and the command information. The analog signal information is synthesized by the unit 6 and transmitted to the analog signal information transmission path 9 via the analog signal transmission unit 11.

As one of the exchanges of the command information, "exchange of related information relating to an encryption key" used for mutual authentication processing and decryption between analog signal information processing apparatuses.
There is.

The encrypted analog video signal information and command information transmitted via the analog signal information transmission path 9 are input to the analog signal information transmission unit 20 of the analog signal information processing device 30.

As described above, when the analog signal information transmission path 9 can perform bidirectional transmission, the transmission information from the analog signal information processing device 30 is transmitted to the command information insertion unit 22.
Is transferred to the analog signal information transmission path 9 via the.

Switching between transmission and reception in the analog signal information processing device 30 is performed by the transmission / reception switching unit 21.

On the analog signal information processing apparatus 30 side, the analog signal information encrypted by the analog signal information extracting section 24 is extracted from the received information, and the command information is extracted by the command information extracting section 23.

The command information on the receiving side extracted here is decoded by the command processing section 27. When it is necessary to return a response command to the analog signal information processing device 1 or a return value (status) to a previously transmitted command, the information is sent from the command information processing unit 27 to the command information insertion unit 22. Sent to
The signal is returned to the analog signal information processing device 1 via the transmission / reception switching unit 21.

For example, when common scramble information is shared between the analog signal information processing apparatuses 1 and 30 before decrypting (restoring) the encrypted analog video information signal, the common scramble information is shared. At the time of mutual authentication required for realization, it is necessary to perform bidirectional command exchange processing between the analog signal information processing apparatuses 1 and 30 a plurality of times.

As shown in the example of FIG. 1, when a scrambled signal is created by the scrambled signal generator 28 in the analog signal information processor 30, the scrambled signal is used to recover the analog signal (decryption unit). At 25, the encrypted analog video signal information transferred from the analog signal information extraction unit 24 is restored (decrypted).

The restored (decrypted) analog video signal information is supplied to an analog video information display unit 26 (TV for displaying a normal NTSC signal or PAL signal).
On a CRT or a liquid crystal display).

The analog video signal information thus decrypted (decrypted) is encrypted again by the analog signal encryption section 29, and predetermined command information is added by the analog signal information / command information synthesis section 33. You. The analog video signal that has been encrypted again and to which the command information has been newly added can be appropriately transmitted to the analog signal information transmission path 46 via the analog signal information transmission unit 35.

Next, a case where the restored (decrypted) analog video signal information is recorded in the recording device 40 will be described.

As shown in FIG. 1, the analog signal information processing device 30 includes an analog signal information processing device (recording device).
40, a plurality of analog signal information processing devices A51
And B52 are connected.

The plurality of analog signal information processing apparatuses A
The analog signal information transmission path 46 connecting 51 and B52 may be a conventional composite analog video cable or analog video cable for S terminal, or may be a multi-line video cable for component video or analog RGB.

The multiple analog signal information processing apparatus (4) shown in FIG.
0, 51, 52), the procedure for selecting the recording device 40 and selectively transmitting the analog video signal information is as follows, for example.

FIG. 2 is a flowchart for explaining the transmission processing of analog signal information in the video signal processing system of FIG.

First, the command information processing section 27 sets “SLOT_I” for declaring the start of transmission of an analog video signal.
D command "is generated to declare the start of transmission of analog signal information (step ST10).

Thus, the analog signal information transmission path 46 is transmitted from the command information processing unit 27 to the analog signal information transmission path 46 via the analog signal information / command information combining unit 33, the analog signal transmitting unit 31, and the transmission / reception switching unit 34. SLOT_I
D command "is sent out.

The SLOT_ID command includes, as parameters, analog signal information transmission declaration information and receiving device designation information for specifying the recording device 40 this time.

Applicable analog signal information processing device 40
Receives this command, issues an SLOT_ID (ID for identifying a session performing each different transmission process) corresponding to the analog video signal information transmission process, and issues an analog signal information reception request (step S).
T12).

Then, the device (in this case, 40) that has made the analog signal information reception request assertion requests the analog signal information processing device 30 to check whether the device is a partner that the analog signal information processing device 30 desires to transmit. A mutual authentication process is performed with the analog signal information processing device 40 (step ST14).

Specifically, the analog signal information processing device 40
Is transmitted to the analog signal information processing devices 30 to 40 (step S).
T16) It is checked whether or not the information can be decoded by the analog signal information processing device 40, and then the mutual authentication process is performed by a challenge-response process that performs the reverse.

Note that information decoding in the analog signal information processing device 40 is performed by the command information processing unit 42, and the decoding result (response) is transmitted to the analog signal information transmitting unit 4.
1. The signal is returned to the command information processing unit 27 of the analog signal information processing device 30 via the analog signal information transmission path 46, the transmission / reception switching unit 34, and the command information extraction unit 32. Based on the returned response, the command information processing unit 27 can confirm whether the other party (in this case, the analog signal information processing apparatus 40) that sent the response is "the other party who desires transmission".

When the mutual authentication processing is completed, information for generating a scramble signal (scramble information) is transmitted (step ST16), and scramble information common to the analog signal information processing devices 30, 40 is transmitted based on the information. Is created (step ST18).

As a specific method, a) a part of the scrambled signal (or basic information for generating the scrambled signal) is simultaneously sent to each other at the time of the challenge / response processing performed in step ST14, and is mutually sent to each other. A method of creating common scramble information from the received information; b) sharing the information based on the scramble information in advance between the analog signal information devices 30 and 40;
A method in which both generate common scramble information based on information transmitted by one of the two.

When the common scramble information is created by the scramble signal generation unit 28 through the above processing, the analog video information restored by the restoration unit (decryption unit) 25 for the analog signal Encrypting section 29 performs encryption again using the common scramble information (step ST20).

The resulting encrypted analog video signal information is combined with the command information created by the command processing unit 27 in a combination unit 33 of analog signal information and command information. The encrypted analog video signal with command information thus synthesized is sent to the analog signal transmitting unit 3
1. The signal is transmitted to the analog signal information processing device 40 via the transmission / reception switching unit 34 (step ST22).

The analog signal information processing device 40 decrypts (decrypts) the encrypted analog video signal information with a common scramble signal (step ST24). The restored analog video signal is recorded by the analog signal information recording unit 43 on an information storage medium (not shown) such as a DVDRAM disk.

In the above description, examples of common scramble information include, for example, information on bit strings a to f described later with reference to FIGS.

The above is an example in which the analog video signal information descrambled can be recorded by the analog signal information processing device 40 (for example, the system CGMS-A that manages the copy generation of this analog video signal information is used once) Copying is permitted).

When the descrambled analog video signal information cannot be recorded by the analog signal information processing device 40 (when the system CGMS-A that manages the copy generation of the analog video signal information does not permit copying).
In the analog signal information device 40, the scrambled (encrypted) analog video signal information is recorded as it is on an information storage medium (not shown).

Note that CGMS-A (Copy Generation Ma)
nagement System -Analog; copy generation management system
(Analog) is well-known (Technical Report of the Institute of Image Information and Television Engineers, May 22, 1997; ITE Technical Report Vol. 21, No. 31, pp. 21-26; Tadashi Ezaki et al .; "CGMS Using VBI- A transmission method ”).

FIGS. 3A to 3E are views for explaining the contents of the vertical blanking period (VBI) of the analog video signal used in the video signal processing system of FIG. here,
An example of a format of transmission information (including command information) TI transmitted between the analog signal information processing apparatuses of FIG. 1 is shown. In this example, command information is transmitted during the tenth to thirteenth and seventeenth to twentieth scanning line periods in the vertical blanking period VBI during the video information transmission period VTP.

FIG. 4 shows the vertical blanking period (VB
It is a figure explaining the example of the command code contained in I).

In the allocation of transmission users within the vertical blanking period (VBI), the slot-ID creation start declarer is given the right to determine a specific period, and the Command Line Control
The allocation is notified by the trol command (FIG. 4).

However, in the case of a simple command transmission in which a plurality of commands are not processed in parallel at the same time and only one command is exchanged with a return value (status), the command sender side performs the 10th to 13th scans. The same command is repeatedly transmitted four times using a line.

In this case, the command status respondent (the side returning the return value) uses the seventeenth to twentieth scanning lines, and similarly returns the same contents four times.

The command information is transmitted in a 272 bit data packet DP structure. The actual command information is contained in a 176-bit command data block CDB, and a slot ID for specifying a unique session; SLID; a transmitting device for recognizing a transmitting device so that a plurality of commands can be simultaneously executed in parallel. ID; TRID,
Information such as a receiving device ID; REID for designating a transmission destination, a command code CMCD indicating the contents of a command, and a command parameter CMPR indicating information on the command can be sent.

Since the size of the command data block CDB is as small as 176 bits, when transmitting a large amount of information in the command format, it is necessary to transmit the information in several steps. Therefore, the serial number SCSN in the same command is also transmitted to indicate the number of times information about the same command is sent.

In the example of FIG. 3, line numbers 10 and 273 in the VBI include command information issued by the command sender (master), and line numbers 11 and 274 in the VBI indicate command status respondents (slaves). It can be configured to include command information issued by the side.

The command information in the format of FIG. 3 has the following features: * Command information is transmitted during the vertical blanking period (VBI) of video signal information; * Vertical blanking period ( VBI), one piece of command information is transmitted in each scanning line period; in the vertical blanking interval (VBI), the same command information (command content and command parameter) for each scanning line period * The command information is not transmitted in the character signal multiplexing period (scanning lines of the 14th to 16th and 21st line numbers in VBI); * Return value for command Is returned in the same command format (in this case, the discrimination between the transmission system from the sender / command issuer and the transmission system from the reply side / return value responder is based on the command parameter * Regarding the assignment of the command transmission user within the command transmission available period within the vertical blanking interval (VBI), Slot_ID
For a specific period after the creation start declarer has made the Slot_ID creation start declaration, the allocation decision right is given to the Slot_ID creation start declarant.

FIG. 5 is a block diagram illustrating a specific example of the analog signal encryption unit (scramble encoder) 29 of FIG.

The analog video signal input section 61A of FIG.
In FIG. 1, it corresponds to, for example, an analog signal restoring unit (decryption unit) 25.

The analog video signal output unit 62 shown in FIG.
A corresponds to, for example, the analog signal transmission unit 31 in FIG.

In FIG. 5, a scramble signal generator 2
The scramble signal generated in 8 is input to the M-sequence random number generator 65A as an initial value for random number generation. The random number generator 65A generates an M-sequence random number based on the input initial value in accordance with the timing of the horizontal blanking period (horizontal synchronization timing) of the video signal from the analog video signal input unit 61A.

The generated random numbers are input to the switching information storage section 64A. The switching information storage unit 64A is constituted by a shift register and a latch flip-flop circuit.

In the switching information storage unit 64A, the input M-sequence random number information is stored in the shift register in accordance with the timing (horizontal synchronization timing) of the horizontal blanking period of the video signal from the analog video signal input unit 61A. The bits are sequentially shifted, and the result is latched in a flip-flop circuit. The bit strings a to f of the random number information thus latched are transferred to the analog video signal switching unit 63A as a scramble signal (scramble information).

The six bit string signals (af) transferred from the switching information storage unit 64A to the analog video signal switching unit 63A are synchronized with the synchronization signal generated by the synchronization signal generation unit 66. Be changed.

As a specific example of the synchronizing signal generated by the synchronizing signal generator 66, there is a signal in the vertical blanking period VBI shown in FIG. In this case, the six bit string signals (a to f) transferred from the switching information storage unit 64A to the analog video signal switching unit 63A are based on the field or frame of the video signal from the analog video signal input unit 61A.
Can be changed.

Alternatively, six bit string signals transferred from the switching information storage unit 64A to the analog video signal switching unit 63A in synchronization with the division of each horizontal scanning line line number in the VBI (ie, at the horizontal synchronization timing). It is also possible to change (af).

Basically, six bit string signals (a to f)
Can be set at any time according to the content of the synchronization signal (VBI) from the synchronization signal generation unit 66.

In the configuration shown in FIG. 5, the synchronizing signal (VBI) generated by the synchronizing signal generating section 66 is output in synchronization with the scanning line timing of the video signal from the analog video signal input section 61A, and the analog video signal is scanned. It is set so as to be switched for each line (a constant value is maintained in each scanning line of the analog video signal).

In the analog video signal switching section 63A, each signal component (luminance Y) of the video signal from the analog video signal input section 61A is based on the scramble information (bit strings a to f) transferred from the switching information storage section 64A. The signal, the color difference U or Cb signal, the color difference V or Cr signal) are exchanged (or shuffled) for each scanning line.

[0099] The analog video signal switching section 63A receives the analog video signal input section 61A based on the transferred scramble information (bit strings a to f).
The polarity of any one or more of the signal components (Y / U / V) of the video signal from the video signal is inverted for each scanning line.

The video signal from the analog video signal input section 61A is encrypted (scrambled) by replacing the signal components (Y / U / V) and / or inverting the polarity.

Further, in the analog video signal switching section 63A, the V signal including the scramble information (bit strings a to f) is output.
BI information (for example, command parameter C in FIG. 3E)
MPR including information of bit strings a to f) is added to any one (arbitrary one or two, or all three) of each of the scrambled signal components (Y / U / V). It has become.

FIG. 6 is a block diagram for explaining a specific example of the analog signal restoring section (scramble decoder) 25 shown in FIG.

The circuit configuration of the analog signal restoration section (decryption section) 25 in FIG. 6 and the analog signal encryption section 29 in FIG.
And the switching information storage units 64A / 64B) can be similarly configured.

The analog video signal input unit 61B shown in FIG.
FIG. 1 corresponds to, for example, the analog signal information extracting unit 24.

The analog video signal output unit 62 shown in FIG.
B is, for example, an analog video information display unit 26 in FIG.
Alternatively, it corresponds to the analog signal encryption unit 29.

Now, assume that the analog video signal encrypted by the analog signal encryption unit 29 of FIG. 5 is input to the analog video signal input unit 61B of FIG.

In this case, each signal component (Y / U / V) of the encrypted (scrambled) video signal is input from the analog video signal input unit 61B to the analog video signal switching unit 63B.

The VBI (containing the bit strings a to f in FIG. 5) added to the encrypted (scrambled) video signal is input from the analog video signal input unit 61B to the scrambled signal generation unit 28. Is done. The scramble signal generator 28 extracts the information of the bit strings a to f (scramble descrambling key) from the input VBI and transfers it to the switching information storage 64B.

The switching information storage unit 64B latches information of the bit strings a to f from the scramble signal generation unit 28 at the synchronization timing (horizontal synchronization timing or vertical synchronization timing) of the video signal from the analog video signal input unit 61B. The information of the latched bit strings a to f is supplied to the analog video signal switching unit 63B as a descrambling key (descrambling key).

The analog video signal switching section 63B converts each signal component (Y / U / V) of the encrypted (scrambled) video signal based on the supplied descrambling keys (bit strings a to f). To restore the signal.

That is, the analog video signal switching unit 63B
Then, the supplied descrambling keys (bit strings a to
Based on f), each signal component (Y / U / V) of the encrypted (scrambled) video signal is replaced (or reverse-shuffled) for each scanning line (to return to the original state). ).

[0102] The analog video signal switching section 63B outputs the signal components (Y / U) of the video signal based on the supplied descrambling keys (bit strings a to f).
/ V), the polarity of the encrypted (scrambled) signal component is inverted for each scanning line (to return to the original state).

The video signal from the analog video signal input unit 61B is restored (de-scrambled) by exchanging the signal components (Y / U / V) and / or inverting the polarity.
Is done.

The amplitude and pedestal level (black level) of each signal component (Y / U / V) of the video signal input to the analog video signal input unit 61B are determined according to the degree of loss in the analog signal transmission path. It may have changed from the original signal. When the amplitude and pedestal level (black level) of each signal component (Y / U / V) of the video signal changes,
Since the white balance of the restored video signal differs from the white balance of the original signal, it is necessary to restore the white balance.

For this reason, the analog video signal switching section 63B shown in FIG. 6 is provided with a gain control section (AGC amplifier) for automatically correcting the amplitude of each signal component (Y / U / V) of the video signal, or each signal component (AGC amplifier). An offset control unit for automatically correcting the pedestal level of (Y / U / V) is appropriately provided.

FIG. 7 is a diagram illustrating a specific example of the analog video signal switching unit (shuffle circuit) 63A of FIG.

The original unscrambled analog video signals (analog component video signals) are supplied to terminals T11 to T13 in FIG. 7, respectively. The signal components of the luminance Y, the color difference U (Cb), and the color difference V (Cr) supplied to these terminals are inverted by inverters (polarity inverting circuits) INV11 to INV13. Such luminance Y, color difference U (Cb), color difference V (Cr) and their polarity inversion signals are guided to terminals T21 to T23 via the switch circuit of FIG.

The selection state of each switch in FIG. 7 is determined by encryption key information composed of a set of six bit strings a to f. With the bit strings a to f, if the selected state of each switch is, for example, the dotted line state shown in the figure, the Y signal of the terminal T11 is guided to the terminal T23 (temporary V terminal)
The U (Cb) signal at terminal T12 is led to terminal T21 (temporary Y terminal), and the V (Cr) signal at terminal T13 is fed to terminal T2.
2 (temporary U terminal).

If scrambled, provisional Y = Y,
Although the temporary U = U (Cb) and the temporary V = V (Cr), the temporary Y = U (Cb) and the temporary U =
V (Cr), provisional V = Y.

The analog video signal information (temporary Y, temporary U, temporary V) encrypted in this way is transferred to the analog video signal output unit 62A of FIG.

In the above example, Y, U (Cb) and V (Cr)
In the case where there is no polarity inversion, Y, U (Cb) and V (Cr) whose polarity has been inverted can be output to the terminals T21 to T23 depending on the contents of the bit strings a to f.

The bit strings a to f are obtained from the switching information storage section 64A of FIG. The contents (0/1) of the bit strings a to f are switched for each scanning line (horizontal or vertical) of the analog video signal in accordance with the timing of the horizontal scanning line of the original analog video signal (a constant within each scanning line). Value).

In the example of FIG. 7, of the 6-bit encryption key (scramble key), the polarity inversion state is controlled by the first 3 bits (a to c), and each of the subsequent 3 bits (d to f) is controlled. The signal component (Y / U / V) is controlled to be in a shuffle state (signal path exchange state).

FIG. 8 is a diagram illustrating a specific example of the analog video signal switching unit (reverse shuffle circuit) 63B of FIG.

The encrypted analog video signal information (temporary Y, temporary U, temporary V) from the terminals T21 to T23 in FIG. 7 is supplied to the terminals T32 to T33 in FIG. 8, respectively.

At this time, the encryption key information (a set of six bit strings a to f) used for scrambling the video signal information (temporary Y, temporary U, temporary V) supplied to the terminals T32 to T33 is The signal is transferred to and stored in the switching information storage unit 64B of FIG. 6 by the VBI of the signal. The set of the six bit strings a to f stored in the switching information storage unit 64B determines the switch selection state of the switch circuit in FIG.

In the case of the switch selection state illustrated in FIG. 8, the provisional Y (U in the example of FIG. 7) supplied to the terminal T31 is used.
(Cb)) is a gain / offset adjusting unit G / OF11.
After passing through the switch circuit, it is led to the terminal T42 via the switch circuit in the illustrated state.

The temporary U supplied to the terminal T32 (FIG. 7)
V (Cr)) is the gain / offset adjustment unit G
After passing through / OF12, it is led to a terminal T43 via a switch circuit in the illustrated state.

Similarly, the provisional V (Y in the example of FIG. 7) supplied to the terminal T33 is a gain / offset adjusting unit G / OF.
After passing through 13, through the switch circuit in the state shown,
It is led to the terminal T41.

Thus, the Y signal of the original analog component video signal is output to the terminal T41 in FIG. 8, and the U signal of the original analog component video signal is output to the terminal T42.
(Cb) signal is output, and the V (Cr) signal of the original analog component video signal is output to the terminal T43.

In the example of FIG. 8, of the 6-bit encryption key (descramble key), the last 3 bits (d to f) are used.
Controls the reverse shuffle state (replacement state of signal paths) of each signal component (Y / U / V), and the first three bits (a to
In c), the polarity inversion state is controlled.

Here, G / OF11 to G / OF3 in FIG.
3 is the state of the analog transmission path, INV11 to INV2
Pedestal level (black level) by reversing process 3
Offset adjustment function that restores the signal that has no longer returned to its original state, and gain adjustment function that restores the signal whose amplitude from the pedestal level to the signal peak level has shifted to the original amplitude due to differences in the signal attenuation rate in the analog transmission path, etc. have. (If the pedestal level / peak level of Y / Cb / Cr deviates, the white balance of the decoded video signal may be lost, and the tone of the original video signal may not be reproduced.) G / OF11 to G / OF33 Can be basically constituted by one high-speed operational amplifier having a gain adjusting resistor circuit. An FET in which the internal resistance between the drain and the source changes with the voltage applied to the gate can be used for the gain adjustment resistor circuit. That is, the drain-source resistance of the FET is controlled by its gate voltage,
The gain of the high-speed operational amplifier can be adjusted.

Further, a DC bias is applied to the input side of the high-speed operational amplifier for offset correction. The FET internal resistance control gate voltage applying unit and the offset DC bias voltage supplying unit are connected to a MPU in the analog signal information processing device via a DAC (not shown).
(Not shown).

Prior to performing the encoding (encoding) / decoding (decoding) processing, the reference video signal is once passed through the analog signal information transmission path 9 or 46 in FIG. The mechanism is such that the gate voltage for controlling the internal resistance of each FET and the offset DC bias voltage are automatically adjusted so that the operation values in the OF11 to G / OF 33 are optimized.

Since the baseband of a high-resolution video signal is very wide, encryption at the baseband level has conventionally been considered difficult. However, in the configurations of FIGS. 7 and 8, only an analog switch (the speed of adjusting the gain / offset may be lower than the inversion speed of the inverter) is used as a high-speed device required for encryption. Analog baseband encryption is possible.

The high-speed analog switch may be an inexpensive high-speed switch used in large quantities in automatic teller machines (ATMs) and the like.

Further, since the configuration of the encryption (scramble) encoder and the decompression (de-scramble) decoder is very small as shown in FIGS. A decoding circuit can be realized.

FIG. 9 is a block diagram for explaining a modification of the analog signal information processing device 30 of FIG.

In FIG. 9, the analog signal restoration unit (decryption unit) 25 of FIG. 1 is treated as a part of the receiving apparatus 201, and the analog signal encryption unit 29 of FIG. The unit 33 is the video output device 20
3 as part of And the receiving device 20
1 and the flow of input signals to the video output device 203 and their operation timings are controlled by the control unit 202. The other components in FIG. 9 functionally correspond to the components in FIG. 1 that are assigned the same reference numerals.

FIG. 10 is a diagram for explaining an example of the internal configuration of the video output device 203 of FIG. Each signal component (Y / U / V) of the analog video signal before being encrypted is first input to a signal switching circuit (shuffle circuit) 206. This signal switching circuit 206, in FIG.
Ｆf corresponds to a switch network controlled to be switched.

The signal switching circuit 206 receives scramble keys (af) from a control circuit (a circuit for performing timing / sequence control of each unit) 209 and receives an analog video signal at a predetermined timing (horizontal synchronization timing or vertical synchronization timing, etc.). The signal path of each signal component (Y / U / V) of the signal is exchanged (shuffled). Each signal component of the shuffled analog video signal (Y / U / V)
Is input to a polarity inversion circuit (inverter circuit) 207. In FIG. 7, the polarity inversion circuit 207 corresponds to the inverters INV11 to INV13 connected to a switch group that is switched and controlled by the encryption key information a to c.

The polarity inversion circuit 207 receives the scramble keys (a to f) from the control circuit 209 and determines the signal polarity of at least one of the signal components (Y / U / V) of the analog video signal at a predetermined timing. (Horizontal synchronization timing or vertical synchronization timing, etc.). Each signal component (Y / U / V) of the polarity-reversed analog video signal is
The signal is input to the synchronization signal (VBI) adding circuit 208.

The synchronizing signal adding circuit 208 generates a synchronizing signal (V) used for restoring the encrypted analog video signal.
BI).

The synchronizing signal adding circuit 208 is
9 receives a scramble key (a to f) from a predetermined position (a command parameter CMPR portion in the example of FIG. 3E) of the generated synchronization signal (VBI).
.. F), and the VBI with scramble key is added to the video signal in which each signal component (Y / U / V) is shuffled / inverted. The video signal to which such a VBI has been added is input to a synthesizing section (scramble signal adding circuit) 33 for analog signal information and command information.

The analog signal information / command information synthesizing section 33 receives predetermined command information from the command information processing section 27 in FIG. 9 and converts the received command information into a VBI command information transmission area from the synchronization signal adding circuit 208. (CITA in FIG. 3B) in the format of FIG.

Thus, the VBI including the predetermined command information and the scramble information (scramble keys a to f)
Is output from the synthesizing unit 33 for analog signal information and command information.

The video signal can be encrypted by either signal shuffling by the signal switching circuit 206 or signal polarity inversion by the polarity inversion circuit 207. Therefore, the polarity inversion circuit 207 can be omitted in the case of encryption using only the signal shuffle, and the signal switching circuit 206 can be omitted in the case of encryption using only the signal polarity inversion.

FIG. 11 is a diagram for explaining an example of the internal configuration of the receiving apparatus 201 in FIG. Each signal component (Y / U / V) of the encrypted analog video signal is first input to the synchronization signal circuit 211.

The synchronizing signal circuit 211 converts each signal component (Y / U / V) of the encrypted analog video signal into
The synchronization signal (V) into which the scramble keys (af) are inserted
BI) are separated. The separated VBI is supplied to a control circuit (a circuit for performing timing / sequence control of each unit) 2
15 is input.

The control circuit 215 extracts the descrambling keys (a to f) having the contents corresponding to the scramble information (a to f) used at the time of the encryption from the input VBI, and outputs a signal switching circuit (an inverse shuffle circuit). 213) and the inversion / non-inversion selection circuit 212.

The signal switching circuit 213 receives the descrambling keys (a to f) from the control circuit 215, and receives each signal component (Y / U / Y / U / U) of the analog video signal at a predetermined timing (horizontal synchronization timing or vertical synchronization timing, etc.).
The signal path of V) is exchanged (reverse shuffle). Each signal component (Y / U / V) of the analog video signal returned to the original state by the reverse shuffling is input to the inversion / non-inversion selection circuit 212. This signal switching circuit 213
In FIG. 8, it corresponds to a switch network controlled to be switched by the encryption key information d to f.

The inversion / non-inversion selection circuit 212 receives one or more signal polarities of each signal component (Y / U / V) of the analog video signal based on the descrambling keys (a to f) from the control circuit 215. At a predetermined timing (horizontal synchronization timing, vertical synchronization timing, or the like). Each signal component (Y / U / V) of the analog video signal returned to the original polarity state by the polarity inversion is applied to a gain / offset adjustment circuit (or gain control AGC circuit) 2.
14 is input. This inversion / non-inversion selection circuit 212
In FIG. 8, inverters INV21 to INV21 connected to a group of switches that are controlled to be switched by the encryption key information ac.
It corresponds to INV23.

The gain / offset adjusting circuit 214 receives each signal component (Y / U / Y / U / A) of the analog video signal which has been returned to the original state after the reverse shuffling and / or the polarity inversion processing.
V), the pedestal level is automatically adjusted and / or the amplitude of each signal component (Y / U / V) is automatically adjusted.

This gain / offset adjustment circuit 214
8 corresponds to the gain / offset adjustment units G / OF11 to G / OF33 connected to the switch group switched and controlled by the encryption key information d to f in FIG.

In this way, the analog component video signal restored to the original state (shuffled video signal) is output from the gain / offset adjustment circuit 214.

FIG. 12 shows a specific example of the inverter (corresponding to INV11 to INV13 in FIG. 7 or INV21 to INV23 in FIG. 8) constituting the polarity inversion circuit 207 in FIG. 10 or the inversion / non-inversion selection circuit 212 in FIG. It is a figure showing an example of a circuit.

In FIG. 12A, an analog inverting amplifier having a gain of “−1” is provided, and its input or output is switched and selected by an inverting / non-inverting selection switch to output an inverted or non-inverted analog output. It is something to take out. A part (a, b, or c) of the encryption key information in FIG. 7 or FIG. 8 can be used as a switching control signal (scramble information) for controlling the switching selection state of the inversion / non-inversion selection switch.

On the other hand, FIG. 12B shows an inverting / non-inverting amplifier (balanced input / output) having a gain of “1” and having a positive-phase input / output (+1) and a negative-phase input / output (−1). Differential amplifier). The inverting / non-inverting amplifier is switched and selected between the positive-phase output and the negative-phase output by an inverting / non-inverting selection switch, and an inverted or non-inverted analog output is extracted. A part (a, b, or c) of the encryption key information in FIG. 7 or FIG. 8 may be used as a switching control signal (scramble information) for controlling the switching selection state of the inversion / non-inversion selection switch. it can.

In an actual amplifier, the gain (gain) of the inverting / non-inverting amplifier may not coincide with that of the inverting output side due to manufacturing variations. Even when the positive-phase output gain and the negative-phase output gain are not equal, this gain difference can be canceled by providing the AGC circuit function (in the gain / offset adjustment circuit 214 in FIG. 11) thereafter.

In order to accurately correct the amplitude of an image signal with the gain control amplifier having the AGC circuit function, information indicating one or a plurality of reference levels is included in a scramble signal (part of VBI). Can be. For example,
The reference level for the white level and the reference level for the black level are V
It can be embedded in BI. If the AGC circuit function is calibrated based on these reference levels and then the reversal process is performed to restore the video signal subjected to the polarity reversal scrambling, the video signal whose brightness, contrast, white balance, etc. are the same as those before encryption are obtained. Can be restored (descrambled).

FIG. 13 is a diagram for explaining the waveform of an analog video signal whose polarity has been inverted (encrypted) by the polarity inversion circuit 207 in FIG. 10 or the inverters 2037 to 2039 in FIGS.

In FIG. 13A, the difference S6 between the pedestal level (black level) S1 of the video signal before the polarity inversion and the pedestal level (black level) S4 of the video signal after the polarity inversion is the image signal portion S2a. Is set to be larger than the white peak amplitude S7a. The synchronization signal S3 of the video signal before the polarity inversion is detected at the threshold level S8, and the synchronization signal S5 of the video signal after the polarity inversion is set at the threshold level S8.
9 is to be detected.

On the other hand, in FIG. 13B, the difference S6 between the pedestal level (black level) S1 of the video signal before the polarity inversion and the pedestal level (black level) S4 of the video signal after the polarity inversion is the image signal. White peak amplitude S7 of portion S2b
It is set smaller than b. The synchronization signal S3 of the video signal before the polarity inversion is detected at the threshold level S8, and the synchronization signal S5 of the video signal after the polarity inversion is detected at the threshold level S9.

If S6> S7a as shown in FIG. 13A, the synchronizing signal S3 or S5 will be at the threshold level S8.
Alternatively, it can be reliably detected in S9.

However, as shown in FIG. 13B, S6 <S
7b, at the threshold level S9, in addition to the synchronization signal S5, the white peak amplitude S7b of the image signal portion S2b
There is a possibility that the part is erroneously detected. When this erroneous detection occurs, for example, the analog video signal switching unit 63B of FIG.
The scramble descramble keys (a to f) having the correct contents cannot be given at the right timing, and the encrypted video signal cannot be restored.

From the above, the difference S between the pedestal level S1 before the polarity inversion and the pedestal level S4 after the polarity inversion is obtained.
6 needs to be larger than the white peak amplitude S7a of the image signal portion S2a.

FIG. 14 is a diagram for explaining a signal exchange pattern (shuffle pattern) in the signal switching circuit 206 of FIG. 10 or the shuffle circuit 63AA of FIGS.

As shown in FIGS. 5 to 8, the encryption key is composed of 6 bits (a to f), and 3 bits (d to
When the signal shuffle pattern is specified in f), up to eight patterns can be distinguished by these 3 bits.

FIG. 14 illustrates a case where six types of shuffle patterns are specified by the above three bits (d to f).

That is, the three input ports (T11 to T13 in FIG. 7) of the analog video signal switching unit (63A in FIG. 5 or FIG. 7) for performing signal shuffling are changed according to the signal exchange state in FIG. Pattern 1 to pattern 6 are defined. A signal having a pattern corresponding to any of these six patterns is supplied to three output ports (T2 in FIG. 7).
1 to T23).

In addition, the three input ports (T31 to T33 in FIG. 8) of the analog video signal switching unit (63B in FIG. 6 or FIG. 8) for performing the signal reverse shuffling are switched according to the signal exchange state in FIG. Pattern 1 to Pattern 6
Is defined. A signal having a pattern corresponding to any of these six patterns is output from three output ports (T41 in FIG. 8).
To T43).

The output port patterns 1 to 6 in FIG. 14 correspond to the three signal components (Y / U / V) of the video signal without any overlap or excess / shortage.

FIG. 15 is a view for explaining a specific circuit example (1) of the video output device 203 of FIG.

Each signal component Y, U, V of the digital component video signal before being encrypted is, for example, a signal switch network having a circuit configuration as shown in FIG. 7 (three digital signals are switched here). Is input to the shuffle circuit 63AA having.

The signal components Y, U, and V of the digital component video signal shuffled by the circuit 63AA (with no overlapping or excess or deficiency between the signals) are converted to digital / digital signals, respectively.
Analog converter (hereinafter abbreviated as DAC) 203
4, 2035, and 2036 convert the signal into a corresponding analog video signal component. The analog video signal component (encrypted analog video signal) thus converted is sent to the video signal output unit 62A.

The synchronization signal (VBI) including the scramble information used for the shuffling is supplied to the synchronization signal adding circuit 6.
It is generated by the synchronization signal generator 66 in 3AB. The generated synchronization signal (VBI including the scramble information) is added to one of the shuffled signal components (YUV) (for example, Y) by the synchronization signal addition circuit 2031.

The synchronizing signal (VBI) can include a descrambling key (descramble key) for restoring the shuffled (scrambled) signal components (YUV), and a decryption unit (decryption unit). 1 or 6 also includes a synchronization signal (horizontal synchronization signal / vertical synchronization signal) for enabling the three scrambled signal components (YUV) to be received at the same timing.

By the way, when a synchronizing signal is put on a specific signal component before shuffling (for example, a Y signal component before shuffling), when a shuffling operation is performed on three kinds of video signal components in the shuffling circuit 63AA, the Y signal and the synchronizing signal are output. Is also shuffled, and the receiving device (decryption side) cannot detect the synchronization signal.

Therefore, after the shuffling operation in the shuffling circuit 63AA, the video signal of the predetermined channel (whether the signal component of this channel becomes Y or not).
It is uncertain whether it will be V or V). Thus, the receiving apparatus can detect a synchronization signal riding on a video signal (Y, U, or V) of a predetermined channel with a conventional configuration. The scramble information in the VBI is read based on the clock reproduced from the detected synchronization signal, and the restored (decrypted) video can be reproduced based on the scramble information.

Note that the above-mentioned channel is a channel of a physical transmission path for transmitting any one of the components Y, U, and V of the component video signal. In this example, three channels are prepared. Whether the signal component passing through each of these three channels is Y, U or V is
It depends on the content of the encryption (signal shuffle state) and cannot be generally specified.

FIG. 16 is a view for explaining a specific circuit example (part 2) of the video output device 203 of FIG.

In the configuration of FIG. 16, the synchronization signal (VBI) is
15 in that it can be added to a plurality of signal components (any two or all of Y, U, and V).

In the configuration of FIG. 16, a synchronizing signal (VBI) can be added to all three types of video signal components. In this way, the VBI can be detected from any of the signal components after the shuffling, so that the receiving device (decryption side) can detect the synchronization signal riding on the video signal in the conventional configuration, and based on that, Can be played (restored).

In the configuration of FIG. 16, since the VBI can be detected from any of the signal components after shuffling, the position of the shuffling circuit 63AA and the position of the synchronization signal adding circuit 63AB may be exchanged.

FIG. 17 is a view for explaining a specific circuit example (part 3) of the video output device 203 of FIG.

The configuration of FIG. 17 is obtained by replacing the shuffle circuit 63AA of FIG. 15 with an inverter circuit 63AC. That is, in FIG. 15, the video signal is encrypted by replacing (shuffling) a plurality of signal components, whereas in FIG. 17, the video signal is encrypted by inverting the polarity of the plurality of signal components.

By the way, when a synchronizing signal is put on a specific signal component before the polarity inversion (for example, a Y signal component before the polarity inversion), when the polarity inversion operation is performed on the three kinds of video signal components in the inverter circuit 63AC, the Y signal is output. The polarity of the synchronization signal is also inverted, so that the reception device (decryption side) cannot detect the synchronization signal.

Therefore, after the polarity inversion operation in the inverter circuit 63AC, a synchronization signal is added to the video signal of the predetermined channel. As a result, the receiving apparatus can detect a synchronization signal riding on a video signal of a predetermined channel and reproduce (restore) a video based on the synchronization signal in a conventional configuration.

FIG. 18 is a view for explaining a specific circuit example (part 4) of the video output device 203 of FIG.

The configuration of FIG. 18 has a configuration in which the shuffle circuit 63AA of FIG. 15 is inserted between the input unit 61D of FIG. 17 and the inverter circuit 63AC.

That is, in FIG. 15, the video signal is encrypted by exchanging a plurality of signal components (shuffling).
In FIG. 18, the video signal is encrypted by inverting the polarity of the plurality of signal components, whereas in FIG. 18, the encryption is performed using both the switching (shuffle) of the plurality of signal components and the polarity inversion.

Note that a method other than the configuration shown in FIG. 18 may be used as a method that uses both the switching (shuffling) of a plurality of signal components and the polarity inversion. That is, the inverter circuit 63AC is arranged after the input unit 61D, and the shuffle circuit 63AC is
A method of arranging AAs is also possible.

FIG. 19 is a view for explaining a specific circuit example (part 5) of the video output device 203 of FIG.

In the configuration of FIG. 19, the synchronization signal (VBI) is
It differs from the configuration of FIG. 18 in that it can be added to a plurality of signal components (arbitrary two or all of Y, U, and V).

In the configuration shown in FIG. 19, a synchronization signal (VBI) can be added to all three types of video signal components. In this way, the VBI can be detected from any of the signal components after the shuffling, so that the receiving device (decryption side) can detect the synchronization signal riding on the video signal in the conventional configuration, and based on that, Can be played (restored).

In the configuration shown in FIG. 19, since the VBI can be detected from any of the signal components after shuffling, the positions of the shuffling circuit 63AA, the inverter circuit 63AC, and the synchronization signal adding circuit 63AB can be arbitrarily exchanged. You may.

FIG. 20 is a view for explaining a specific circuit example (part 6) of the video output device 203 of FIG.

For example, in the configuration of FIG. 15, the spotlight shines on the addition of the synchronization signal necessary for the synchronous reception of the encrypted analog component video signal.
In the case of 0, the synchronization signal (VBI) including the scramble information used for the encryption is spotlighted.

That is, the scramble information (FIG. 7) used for signal shuffling in shuffle circuit 63AA.
In other words, bits d to f) of the encryption key information a to f are generated from the control circuit 63AE. This scramble information is inserted into the synchronizing signal (VBI), and added to any one of the shuffled signal components (YUV) (for example, Y) by the addition circuit 2041 in the scramble information addition circuit 63AD.

FIG. 21 is a view for explaining a specific circuit example (part 7) of the video output device 203 of FIG.

The configuration of FIG. 21 is different from that of FIG. 20 in that a synchronization signal (VBI) including scramble information can be added to a plurality of signal components (arbitrary two or all of Y, U, and V).
Configuration is different.

In the configuration shown in FIG. 21, a synchronization signal (VBI) including scramble information can be added to all three types of video signal components. By doing so, the VBI can be detected from any of the signal components after shuffling, so that the receiving device (decryption side) can detect the synchronization signal riding on the video signal in the conventional configuration, and scramble based on it. The information can be extracted and the encrypted video can be played back (restored).

In the configuration of FIG. 21, since the VBI including the scramble information can be detected from any of the signal components after the shuffle, the position of the shuffle circuit 63AA and the position of the scramble information addition circuit 63AD may be exchanged.

FIG. 22 is a view for explaining a specific circuit example (No. 8) of the video output device 203 of FIG.

The configuration of FIG. 22 is obtained by replacing the shuffle circuit 63AA of FIG. 20 with an inverter circuit 63AC. That is, in FIG. 20, the video signal is encrypted by replacing (shuffling) a plurality of signal components, whereas in FIG. 22, the video signal is encrypted by inverting the polarity of the plurality of signal components.

Incidentally, a synchronization signal (VBI) is added to a specific signal component before the polarity inversion (for example, the Y signal component before the polarity inversion).
When the polarity inversion operation is performed on three types of video signal components in the inverter circuit 63AC, the polarity of the synchronization signal (VBI) is also inverted with the Y signal,
The receiving device (decryption side) cannot detect the synchronization signal (VBI).

Therefore, after the polarity inversion operation in the inverter circuit 63AC, a synchronization signal (VBI) is added to the video signal of the predetermined channel. As a result, the receiving apparatus can detect the synchronization signal (VBI) riding on the video signal of the predetermined channel in the same configuration as the conventional apparatus, and scramble information (encryption key information in FIG. Bits a to c) are extracted from a to f, and the encrypted video can be reproduced (restored).

FIG. 23 is a view for explaining a specific circuit example (No. 9) of the video output device 203 of FIG.

The configuration of FIG. 23 has a configuration in which the shuffle circuit 63AA of FIG. 20 is inserted between the input unit 61D of FIG. 22 and the inverter circuit 63AC.

That is, in FIG. 20, the video signal is encrypted by exchanging a plurality of signal components (shuffling).
In FIG. 23, the video signal is encrypted by inverting the polarity of the plurality of signal components, whereas in FIG. 23, the encryption is performed by using both the switching (shuffle) of the plurality of signal components and the polarity inversion.

Then, the scrambling information (encrypted key information a to f in FIG. 7) used for the encryption is generated from the control circuit 63AE. This scramble information is inserted into the synchronizing signal (VBI), and added to any one of the shuffled signal components (YUV) (for example, Y) by the addition circuit 2041 in the scramble information addition circuit 63AD.

Note that a method other than that shown in FIG. 23 may be used as a method for simultaneously using the exchange (shuffle) of a plurality of signal components and the polarity inversion. That is, the inverter circuit 63AC is arranged after the input unit 61D, and the shuffle circuit 63AC is
A method of arranging AAs is also possible.

FIG. 24 is a view for explaining a specific circuit example (No. 10) of the video output device 203 of FIG.

The configuration shown in FIG. 24 is a synchronizing signal (VBI) having scramble information (a to f; which includes both polarity inversion scramble information ac and shuffle scramble information df) used for encryption. Can be added to a plurality of signal components (arbitrary two or all of Y, U, and V).

In the configuration shown in FIG. 24, the synchronization signal (V) having scramble information (a to f) in all three video signal components
BI) can be added. In this manner, the VBI scramble information (a to
f) can be detected. Therefore, on the receiving device side (decryption side), the synchronizing signal (V
BI), the scramble information (af) can be detected, and the video can be reproduced (restored) based on the scramble information (af).

In the configuration of FIG. 24, VBI can be detected from any of the signal components after shuffling, so that the positions of shuffle circuit 63AA, inverter circuit 63AC, and scramble information adding circuit 63AD can be arbitrarily exchanged. You may.

However, in the configuration of FIGS. 20 to 24, the position of scramble information adding circuit 63AD is (V
It is desirable to place it on the DAC 2034-2036 side (in that the BI is not shuffled or inverted).

In the examples of FIGS. 15 to 24, it is assumed that the video signal before encryption is a digital component signal reproduced from, for example, a DVD player. Each component of these digital component signals (Y / U /
V) is shuffled or inverted and encrypted at the digital signal stage, and then passed through DACs 2034 to 2036 to become an encrypted analog component signal. If the video signal before encryption input to the input unit 61D in FIGS. 15 to 24 is already analog, the DACs 2034 to 2036 are not required.

FIG. 25 is a view for explaining a specific circuit example (1) of the receiving apparatus 201 of FIG.

The configuration shown in FIG. 25 restores (descrambles / descrambles) the analog component video signal encrypted (scrambled / shuffled) by the video output device 203 having the configuration shown in FIG. 15 or FIG.

In FIG. 25, three video signal components (Y / U /
Sync separation circuits 2011 to 2013 are connected to each of the three channels for individually transmitting V). These sync separation circuits 2011 to 2013 have the same circuit configuration, and the video signal components (Y,
U or V), the synchronization signal (VBI) is detected.
The synchronization signal (VBI) is extracted.

A synchronization signal (VBI) extracted by any one (one, two, or three) of the synchronization separation circuits 2011 to 2013 is input to a synchronization detection circuit 2014.

Synchronous detection circuit 2014 is provided, for example, in FIG.
A synchronization pulse is detected from the vertical synchronization pulse area VSPA of FIG.
5

[0214] The clock reproduction circuit 2015 is a reproduction clock for processing the three video signal components (Y / U / V) of the encrypted analog component video signal at a predetermined timing based on the supplied synchronization pulse. Generate a signal. This reproduced clock signal is also used for synchronously receiving three video signal components (Y / U / V).

The receiving apparatus shown in FIG. 25 includes an inverse shuffle circuit 63BA for inversely shuffling the three video signal components synchronously received by the reproduced clock signal to restore the original analog component video signal. The analog component video signal restored by the reverse shuffle circuit 63BA is sent to the video signal output unit 62B.

In the configuration of FIG. 25, for example, when it is determined that a synchronization signal (VBI) is to be added to a specific channel as shown in FIG. 15, or the same synchronization is applied to all three channels as shown in FIG. When a signal (VBI) is added, only one synchronization signal separation circuit 2011 connected to a specific channel is required. In this case, the synchronization separation circuits 2012 and 2013 can be omitted.

On the other hand, when the synchronization separation circuits 2011 to 2013 are connected to all three channels as shown in FIG. 25, the synchronization signal (VBI) is applied to one of the three channels.
Is known, but it is possible to cope with the case where it is uncertain which channel it is in (that is, the case where three signal components are randomly shuffled).

In the configuration of FIG. 25, the synchronization signal (VBI) can be detected regardless of which channel has the synchronization signal (VBI). Therefore, the synchronization signal circuit 63BB may be arranged at the subsequent stage of the reverse shuffle circuit 63BA.

In the configuration of FIG. 25, all three channels are provided with the synchronization separation circuits 2011 to 2013.
Since the circuit configuration after the synchronization detection (2014) requires only one system, the total hardware amount does not increase three times as much as when only one synchronization separation circuit is used.

FIG. 26 is a view for explaining a specific circuit example (part 2) of the receiving apparatus 201 of FIG.

The configuration shown in FIG. 26 is for restoring (descramble / descramble) the analog component video signal encrypted (scrambled / shuffled) by the video output device 203 having the configuration shown in FIG. 20 or FIG.

In FIG. 26, three video signal components (Y / U /
Each of the three channels for individually transmitting V) is connected to the control circuit 63BE.

The control circuit 63BE includes a clock recovery circuit 2
Based on the clock signal reproduced in 015, a synchronization signal (VBI) is detected from one or more of the three channels.

Specifically, the control circuit 63BE extracts the information of FIGS. 3C, 3D and 3E from the command information transmission area CITA of the line number 11 in the VBI of FIG. 3B, for example. (Command parameter CMPR part)
From the video output device 203 to extract the scramble information (a to f).

Then, the control circuit 63BE uses the extracted scramble information (a to f) to perform descrambling corresponding to the scramble information (encryption key information de to e in FIG. 7) indicating the shuffle state at the time of encryption execution. Keys (encryption key information de to e in FIG. 8) are generated.

The descramble keys (encrypted key information de to e in FIG. 8) thus generated are supplied to the reverse shuffle circuit 63BA. Then, the reverse shuffle circuit 63
BA is based on the supplied descramble key,
Three video signal components on three channels (Y / U / V)
To restore the original analog component video signal.

It is sufficient that the reproduced clock signal in the configuration of FIG. 26 has a timing at which the VBI of FIG. 3 can be extracted, and the synchronization signal extracted from the three video signal components input to the video signal input section 61B. Based on
It is not necessarily limited.

For example, in the case where the encrypted video signal components of the three channels are RGB signals and a synchronization signal channel is provided separately (in addition to the three channels of the RGB signal, the V sync channel and the H sync channel are not included). In the case where it is provided separately), it is possible to generate the reproduced clock signal in the configuration of FIG. 26 based on the synchronization signal of the different channel.

FIG. 27 is a view for explaining a specific circuit example (part 3) of the receiving apparatus 201 of FIG.

The configuration shown in FIG. 27 is applied when the channel on which the synchronization signal (VBI) including the scramble information is carried is predetermined (for example, when the channel is encrypted by the configuration shown in FIG. 20).

That is, the synchronization separation circuit 2 is added to the channel on which the synchronization signal (VBI) containing the scramble information is placed.
016 and the control circuit 63BE are connected.

The synchronization separation circuit 2016 converts the video signal component (Y, U, or V) of the corresponding channel into a synchronization signal (VB
A vertical synchronization pulse in I, etc.) is extracted and input to the clock recovery circuit 2015. Then, the clock reproduction circuit 2015 generates a reproduction clock signal synchronized with the vertical synchronization pulse in the VBI (or synchronized with the horizontal scanning line in the VBI period), and supplies this to the control circuit 63BE.

The control circuit 63BE extracts the scramble information (a to f) from the synchronization signal (VBI) of the video signal component of the connected channel at a timing based on the supplied reproduced clock signal. Then, a descrambling key (encryption key information de to e in FIG. 8) for restoring an encrypted (shuffled based on the scramble information) analog video signal from the extracted scramble information (a to f). Generate

The descramble keys (encryption key information de to e in FIG. 8) thus generated are supplied to the reverse shuffle circuit 63BA. Then, the reverse shuffle circuit 63
BA is based on the supplied descramble key,
Three video signal components on three channels (Y / U / V)
To restore the original analog component video signal.

If the encrypted analog video signal is from the video output device 203 in FIG. 21, a synchronization signal (VB
I) is riding. In this case, the sync separation circuit 2016 of FIG. 27 may be connected to a channel between the reverse shuffle circuit 63BA and the video signal output unit 62B. Similarly,
The control circuit 63BE can also be connected to a channel between the reverse shuffle circuit 63BA and the video signal output unit 62B.

When a synchronization signal (VBI) containing scramble information is carried on all three channels,
The channel to which the sync separation circuit 2016 is connected may be different from the channel to which the reverse shuffle circuit 63BA is connected.

FIG. 28 is a view for explaining a specific circuit example (part 4) of the receiving apparatus 201 of FIG.

In the configuration of FIG. 28, the video signal input section 61B
For all three signal channels.
013 are individually connected. A VBI is detected by a synchronization detection circuit 2014 from a synchronization signal (VBI) separated and extracted by one or more of the synchronization separation circuits 2011 to 2013, and a clock recovery circuit is generated based on the detected vertical synchronization pulse or the like in the VBI. At 2015, a reproduced clock signal is generated.

In the configuration of FIG. 28, the control circuit 63BE is connected to all three signal channels of the video signal input section 61B. The control circuit 63BE converts the synchronization signal (VBI) detected from any one or more of the three signal channels based on the recovered clock signal from the clock recovery circuit 2015 into the scramble information (a to Extract f). A descramble key (encryption key information de to e in FIG. 8) is created from the extracted scramble information and supplied to the reverse shuffle circuit 63BA.

In the configuration of FIG. 28, since the synchronization signal (VBI) can be detected from any of the three channels, the position of the reverse shuffle circuit 63BA may be on the video signal input section 61B side. That is, since the synchronization signal (VBI) can be detected from the signal component after the reverse shuffle, the descrambling key (encryption key information de to e in FIG. 8) can be obtained therefrom.

FIG. 29 is a view for explaining a specific circuit example (part 5) of the receiving apparatus 201 of FIG.

The configuration shown in FIG. 29 is applied when the channel on which the synchronization signal (VBI) including the scramble information is carried is predetermined (for example, when the channel is encrypted by the configuration shown in FIG. 22).

In FIG. 29, three video signal components (Y / U /
Inverting / non-inverting selecting circuits 2017 to 2019 are connected to each of the three channels for individually transmitting V).

[0244] Also, a synchronization separation circuit 20 is provided on a channel on which a synchronization signal (VBI) containing scramble information is carried.
16 and the control circuit 63BE are connected.

The sync separation circuit 2016 converts the video signal component (Y, U, or V) of the corresponding channel into a sync signal (VB
A vertical synchronization pulse in I, etc.) is extracted and input to the clock recovery circuit 2015. Then, the clock reproduction circuit 2015 generates a reproduction clock signal synchronized with the vertical synchronization pulse in the VBI (or synchronized with the horizontal scanning line in the VBI period), and supplies this to the control circuit 63BE.

The control circuit 63BE extracts the scramble information (a to f) from the synchronization signal (VBI) of the video signal component of the connected channel at a timing based on the supplied reproduced clock signal. Then, from the extracted scramble information (a to f), a descrambling key (encryption key information a to c in FIG. 8) for restoring an encrypted (inverted polarity based on the scramble information) analog video signal. ).

The descramble keys (encryption key information a to c in FIG. 8) thus generated are supplied to inversion / non-inversion selection circuits 2017 to 2019. Then, invert
The non-inverting selection circuits 2017 to 2019 output three video signal components (Y / U / V) on three channels to the control circuit 6
The polarity is appropriately inverted based on the descrambling key from 3BE to restore the original analog component video signal.

For example, the analog video signal component (Y / Y) subjected to polarity inversion / repolarization inversion by inverters (inverting / non-inverting polarity inverting circuits) 2037 to 2039 in FIG. 22 and inverting / non-inverting selecting circuits 2017 to 2019 in FIG. U /
V) The amplitude ratio between each of them may have changed from the amplitude ratio between each of the original analog video signal components (Y / U / V). Then, the white balance of the restored analog component video signal changes from the original state.

This change in white balance can be detected by the A provided in the subsequent stage of the inversion / non-inversion selection circuits 2017 to 2019.
It is corrected by the GC circuits 2051 to 2053. The functions of the AGC circuits 2051 to 2053 correspond to the functions of the gain / offset adjustment units G / OF11 to G / OF33 in FIG.

It should be noted that the unencrypted video signal is
9, the inversion / non-inversion selection circuits 2017 to 2019 are in a pass-through state.
No correction of white balance is required. In this case, the control circuit 63BE controls the AGC circuit 2051
The GC function is stopped and a fixed gain circuit operation is performed.

FIG. 30 is a view for explaining a specific circuit example (part 6) of the receiving apparatus 201 of FIG.

The configuration shown in FIG. 30 is applied when the channel on which the synchronization signal (VBI) including the scramble information is carried is not predetermined (when it is uncertain which channel carries the VBI).

In FIG. 30, three video signal components (Y / U /
Inverting / non-inverting selecting circuits 2017 to 2019 are connected to each of the three channels for individually transmitting V).

In the configuration of FIG. 30, all three signal channels of the video signal input section 61B are provided with the synchronization separation circuit 201.
1 to 2013 are individually connected. Then, the synchronization detection circuit 2014 is extracted from the synchronization signal (VBI) separated and extracted by any one or more of the synchronization separation circuits 2011 to 2013.
, A VBI is detected, and a clock recovery circuit 2015 generates a reproduced clock signal based on the detected vertical synchronizing pulse or the like in the VBI.

Further, in the configuration of FIG. 30, the control circuit 63BE is connected to all three signal channels of the video signal input section 61B.
Is connected. The control circuit 63BE converts the synchronization signal (VBI) detected from any one or more of the three signal channels based on the recovered clock signal from the clock recovery circuit 2015 into the scramble information (a to Extract f). A descramble key (encryption key information a to c in FIG. 8) is generated from the extracted scramble information.

The descramble keys thus generated (encryption key information a to c in FIG. 8) are supplied to inversion / non-inversion selection circuits 2017 to 2019. Then, invert
The non-inverting selection circuits 2017 to 2019 output three video signal components (Y / U / V) on three channels to the control circuit 6
The polarity is appropriately inverted based on the descrambling key from 3BE to restore the original analog component video signal.

Inversion / non-inversion selection circuits 2017 to 2019
AGC circuits 2051 to 2020 similar to those in FIG.
53 are provided. The AGC circuits 2051 to 20
53 corrects the white balance of the restored analog component video signal.

In the configuration shown in FIG. 30, the synchronization signal (VBI) can be detected from any of the three channels.
The positions of the non-inverting selection circuits 2017 to 2019 may be on the video signal input unit 61B side. That is, since the synchronization signal (VBI) can be detected from the signal component after the reverse shuffle, the descramble key (encryption key information a to c in FIG. 8) can be obtained therefrom.

FIG. 31 is a view for explaining a specific circuit example (7) of the receiving apparatus 201 in FIG.

In the configuration of FIG. 31, the reverse shuffle circuit 63BA of FIG. 27 is replaced with the inversion / non-inversion selection circuit 2017 of FIG.
To 2019.

In the configuration shown in FIG. 31, a video signal component (Y, U, or V) of a predetermined channel is converted into a synchronization signal (VBI).
Are separated, and scramble information (af) is extracted from the separated VBI. Then, from the extracted scramble information (a to f), a descrambling key for reverse shuffle (encryption key information de to e in FIG. 8) and a descramble key for inversion / non-inversion selection control (FIG. 8) Is generated.

One of the thus generated descramble keys (d to e) is supplied to an inverse shuffle circuit 63BA, and the other descramble keys (a to c) are supplied to inversion / non-inversion selection circuits 2017 to 2019. Is done.

The inverse shuffle circuit 63BA inversely shuffles the input signal components based on the descramble keys (d to e), and inverts / non-inverts select circuits 2017 to 2019.
Reverses the polarity of the signal component after the reverse shuffle based on the descramble keys (a to c). The analog video signal restored in this manner is used as a white balance correcting A
The data is sent to the output unit 62B via the GC circuits 2051 to 2053.

In the structure shown in FIG. 31, the position of the reverse shuffle circuit 63BA and the inversion / non-inversion selection circuit 201
7 to 2019 and AGC circuits 2051 to 2053
Are interchangeable.

FIG. 32 is a view for explaining a specific circuit example (8) of the receiving apparatus 201 of FIG.

FIG. 32 is a diagram showing the sync separation part / VBI of FIG.
This is a case where the extracted part is made to correspond to all three channel circuits as shown in FIG.

That is, in the configuration shown in FIG. 32, synchronization separation circuits 2011 to 2013 are provided for each of the three channels through which each video signal component of the input (encrypted) analog component video signal passes.

These synchronization separation circuits 2011 to 2013
When a synchronizing signal (VBI) is detected in any of the above, a reproduced clock signal is generated therefrom (by the clock reproducing circuit 2015 through the synchronizing detection circuit 2014). Then, based on the reproduced clock signal, the control circuit 63B
By means of E, scramble information (af) is extracted from the synchronization signal (VBI) on any of the three channels.

In the control circuit 63BE, based on the extracted scramble information (af), the descramble keys (d to e) and the descramble keys (a to
c) is generated.

One of the generated descramble keys (d to e) is supplied to an inverse shuffle circuit 63BA, and the other descramble keys (a to c) are supplied to inversion / non-inversion selection circuits 2017 to 2019. Is done.

The inverse shuffle circuit 63BA inversely shuffles the input signal components based on the descramble keys (d to e), and inverts / non-inverts select circuits 2017 to 2019.
Reverses the polarity of the signal component after the reverse shuffle based on the descramble keys (a to c). The analog video signal restored in this manner is used as a white balance correcting A
The data is sent to the output unit 62B via the GC circuits 2051 to 2053.

In the above description, the receiving device 201 and the video output device 203 have been described as a part of the analog signal information processing device 30.

However, the present invention is not limited to the above description,
For example, the receiver 201 is regarded as one video receiver such as a TV or a VCR with a built-in tuner, and the video output device 20 is used.
3 can be regarded as one video output device such as a DVD player or a VCR.

In FIGS. 15 to 32, three signals Y, V, and U are used as video signals, but the present invention is not limited to this. For example, the present invention is applicable to a case where R, G, and B signals are used, and a case where S signals (two signals obtained by separating a luminance signal and a chrominance signal) are used.

When the S signal is used, for example, in the circuit configurations shown in FIGS. 15 to 32, Y is used for the S luminance signal, U is used for the S color signal, and V is deleted (or the V circuit is used). U common circuit) is conceivable.

Further, the luminance signal (Y) is added to the color difference signal (I /
Q or Y-R / Y-B) is superimposed on the original composite video signal, the composite video signal after polarity inversion, the pedestal level of the composite video signal, and the composite video signal. It is also possible to replace (shuffle) or invert the polarity of the four types of the maximum amplitude of the included image signal portion, or to create an encrypted signal.

For example, the original composite video signal and the composite video signal whose polarity has been inverted can be replaced for each field and encrypted. Further, the pedestal level of the original composite video signal can be inverted and inverted for each frame. Also, the maximum amplitude of the image signal portion of the original composite video signal can be changed for each field and encrypted. Encryption using a mixture of these encryption methods is also possible.

[0278]

Advantages of the Invention By transmitting the encrypted analog video information between the devices, it is possible to prevent unauthorized use or illegal copying of the video information by other devices connected to the network.

[0279] 2. By transmitting encrypted analog video information between devices, the existing analog connection terminal (composite terminal or S terminal) can be used with a small circuit addition (for example, adding one dedicated IC). .

Since the analog video terminal is provided as standard equipment in most video equipment, the transmission processing of the encrypted analog video information according to the present invention can be easily spread.

[0281] 3. Compared with the existing IEEE 1394 copy protection (transmission processing of encrypted digital video information), the control circuit scale is small, the cost of the video information device is suppressed, and the size of the video information device is prevented from increasing. Can be.

[0282] 4. As an analog video information encryption method, since the signal exchange level in the scanning line order is simple, it is possible to grasp the approximate content of the video information even with devices other than the authorized receiver (of course, normal reception is not possible). Then, the encrypted analog video signal serves as a commercial, which invites other model users who intercept the video signal to purchase (for the device using the present invention), and the encrypted analog video information It will greatly contribute to the market expansion of video information equipment having the processing function of.

[0283] 5. Since the scramble information (encryption key) can be transmitted at the same time using the analog signal transmission line that transmits the video signal, the scramble information (decryption key) is distributed to the legitimate contract user's home by mail or another method. This makes it very easy to deliver scramble information that can be used only by authorized recipients. That is, according to the present invention, there is almost no cost for delivering the encryption key information to the authorized user.

[0284] 6. Since the scramble information can be transmitted simultaneously using the analog signal transmission path that transmits the video signal,
The sender of the video signal information can frequently change the scramble content. As a result, since the hackers are not given a margin of time for decryption, it is possible to ensure extremely high security (prevention of unauthorized use, prevention of unauthorized copy).

[Brief description of the drawings]

FIG. 1 is an exemplary view for explaining the outline of a video signal processing system according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a process of transmitting analog signal information in the video signal processing system of FIG. 1;

FIG. 3 is an exemplary view for explaining a content example of a vertical blanking period (VBI) of an analog video signal used in the video signal processing system of FIG. 1;

FIG. 4 is an exemplary view for explaining a specific example of a command code included in a vertical blanking period (VBI) in FIG. 3;

FIG. 5 is a block diagram illustrating a specific example of an analog signal encryption unit (scramble encoder) 29 of FIG. 1;

FIG. 6 is a block diagram illustrating a specific example of an analog signal restoring unit (scramble decoder) 25 of FIG. 1;

FIG. 7 is a diagram illustrating a specific example of an analog video signal switching unit (shuffle circuit) 63A in FIG. 5;

FIG. 8 is a diagram illustrating a specific example of an analog video signal switching unit (reverse shuffle circuit) 63B of FIG. 6;

FIG. 9 is a block diagram illustrating a modification of the analog signal information processing apparatus 30 of FIG.

FIG. 10 is a view for explaining an example of the internal configuration of the video output device 203 in FIG. 9;

11 is a view for explaining an example of the internal configuration of the receiving apparatus 201 in FIG.

12 is a diagram showing a specific circuit example of an inverter constituting the polarity inversion circuit 207 in FIG. 10 or the inversion / non-inversion selection circuit 212 in FIG. 11;

FIG. 13 shows the polarity inversion circuit 207 of FIG. 10 or FIGS.
FIG. 20 is a view for explaining the waveform of an analog video signal whose polarity has been inverted (encrypted) by inverters 2037 to 2039 in FIG. 19;

14 is a diagram illustrating the signal switching circuit 206 of FIG. 10 or FIGS.
FIG. 25 is a view for explaining a signal exchange pattern (shuffle pattern) in the shuffle circuit 63AA of FIG. 24.

FIG. 15 is a view for explaining a specific circuit example (part 1) of the video output device 203 in FIG. 9;

16 is an exemplary view for explaining a specific circuit example (2) of the video output device 203 in FIG. 9;

FIG. 17 is an exemplary view for explaining a specific circuit example (3) of the video output device 203 in FIG. 9;

FIG. 18 is a view for explaining a specific circuit example (part 4) of the video output device 203 in FIG. 9;

FIG. 19 is a view for explaining a specific circuit example (part 5) of the video output device 203 in FIG. 9;

20 is an exemplary view for explaining a specific circuit example (part 6) of the video output device 203 in FIG. 9;

21 is an exemplary view for explaining a specific circuit example (part 7) of the video output device 203 in FIG. 9;

FIG. 22 is a view for explaining a specific circuit example (8) of the video output device 203 in FIG. 9;

FIG. 23 is an exemplary view for explaining a specific circuit example (part 9) of the video output device 203 in FIG. 9;

FIG. 24 is a view for explaining a specific circuit example (10) of the video output device 203 in FIG. 9;

FIG. 25 is a view for explaining a specific circuit example (1) of the receiving apparatus 201 in FIG. 9;

FIG. 26 is a view for explaining a specific circuit example (2) of the receiving apparatus 201 in FIG. 9;

FIG. 27 is a view for explaining a specific circuit example (3) of the receiving apparatus 201 in FIG. 9;

FIG. 28 is a view for explaining a specific circuit example (part 4) of the receiving apparatus 201 in FIG. 9;

FIG. 29 is a view for explaining a specific circuit example (part 5) of the receiving apparatus 201 in FIG. 9;

FIG. 30 is a view for explaining a specific circuit example (part 6) of the receiving apparatus 201 in FIG. 9;

FIG. 31 is a view for explaining a specific circuit example (7) of the receiving apparatus 201 in FIG. 9;

FIG. 32 is a view for explaining a specific circuit example (8) of the receiving apparatus 201 in FIG. 9;

[Explanation of symbols]

1, 30, 40, 51, 52: Analog signal information processing device; 2, Analog video signal generator; 3, Analog signal encryption unit; 4, Scramble signal generation unit; 5, Command information processing unit; 6, Analog signal 7: Analog signal information transmission section; 8: Transmission / reception switching section; 9: Analog signal information transmission path; 10: Command information extraction section; 11: Analog signal transmission section; 20: Analog signal Information transmission section; 21 transmission / reception switching section; 22 command information insertion section; 23 command information extraction section; 24 analog signal information extraction section; 25 analog signal restoration section (decryption section); Analog video information display unit; 27
... Command information processing unit; 28 ... Scramble signal generation unit; 29 ... Analog signal encryption unit; 31 ... Analog signal transmission unit; 32 ... Command information extraction unit; 33 ... Synthesis unit of analog signal information and command information (scramble information addition 34) Transmission / reception switching unit; 35, 41 ... analog signal information transmission unit; 42 ... command information processing unit; 43 ...
Analog signal information recording section; 61A ... analog component video signal (before scrambling) input section; 61B ... analog component video signal (after scrambling) input section; 63D ... digital component video signal (before scrambling) input section; 62A ... analog component video Signal (after scrambling) output section; 62B ... Analog component video signal (after descrambling) output section;
63A: analog video signal switching unit (shuffle circuit);
63A: analog video signal switching unit (reverse shuffle circuit); 64A: switching information storage unit (scramble information storage unit); 64B: switching information storage unit (scramble descramble information storage unit); 65A: M-sequence random number generator; 63AB: Synchronization signal addition unit; 63AC: inversion / non-inversion processing unit; 63AD: scramble information addition unit; 63AE: scramble control circuit; 63BA: reverse shuffle circuit; 63BB: synchronization signal separation unit;
Inverting / non-inverting processing section; 63BE descramble control circuit; 63BF automatic amplitude adjustment section; 66 synchronization signal generating section; INV11 to INV13 inverter;
To INV23 ... inverter; G / OF11 to G / OF3
3: gain / offset automatic adjustment unit; 201: reception device; 202: control unit (control of overall operation); 203: video output device; 206: signal switching circuit (shuffle circuit);
207: polarity inverting circuit (inverter circuit); 208: synchronizing signal (VBI) adding circuit; 209: control circuit (control of timing / operation sequence on the scramble side);
1 synchronization signal circuit; 212 inversion / non-inversion selection circuit; 2
13: signal switching circuit (reverse shuffle circuit); 214: gain / offset adjustment circuit; 215: control circuit (timing / operation sequence control on the descrambling side);
2011 to 2013: synchronization signal separation circuit; 2014: synchronization signal detection circuit; 2015: clock recovery circuit;
Reference numeral 6: Synchronous signal separation circuit; 2017 to 2019: Inverting / non-inverting polarity inverting circuit (inverter switch / non-inverter switch); 2031 to 2033: Synchronizing signal adding circuit; 2034 to 2036: Digital / analog converter (DAC); 2039 ... inverting / non-inverting polarity inverting circuit (inverter switch / non-inverter switch); 2041 to 2043 ... scramble information adding circuit; 2051 to 2053 ... gain control amplifier (AGC circuit).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/169 H04N 7/167 A 9/804 9/80 B 9/808 (72) Inventor Tomohisa Kimura Kanagawa (72) Inventor Tetsuro Itakura 1 Kosuka Toshiba-cho, Kawasaki-shi, Kawasaki, Kanagawa Prefecture, Japan Toshiba R & D Center (72) Invention Person Hiroshi Tanimoto 1 Toshiba-cho, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture F-term in the Toshiba R & D Center (reference) HA15 HA31 5C064 BA01 BB01 BB10 BC17 BC22 BD08 BD09 CA02 CA05 CB02 CC02 5J104 AA01 BA03 JA04 PA05

Claims (8)

[Claims] 1. A luminance signal component, a first color difference signal component, and a second color difference signal component.
A signal switching unit that replaces and scrambles an arbitrary signal component among component video signals including a color difference signal component of the above; and a synchronization signal necessary for synchronously receiving each signal component of the scrambled component video signal. A video signal processing system, comprising: a synchronizing signal generator for adding to any of the signal components of the component video signal. 2. A luminance signal component, a first color difference signal component and a second color difference signal component.
An inverting / non-inverting switching unit that scrambles by inverting or non-inverting the polarity of an arbitrary signal component of the component video signal including the color difference signal components of the above; and each signal component of the scrambled component video signal A synchronizing signal generator for adding a synchronizing signal necessary for synchronous reception to any one of the signal components of the component video signal. 3. The method according to claim 1, wherein the luminance signal component, the first color difference signal component, and the second
A signal switching unit that replaces and scrambles an arbitrary signal component among the component video signals including the color difference signal components; and restores each signal component of the scrambled component video signal to a state before being scrambled. A scramble information adding unit for adding necessary scramble information to any one of the signal components of the component video signal. 4. A luminance signal component, a first color difference signal component and a second color difference signal component.
An inverting / non-inverting switching unit that scrambles by inverting or non-inverting the polarity of an arbitrary signal component of the component video signal including the color difference signal components of the above; and each signal component of the scrambled component video signal And a scramble information adding unit for adding scramble information necessary for restoring to a state before being scrambled to one of the signal components of the component video signal. 5. A synchronization separating circuit for separating a synchronizing signal from a signal component of a scrambled component video signal in which an arbitrary signal component among a luminance signal component, a first color difference signal component, and a second color difference signal component is replaced. A clock recovery circuit for generating a recovered clock based on the separated synchronization signal; and a signal of the scrambled component video signal from a signal component of the scrambled component video signal based on the recovered clock. A control circuit for detecting scramble information necessary for restoring the component to a state before being scrambled, and outputting a descrambling key; each signal of the component video signal scrambled based on the descrambling key Reverse shuffle to restore components to their pre-scrambled state A video signal processing system characterized by comprising a Le circuit. 6. The method of claim 1, wherein the polarity of any of the luminance signal component, the first chrominance signal component, and the second chrominance signal component is inverted or non-inverted to obtain a scrambled component video signal. A synchronization separation circuit for separating a synchronization signal; a clock recovery circuit for generating a reproduction clock based on the separated synchronization signal; and a scramble from the signal component of the scrambled component video signal based on the reproduction clock. A control circuit for detecting scramble information necessary for restoring each signal component of the component video signal to a state before being scrambled, and outputting a descrambling key; and a scrambled key based on the descrambling key. Before each signal component of the component video signal is scrambled. An inverting / non-inverting selecting circuit for restoring a state; and for each signal component of the component video signal restored by the inverting / non-inverting selecting circuit, an automatic gain for adjusting the amplitude of these signal components to a predetermined value. A video signal processing system comprising a control circuit. 7. A method according to claim 1, wherein any of the luminance signal component, the first chrominance signal component, and the second chrominance signal component is replaced with each other and the signal components of the scrambled component video signal are replaced with each other. A control circuit for detecting scramble information necessary for restoring to a state before being scrambled and outputting a descrambling key; and converting each signal component of the component video signal scrambled based on the descrambling key. A video signal processing system comprising: an inverse shuffle circuit for restoring a state before scrambling. 8. An arbitrary signal component of the luminance signal component, the first color difference signal component, and the second color difference signal component is replaced and scrambled, and the polarity of the arbitrary signal component is inverted or non-inverted. A synchronization separation circuit for separating a synchronization signal from the signal component of the component video signal scrambled by the above; a clock recovery circuit for generating a reproduction clock based on the separated synchronization signal; Detecting, from the signal components of the scrambled component video signal, scramble information necessary for restoring each signal component of the scrambled component video signal to a state before being scrambled, and outputting a descrambling key And a control circuit for inputting the signal component based on the descrambling key. An inverse shuffling circuit for restoring each signal component of the component video signal scrambled by the switching to a state before being scrambled; and the scrambled signal inverted or non-inverted based on the descrambling key. An inverting / non-inverting selecting circuit for restoring each signal component of the component video signal to a state before being scrambled; and for each signal component of the component video signal restored by the inverting / non-inverting selecting circuit, An automatic gain control circuit for adjusting the amplitude of the signal component to a predetermined value.