JPS62164202A - Pulse current output circuit - Google Patents

Abstract

PURPOSE:To improve the stability of the pulse current output and to omit the control of a pulse current output circuit, by using the 3rd semiconductor switch to keep the output voltage of a constant current source at a fixed level for the periods excepting for the load drive periods of the 1st and 2nd semiconductor switches. CONSTITUTION:A control circuit 24 controls the semiconductor switches 19 and 20 based on the timing control signal and the indication data on the current direction of a load 23 and flows a constant current of the indicated direction to the load 23 via a constant current source 15 for a period indicated by the timing control signal. While the circuit 24 controls the semiconductor switches 21 and 22 for a period when the groups of both switch groups 19 and 20 are not driven to give the same impedance as the load 23 to the output of the source 15. Thus a constant current is supplied from the source 15 and the potential of the output point of the source 15 is kept at a fixed level. In such a way, a stable constant current is supplied to the load 23 as a pulse current even in case both switch groups 19 and 20 and switches 21 and 22 have fast switching actions.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a pulse current output circuit that drives a load with a pulse current, and in particular to a fixed head type digital data output circuit.
This invention relates to a drive circuit for a multi-track thin film recording head in a tape recorder or a fixed head type digital audio tape recorder.

(b) Conventional technology In recent years, PCM (Pulse Code Modulation) recording, which applies digital technology to record audio signals, has become popular. In particular, tape recorders that can record and play PCM using compact cassette tapes are becoming popular. It is appearing. Such a tape recorder is a fixed head type digital audio tape recorder using a multi-trunk thin film recording head, and each channel of the recording head has a positive/negative signal corresponding to "1" and "0" of the signal data. A pulsed current is applied to control the magnetization direction of the tape. Pulse current is applied to the multi-track thin film recording head in a time-divisional manner, but when the period of the pulse current that can be applied to each head, that is, the recording frequency is increased, the output voltage vs. write current characteristic of the recording head changes as follows: As shown in FIG. 3, peak characteristics are shown centered around a certain value. Therefore, the pulse current applied to the recording head must be adjusted to fall within the optimum current range centered around its peak value.

Therefore, conventionally, the recording head has been driven by circuits as shown in FIGS. 4(a), 4(b), and 4(c). In FIG. 4(a), each head (1) is connected to a variable voltage source (2).
A P-channel MO3FET (
3) and the connection point of N-channel MO8FET (4) and P
Channel MO3FET (5) and N-channel MO3
Connection can be made between the connection point of FET (6) and the connection point of FET (6). The control circuit (7) controls the current flowing through the recording head (1) to each MO8FET (3) (4) based on the data to be recorded.
(5) and (6), the optimum value of which current is adjusted by the variable voltage source (2). FIG. 4(b) shows a configuration in which the variable voltage source (2) of FIG. 4(a) is constructed from a variable resistor (8) and a voltage source (9). In Fig. 4(C), the recording head (1) is connected between the connection point of P-channel MO3FET (10) and N-channel MO8FET (11) and the ground, and MO8FE T (10)<11).
Variable voltage sources (12) and (13) are connected to the other ends, respectively. That is, in each of FIGS. 4(8), (b), and (C), the current value of the pulse current is adjusted by adjusting the voltage applied to the recording head. This is described on pages 168 to 171 of "AES" [Conference 1985 Proceedings].

(c) Problems to be Solved by the Invention However, in the circuits shown in FIGS. 4(a), (b), and (C), variations in the internal impedance of the MOSFET and the impedance of the recording head cause the value of the pulse current to The pulse current may deviate from the optimum value. Therefore, it is necessary to adjust the voltage each time according to the variation, and it has been impossible to obtain highly reliable and stable performance regardless of the environment.

(d) Means for solving the problem The present invention has been made in view of the above-mentioned points, and includes a constant current source for supplying a constant current to a load, and an output of the constant current source and a predetermined value. Cannot be connected in series with potential, e.g. ground,
A third semiconductor for providing approximately the same impedance as the load between the first semiconductor switch group and the second semiconductor switch group to which the load is connected to the connection point, and the output of the constant current source and ground. a control circuit that controls a first semiconductor switch group, a second semiconductor switch group, and a third semiconductor switch;
During periods other than the period in which the pulse current is passed through the load by the third semiconductor switch, the third semiconductor switch causes the pulse current to flow approximately the same as the load.
An impedance is applied to the output of a constant current source, and a current is passed through that impedance.

(E) Operation According to the above means, the control circuit controls the first semiconductor switch and the twentieth semiconductor switch based on the timing control signal and the data instructing the direction of the current flowing through the load, and the timing control signal A constant current is passed from the constant current source to the load in the specified direction for the period specified by . In addition, the control circuit controls the third semiconductor switch during a period in which the first semiconductor switch group and the second semiconductor switch group are not driven by the timing control signal, so that the output of the constant current source has approximately the same voltage as the load. Gives impedance.

As a result, a constant current flows through that impedance from a constant current source. That is, even if the first semiconductor switch group, the second semiconductor switch group, and the third semiconductor switch are switched by the control circuit, a constant current always flows from the constant current source. The potential at the output point is always held constant. Therefore, even if the first semiconductor switch group, the second semiconductor switch group, and the third semiconductor switch perform high-speed switching operations, a stable constant current can always be supplied to the load as a pulse current.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, which is a circuit for driving four recording heads.

The constant current source (15) that supplies constant current to the recording head (14) is a well-known circuit composed of an operational amplifier (16), a PNP transistor (17), and a resistor (18). A voltage lower by the reference voltage Vref is applied from the power source E to the 16) human power, and a voltage lower by the voltage drop of the resistor (18) is applied to the - human power from the power source E. Therefore, the current taken out from the collector of the transistor (17) via the output terminal Ncom becomes a constant current.

Between this output terminal Ncom and ground, there is a P-channel MO3FET (19) which is a first semiconductor switch.
and a second semiconductor switch, an N-channel MOS.
Five sets of FET (20) are connected in series. And each MOS FET (19) and MOSFET (20)
A recording head (14) is connected between each connection point.

Furthermore, a P-channel MOS FET (21), which is a third semiconductor switch, is connected between the output terminal Neon and the ground.
and an N-channel MOSFET (22), and a dummy load (with the same impedance as the recording head (14)).
23) are connected in series. Here, MOS FET
(21) and 22〉 are each other MO8F' E T
Since they are formed with the same size as (19) and (20), their impedances in the on state are equal. Therefore, one MOS FET (19) and one MOS
The impedance between the output terminal Ncom and ground when the FET (20) is turned on and current is flowing to the recording head (14), and the impedance between the output terminal Ncom and the ground when the MOS FET (21) and <22) are turned on and the dummy load (23) Output terminal Nc when current flows
The impedance between om and ground will be equal.

These (7) MOS FET (19) (20)
The on and off of (21) and (22) can be controlled by the control circuit (24). The control circuit (24) includes 4
A timing control signal 5trobel to 4 for sequentially specifying the recording heads (14) and driving the pulse train.
MOS F.
ET (19), (20), (21), and (22), a NAND gate (25) that applies the output to the gate of MOSFET (19), and a NOR gate that applies the output to the gate of MOSFET (20). (26) is provided. That is, MO8F-7= E T (19) (20) and NAND gate (25) N
The OR gate (26) and the inverter (27) form a CMOS driver that operates in three stages. In addition, the control circuit (24>) receives timing control signals 5trobel to 4.
and inverters (28) (29) that selectively input recording data DATE, E-OR gate (30), and NOR
A gate (31) is provided. Furthermore, a timing control signal str.

The output of the NOR gate (32) that inputs be1 to be4 is M
It is applied to the gate of the OSFET (22) and is also applied to the gate of the MOSFET (21) via the inverter (33). As a result, during the period when the timing control signals 5trobe1 to 5trobe4 are all "0"', MO3
FET (21) and (22) are turned on.

Note that a capacitor (34) is connected between the output terminal Ncom of the constant current source (15) and the ground. This capacitor (34
) is M OS F E T (19) (20) (21
) and (22) are bypass capacitors for absorbing spike noise generated during switch operation.

FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. The timing control signal 5trobel~4 is
These pulses have a pulse width t1 that sequentially becomes "1", and each pulse selects a recording head (14). Also, there is a time t between one pulse and the next.

The recording data DA is recorded during the period t.
TA changes. The recording data DATA is data that is synchronized with the pulses of the timing control signals 5trobel to 4 and instructs the direction of the current to flow through the recording head (14) specified by the pulses.

Therefore, when a pulse is generated in the timing control signal 5trobe 1, if the recording data DATA is "1", the Q p+ of the MOS FET (19) and the MOS
Since only QN2 of the FET (20) is turned on and the others are turned off, a current flows through the recording head (14) in the direction of the arrow. This current (1) is a constant current that can be supplied from the constant current source (15). On the other hand, when the recording data DATA is "O" (7), MOSFET (19
) and QNl of the MOSFET (20) are turned on, so a current in the direction opposite to the arrow, ie, a current flows through Ll of the recording head (14). Similarly, when a pulse is generated in the timing control signal 5trobe2.3.4, according to the contents of the recording data DATA, each of L2, L3, and L4 of the recording head (14) is
A current of 3.±.4 will flow, and the magnitude of these currents will all be constant currents that can be supplied from the constant current source (15).

On the other hand, during the period t2 in which no pulse is generated in the timing control signals 5trobe1-4, the output of the NOR gate (32) becomes "1" and the output of the inverter (33) becomes "0", so that the MOS FET (21) and ( 22) are both turned on, a light beam flows through the dummy load (23) in the direction of the arrow.The current A is a constant current that can be supplied from the constant current source (15).

Therefore, regardless of the pulse train that can be applied to the timing signals 5trobel to 4, a constant current always flows from the constant current source (15). Therefore, in each path where a constant current flows, MOS FET (19) (20
) and the recording head (14) are set to be equal, and the MOSFETs (21) and (2) are set to have the same impedance.
2) and the dummy load (23) are set to be equal, so the output terminal N. The potential of 0u is MOSFET (1,9)(20) and MOS
It is held constant regardless of the switching operations of FETs (21) and (22). Therefore, the constant current fi(15) is
A high-performance device is not necessary because it is sufficient to simply keep the direct current flowing.

In this way, each of the recording heads (14) has a constant current source (
15), so once the current value of the constant current source 15) is set to the optimum current value shown in FIG.
19) The current value does not change due to the impedance variations in (20). Also, the output terminal N. . Since the voltage of , can be maintained constant, the high-speed response performance of a constant current source is not required, and as a result, MOSFET (19) (20)
This enables high-speed switching operation.

In the circuit shown in FIG. 1, the recording head (14
) and constant current source (15) are integrated on the same chip, but by configuring the constant current source (15) with a MOS FET or by using Bi-MO8 technology to integrate bipolar transistors and MO8. It is also possible to accumulate

(g) Effects of the Invention As described above, according to the present invention, a pulse current output circuit suitable for a drive circuit of a multi-track thin film recording head of a fixed head digital audio tape recorder can be obtained, and a semiconductor switch can be used. This eliminates the effects of fluctuations in the impedance of the recording head and the temperature, improving the stability of the pulse current output, making it possible to eliminate the need for circuit adjustments, and increasing speed. Therefore, highly reliable and stable characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. 1, FIG. 3 is a characteristic diagram of the recording head, and FIG. (b) and (c) are circuit diagrams showing a conventional example. (14)... Recording head, (15)... Constant current source, (19) (21)... O8FET between P channels,
(20) (22)...N-channel MO3FET,
(23)...Dummy load, (24)...Control circuit, (34)...Capacitor. 5trobe 3 S (:robe4 Figure 4 (F) Figure 4 (C) Figure 4 (C)

Claims (1)

[Claims] 1. A constant current source for supplying a constant current to a load; a first semiconductor switch group having one end connected to the output of the constant current source and the other end connected to the load; a second semiconductor switch group connected between a connection point of the load and a predetermined potential; a third semiconductor switch for providing the same impedance as the load between the output of the constant current source and the predetermined potential; and the load. a control circuit that controls the first semiconductor switch group, the second semiconductor switch group, and the third semiconductor switch based on data and a control signal instructing a current to flow in the first semiconductor switch group, and a control circuit that controls the first semiconductor switch group, the second semiconductor switch group, and the third semiconductor switch, The third semiconductor switch applies the same impedance as the load to the output of the constant current source during a period other than the period in which the second semiconductor switch drives the load, thereby keeping the output voltage of the constant current source constant. Pulse current output circuit.