JPS62163360A - Bipolar integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a bipolar integrated circuit of high withstand voltage in a process of low withstand voltage without requiring outside resistance and large consumed- electric power in the integrated circuit, by using a constant-current source instead of resistance and making a biased current flow across a constant-voltage element with the constant current so that a consumed current can be reduced when a power input voltage becomes high. CONSTITUTION:The first constant-voltage element 5, one end of which is connected with a positive power-source input VCC and the other end of which is connected with a negative power-source input VEE through an impedance element 6 connected in series, and a PNP transistor 7, whose base is connected at a connection point of the impedance element 6 and the first constant-voltage element 5 and whose emitter is connected with the positive power-source input VCC through a resistor 9, are provided. And, the second constant-voltage element 2 connected between a collector of the PNP transistor 7 and the negative power-supply input VEE, and a NPN transistor 3, whose base is connected at a connection point of the collector of the PNP transistor 7 and the second constant-voltage element 2 and whose collector is collected with the positive power-supply input VCC, are provided. And, bias voltage is obtained from the emitter of the NPN transistor 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high voltage bipolar integrated circuit.

BACKGROUND ART Conventionally, the method shown in FIG. 14 has been used to realize a high voltage integrated circuit. 1 is a circuit network inside the integrated circuit,
This is the part that performs the original function of an integrated circuit. Vcc is a positive power input, and Vxx is a negative power input.

In this case, N occupies most of the elements constituting the circuit network 1
For example, using a PN transistor as a diode, etc.
Except for special cases, a voltage approximately equal to the power supply input voltage is applied between the collector and emitter of most NPN transistors in the worst case, so the withstand voltage between the collector and emitter when the base of the NPN transistor is open (hereinafter referred to as VCI) is
(referred to as IO) must be higher than the power supply input voltage.

The Vcxo of an NPN transistor is determined by the process of its integrated circuit;
In this case, a process in which o can be made high will be referred to as a high breakdown voltage process.

In the case of Figure 14, is it an integrated circuit with a high level of 1? To achieve this, heavy use of high-voltage processes is required.

Such a configuration has the following problems.

The high breakdown voltage process has a low impurity concentration, resulting in a high specific resistance, and for transistors with the same current capacity, the area occupied by the emitter must be large. Furthermore, since a high voltage is applied to the elements themselves or between the elements, it is necessary to set a large mask rule (the distance between the masks).

For this reason, the chip area becomes very large in the high-voltage process, and the yield deteriorates by the increased chip area, and the number of chips per wafer decreases markedly. In addition, since the impurity concentration is low and the mask rule must be large, the DC current amplification factor hp of the transistor is
As g becomes lower, the number of elements inevitably increases or the function deteriorates if the same function is to be achieved.

Furthermore, a high voltage process is not common, and the process itself is expensive.

For these reasons, the high-voltage process has the problem of increased costs, but it goes without saying that an integrated circuit with a stylus pressure higher than that of the high-voltage process is impossible.

Therefore, when trying to realize a complete high-voltage integrated circuit without using a high-voltage process, the Vart
o Since the power supply input voltage is higher than VCIIO, the voltage applied between the collector and emitter exceeds VCIIO.
For transistors, it is necessary to add a special circuit to each NPN transistor to ensure that VCKO is not exceeded, but in that case, increasing the number of elements or adding circuits to an extreme degree will reduce performance. There is a problem with this. Furthermore, depending on the circuit, the above-mentioned circuit may not be added at all due to its functionality.

In order to solve this problem, the circuit shown in FIG. 16 can be considered as an improvement on the conventional example described above.

Figure 15 shows that a constant voltage element 2 is used in addition to the circuit network 1 inside the integrated circuit, which performs the original function of the integrated circuit, without using a high withstand voltage process.
, an NPN transistor 3, and a resistor 4, which are internal elements of the integrated circuit. The power supply input voltage is
By lowering the power supply input voltage using a circuit to lower it below and supplying electric power Et to the circuit network 1, a voltage higher than Veto is prevented from being applied to the NI'N transistor of the circuit network 1. N of the circuit that drops the input voltage
By connecting the collector and emitter of the PN transistor 3 and the circuit network 1 in series with the power supply, a voltage of 1cxo or more is not applied between the collector and emitter.

In the circuit of FIG. 15, for example, the current consumption factor 1 of the circuit network 1 is 4 mA, and the minimum DC current amplification factor h of the NPN transistor 3 is
yi+Q40, operating voltage Vz2 of constant voltage element 2 16-
T'l, integrated circuit knob o cess r6. The Vcgo of N P N transistor 3 is guaranteed to be 24V (hereinafter referred to as 24V
The following explanation assumes that a process (referred to as a process) has been adopted.

The base current Las required for the NPN transistor 3 is determined by the following equation.

From 5 = Ics / hyw-... (1)
hyx')) When 1, I! 15 = Ix / hyx = 4 [mA) / 4o = o, 1 (:mA] --
---- (2) In order to prevent the operating voltage of the constant voltage element from fluctuating too much, it is necessary to keep the operating current IZ2 flowing at about 0.1 mA or more, so the lowest value of IZ2 should be set to 0.
．． It is set to 1 mA.

Minimum value of voltage drop between the collector and emitter of NPN transistor 3' (i72V) If it is made smaller than this, the resistance value of resistor 4 will be lowered and the current consumption will increase, and if it is made larger than this, the resistance value of resistor 4 will be ), and the power supply input voltage (Vcc,
Vgx voltage voltage operating range? (Minimum operating voltage FE of the circuit network
)+2V to 40V, and the voltage between the base and emitter of the NPN transistor 3 is Vuxsfo·7V, then the resistance value R4 of the resistor 4 is determined by the following equation.

0,1 j mA,]+0.1[mA'1=6.5(k
Ω] ...... (3) When the circuit shown in Figure 15 is operated with a resistance of 4% - 6.5 Ω, the voltage applied to circuit 1 (hereinafter referred to as internal bias voltage) and the power input voltage The relationship is as shown in Figure 16, and the internal bias voltage is VZ2-VBt5=16.7(V)-0,7
(V'l: stabilized at 16 (V)).

Since the internal bias voltage does not exceed 16Vi, there is no problem with the elements in the circuit network 1 in the 24V process. Since Veto of the NPN transistor 3 is 24V, the withstand voltage of the integrated circuit is 16 [V] [internal bias voltage IE
E) + 24 (V) (VCto) = 4c) ('V')...
(41) The withstand voltage can be set to 24oV.The current consumption of the integrated circuit at that time is as shown in Figure 17, and the current consumption Ice when the power supply input voltage is 40V is given by the following formula % Formula % , current consumption of 4 m to perform the original function of the integrated circuit
The current consumption is 1.87 times that of A, which is extremely poor power efficiency.The power consumption is: Power supply input voltage x Icc== m(V) x 7.4s
(m people] = 2s9 (mW') - - - ) cannot be contained at all.

Therefore, in order to reduce the power consumption of the integrated circuit, the circuit shown in FIG. 18 can be considered. The configuration and operation of this circuit are exactly the same as those shown in FIG.
This is an attempt to reduce the power consumption of the integrated circuit by bringing only the power to the outside of the integrated circuit, and to house it in a package with low power dissipation.The power consumption in the case of Figure 18 can be calculated using the following formula
Resistor power consumption (40 (V'1 - VZ2) x (IZ2
+IBM)= (40(V) -16,7(V))X(
3, as (mA) + o, 1 (mm) = sa4 (mW)
--= (8) Power consumption of integrated circuit of 18th factor = Power consumption of Figure 15 - Power consumption of resistor = 299 (mW
)-ss, 4 (mW) = 21e (mW)...
(9) Even in the case of Figure 18, it is impossible to fit it into a 14-pin full-body cage, and it is necessary to fit it into a package with a larger number of pins and higher power dissipation.Also, the integrated circuit has only one lead-out terminal. Since one extra bonding pad is required, the chip area becomes larger, and the total number of pins needs to be increased by one, which increases the cost of the integrated circuit. Since one more wire is added, the design is complicated, an extra base is required for one resistor, the cost increases by one resistor, and it goes without saying that power efficiency deteriorates.

In order to reduce the power consumption in the circuit shown in Fig. 15, there is a method of increasing the resistance value of the resistor 4, but if the resistance value of the resistor 4 is 6.5Ω, the potential difference between the input voltage and the internal bias voltage is
As shown in Figure 6, if the resistance 4, which is 2V in the low input voltage region (power supply input voltage is 18V or less), becomes high resistance, the potential difference between the power supply input voltage and the internal bias will increase, and the operation will be affected by that potential difference. The power input voltage range becomes narrower.

Problems to be Solved by the Invention In this conventional method, as mentioned above, the power consumption of the integrated circuit increases, and extra terminals are required to connect all the external resistors of the integrated circuit. was there.

The present invention solves these problems by providing a high-voltage bipolar integrated circuit using a low-voltage process without requiring external resistors or increasing the power consumption of the integrated circuit. The purpose is to

Means for Solving the Problem In order to solve this problem, the present invention uses a constant current source instead of a resistor and causes a constant bias current to flow through the constant voltage element, thereby increasing the power supply input voltage. This reduces current consumption and power consumption when

By realizing a high-voltage constant current source using a low-voltage process, it is possible to realize a high-voltage, low-power integrated circuit using a low-voltage process.

Embodiment FIG. 1 is a circuit diagram for explaining the basic principle of the present invention, in which the same reference numerals as those in FIGS. 16 and 18 indicate the same parts, and 5 is a constant voltage element; 6 is an impedance element for allowing a certain amount of base current to flow through the PNP transistor, and 9 is a resistor. These elements constitute a constant current source. Note that the internal bias voltage of the circuit network 1, constant voltage element 2, and HPN transistor 3 is 16Vj.
No voltage exceeding z is applied, and the elements in network 1 are 24
I am sure that there will be no problems with the V process.

Now, the operating current IZ2 required for the constant voltage element 2 and the base current 1rzs'fx required for the NPN transistor 3.
Assuming that each voltage is 0.1 mA as in the case of the figure, the operating voltage vZ of the constant voltage elements is 1.4 V, and the lowest DC current amplification factor of the P N P transistor is hyx gold 10, IC7:
IB3+IZ2=0.1(mA)+o,1(mA)=
o, 2 [mA)...= (1o)...
... (11) Resistance value of resistor 9 R91PNP transistor V! 1g
, VBt of the input side PNP transistor inside the current mirror 8 is 0. If it is a TV, f is calculated using the following equation.

LR7 = 3.1s (kΩ)... (12)P
The necessary base current IB7 of the NP transistor is determined by the following equation.

Il7 == hy/hyx = o, 2 (mA)
/ 1° = o, o2 (mA) - (13) The operating current of the constant voltage element 5 is 0.0 for the same reason as the constant voltage element 2.
If 1 mA is applied, I6 = Izs + Ia
y = o, 1 (mA) + o, o2 (m people) 20.12 [
m people] ... (14) Therefore, the electric current 6 flowing through the impedance element 6 needs to be set to 0-12 mA. Assuming that the impedance element 6 is, for example, a constant current element, the input voltage (I6 is constant, Izs, , Vzs, 1.R7, Il,7, I
C7, IZ2. Since VZ2 and Il5 are all constant, the relationship between power consumption and power supply input voltage is constant regardless of the input voltage, as shown by the solid line in Figure 2, and the current consumption Ice
1 is 4 mA as in the case of Fig. 15, so it can be obtained from the following formula.

IcC:= I + IZ2 + 11 = o, 12 (mA) + o, 1 (mA) + 4 (
[m people] = 4 + 22 [m people] ...... (16) Therefore, the current consumption for the integrated circuit to perform its original function is 4 mA.
The current consumption is 1.06 times that of the current consumption.In addition, the power consumption is as follows: Power consumption: Human power voltage x engineering CC = 4o(V”l x 422(!1 person)) = 16
It is as low as 9 (mW) (16) and can be accommodated in a 14-bin flat package, for example.

In the above equation (12), R9 is 3.18 Ω, which is a resistance value that is very easy to manufacture in an integrated circuit because a highly accurate resistor can be designed with a relatively small occupied area.

Figure 3 shows the relationship between the internal bias voltage and the power supply input voltage.The collector and emitter saturation voltage of a PNP transistor can be prevented from parasitic effects by applying a collector all, so it saturates to about 3V. . in this case,
t=i potential difference between input voltage and internal bias voltage in low input voltage region, i.e. Vex of NPN transistor 3
s is VCE3 = VBgs + V147- VBE
7 + Vzs=0.7CV)+0.3(V')-〇,
7 (V) + 1.4 (V) = 1.7 [■]...
(17), and the potential difference between the power supply input voltage and the internal bias voltage in the low input voltage region (power supply input voltage is 17.7V or less) is 1°7V, so the operating power supply input voltage range is (minimum operation of circuit network 1). Voltage) 1.7V to 40V. PNP
If you do not apply a collector wall to the transistor,
The collector and emitter saturation voltages are 0. Since the potential difference between the power supply input voltage and the internal bias voltage in the low input voltage region is 2.1 V, the operating power supply input voltage range is (
The minimum operating voltage of the circuit network is 2.1V to 40V.

Let us assume that the impedance element 6 is not a constant current element but a resistor. The potential difference between the power supply input voltage in the low input voltage region and the internal bias is 1.7V.

Assuming the internal bias voltage 'i16V, the resistance value R6 of the resistor is determined by the following equation.

= 136 (kΩ) ...... (18) When the power supply input voltage is 40 V, = = 0.284 (mi) --- (19) When the input voltage is 17.7 V or more, Even if it changes, Vzs does not change, so In7, In2, IZ2, In2, and L+ do not change.

Moreover, the power consumption Ice at a power supply input voltage of 40V is Ice = Ib + IZ2 + l1
= o, 2s4 (mA) + o, 1 (m people) + 4 (m people) =
4.3a (m people) ...... (20),
The relationship between current consumption and power supply input voltage is as shown by the broken line in FIG.

Therefore, the current consumption is 4 m to fulfill the original function of the integrated circuit.
This means that 1.1 times A is sufficient.

In addition, the power consumption is as follows: Consumption type crab human power voltage x consumption current = 40 (V) + 4.38 (mA) = 175 (mW
) and can be housed in a 14-bin flat package, for example.

In this way, whether the impedance element 6 is a constant current element or a resistor (actual embedded junction FET
(Since it has a composite characteristic of resistance characteristics and constant current characteristics, it cannot be said to be a perfect constant current element), and has almost the same characteristics as a constant current element. On the other hand, as the constant voltage element 5, a Zener diode or a diode between the emitter and the base of an NPN transistor is used, and as described above, the withstand voltage between the element and the negative input terminal 'l/El1 is 40 V or more. The constant current element used as the impedance element 6 is actually an embedded junction FET 1, which also has a withstand Ee of 40 V or more as described above.

As described above, both the base diffusion resistance and the bulk resistance of the impedance element 6 and the resistance 9 have a breakdown voltage of 401 or higher. A lateral type PNP transistor is usually used, but the input voltage between the collector and emitter of the NPN transistor 3 is aoV, which has a withstand voltage of 40V or more.
If the voltage does not exceed 24 Vi, no voltage will be applied. or,
A voltage higher than VZ2 is not applied to the constant voltage element 2. Therefore, even in the case of a 24V process, all elements are
i: It can withstand 40V.

4th sentence to Figure 10 are structural diagrams (cross-sectional views) of elements in a bipolar integrated circuit, and Figure 4 is an NPN transistor,
Figure 6 shows a lateral PNP transistor, Figure 6 shows a substray PNP transistor, Figure 7 shows a Zener diode, Figure 8 shows a bulk resistor, Figure 9 shows a base diffused resistor, and Figure 10 shows a buried junction FET. .

In the case of the NPN transistor shown in Figure 4, Vcxo is the breakdown voltage of the three layers (N epitaxial layer - 2nd layer - 1st layer) and the collector-base breakdown voltage when the emitter is open (hereinafter referred to as vcKo).
That is, the following equation generally holds true between the breakdown voltage between the N epitaxial layer and the P layer.

(n: takes a value of 3 to 4 for NPN transistors) (2
1) Transforming the formula, “” = ” hrx + 1 − Vctto ・
−・−(22) For example, in a process that guarantees 24V (j) of Vc++o, VCBO will be as follows (Vono
Considering the lowest case, hyx is assumed to be the lowest value of 40, and n is assumed to be the highest value of 4). That is, ``'''''9-24: 60.7 (Vl・-・-(
23) In the VClo (7) 247 (7) process, Vcao is 60 and a Vf can be guaranteed.

Figure 6 shows the case of a lateral PNP, where Vcao and the withstand voltage between the emitter and base when the collector is open (hereinafter referred to as Vra)
It can be understood by comparing FIG. 4 and FIG. 5 that the voltage (referred to as "0") has the same breakdown voltage as VcBo of the NPN transistor.

In Fig. 5, the base width wb is 6 base width, which is determined by the mask rule, so it is necessarily wider than the base width in Fig. 4, and the base (■ epitaxial layer) and emitter Since the impurity ratio between the base (P layer) and the emitter (N layer) of an NPN transistor is small compared to the 0 degree impurity ratio of the base (P layer) and emitter (N layer), the hrx is very low, about 20 at most. , Also, since Wb is wide, NP
The variation in hrx is smaller than that of an N transistor.

(23) Equation (7) Result Kj, Vcao f 60.7
When V is calculated and Veto f is calculated using equation (21), the result is as follows. (In a PNP transistor, n generally takes a value of 8 or more, so n is set to 8) 0, that is, VCXO 40'I f can be guaranteed.

Also, by further widening the base width Wb in FIG.
y++i is lowered, hyg variation is reduced, Vc
It is also possible to increase xo f. Depending on the design of the mask, it is possible to guarantee Veto f 40 V or more. For example, if the maximum hyxi can be increased to 10, then Vczo can be guaranteed up to 45V.0 Figure 6 shows the case of a substrate PNP transistor.
In this case, as in the case of the lateral PNP transistor in FIG. 6, the base width wb is wide and the ratio of impurity concentration between the base and the emitter is small, so
It is a little lower than the transistor, and furthermore, P becomes the collector.
Since the impurity concentration of the substrate is much lower than the P layer in case of lateral PNP transistors, vCBO
becomes higher. Therefore, it can be said that Veto of the substrate PNP transistor is higher than that of the lateral PNP transistor.

Figure 7 shows the case of a Zener diode, with P and N
A PM junction is formed between the layers, and a Zener characteristic that breaks down at a predetermined voltage is obtained. In this case, the impurity concentration of the P layer #
overlaps with P isolation, so it is higher than the P layer of the NPN transistor, and the breakdown voltage is V of the NPN transistor.
x! It will be lower than to.

FIG. 8 shows the case of bulk resistance, and T1. T2 and N
Since an iPN junction cannot be formed between the epitaxial layer and the epitaxial layer, there is no actual breakdown voltage.

FIG. 9 shows the case of a base diffused resistor, and the P layer (T1.
It can be understood by comparing FIGS. 4 and 9 that the breakdown voltage between T2) and the N epitaxial layer is the same as Vcao of the NPN transistor.

Figure 10 shows the case of a buried type junction FET.
It can be understood by comparing FIG. 4 and FIG. 8 that the breakdown voltage between the N epitaxial layer and the P layer is the same as Vaao of the NPN transistor.

The breakdown voltage between the elements shown in FIGS. 4 to 10 and the negative input terminal Vxz (P substrate) is determined by the N epitaxial layer and the P substrate, the N epitaxial layer and the P separation, lJ'pl
The impurity concentration of the P substrate is even lower than that of the N epitaxial layer, and the impurity concentration of the P substrate is lower than that of the N epitaxial layer.

Since the impurity concentration of at least one of N is low, the withstand voltage between the element and the negative input terminal VEz is higher than Vcao of the NPN transistor. Therefore, the guaranteed breakdown voltage of a process is generally expressed by the Vczo of an NPN transistor, but in the case of a bipolar integrated circuit, it can be said that the breakdown voltage of elements other than the NPN transistor is at a considerably higher level than the guaranteed voltage of the process.

FIG. 11 is a circuit diagram of a specific example of the present invention, in which the same reference numerals as those in FIG. 1 indicate the same parts, and 12.
13 is two NPN transistors diode-connected between the base and emitter as a constant voltage element, 11 is a buried type junction yFET as an impedance element 6 (
An actual embedded junction FET is a combination of resistance characteristics. In addition, in order to obtain an operating voltage IE of 16.7 V, the constant voltage element 2 is connected to the emitter and base of the NPN transistor by connecting the 2-1 t'L of the emitter and base listening diodes 14 and 15.
I use it twice.

FIG. 12 is a circuit diagram of another embodiment of the present invention, in which parts having the same reference numerals as those in FIG.
6 is the base-emitter diode 1 shown in the 10th factor
2. A constant voltage is used instead of 13, a Zener diode is used as the bevel 6, and a resistor is used as the impedance element 17i-i.Since this resistor 17 has a high resistance, in order to reduce the area occupied by the impedance element 6, In general, bulk resistance is more important than base diffusion resistance.

FIG. 13 is a circuit diagram of still another specific example of the present invention.
The same reference numerals as those in the figure indicate the same parts, and 18 and 19 are Zener diodes connected in series with each other to function as constant voltage elements 2. A stabilized voltage Vz+q is obtained from the midpoint of the series connection. 20 is NPN
transistor, 21 is a resistor, 22 and 23 are NPN transistors using base-emitter diodes, 2
4°25, 26, 27 and 28 are PNP transistors forming a current mirror. Since VZI is stabilized, the emitter current of NPN transistor 2o!
20 is a constant current, Vzlq shows a positive temperature characteristic, and the resistor 21 also shows a positive temperature characteristic, but in general, a resistor shows a higher temperature characteristic, so the temperature characteristic of Ix2o is set close to zero. For this purpose, diodes 22 and 23 are connected in series.

In addition, IC7 becomes a constant current that flows to Zener diode 19, and Vzlqf<occurrence, Vz+q K J-1)
Since l1120 becomes a constant current, Ix2o is stabilized in two stages, and also becomes a very perfect constant current without temperature characteristics. Current Ic+ of NPN transistor 20
o becomes a very perfect constant current, and the output of the current mirror connected by it is Is+, s2゜Iss
,... and multiple perfect constant-accumulation bullets can be obtained.

In addition, between the collector and emitter of the PNP transistor shown in FIGS. 11 to 13: 1 The withstand voltage of this process is 24V.
A voltage far exceeding f is applied. In this case, a voltage close to 40V is applied, so in order to sufficiently guarantee the withstand voltage of 40V as an integrated circuit, in the case of a lateral PNP transistor,
Base width wbl of PNP transistor 7 Base width (P
It is better to make it wider than the mask rule between 4 base diffusions).

Effects of the Invention As described above, according to the present invention, the following effects can be obtained.

(1) By simply increasing the number of integrated circuit elements by a few points, it is possible to create a high voltage integrated circuit by using all low voltage processes.

(2) A process with low breakdown voltage is highly versatile and the cost of the process itself is low.

(3) Although the number of elements increases slightly, in an integrated circuit with a large number of elements, the increase in chip area due to the increase in the number of elements is negligible. In a process with low breakdown voltage, the mask rule can be made small, the impurity concentration is high, the resistivity is low, and the emitter area can be made small. Compared to the case where a process is used, the chip area can be extremely reduced and costs can be reduced.

(4) Since the chip area can be reduced, the yield is good.

(5) High voltage is applied to the aluminum wiring, causing parasitic MOS
- FETs are configured and channels are formed, which may cause malfunctions, but in order to completely prevent such phenomena,
Usually, it is common to apply a channel stopper,
In the case of the present invention, since the number of elements to which high voltage is applied is limited, high voltage is applied to the aluminum wiring only in limited places, so there are extremely few places to insert the channel stopper, which also causes high voltage. Chip area can be reduced while maintaining surface earth pressure.

(6) l'l! The increase in current per cost is also much lower than in the cases of Figures 16 and 18, and is around a factor of 10 (1
, 06 or 1.1 times), the power consumption is small, and it can be housed in a package (such as a flat package) with low power dissipation intended for high-density packaging. It is also effective in other applications aimed at low power consumption.

) As shown in Figure 18, there is no need to increase the number of pins on the integrated circuit by one, there is no need to attach an external resistor, there is no need to increase the chip area due to the bonding pad, and there is no cost amplifier.
There is no increase in the base of external resistors.

(s) The voltage drop between the collector and emitter of the NPN transistor in diagram FJ1 is very low, about 1.7V, so
The minimum power supply input voltage is the minimum operating voltage of the circuit network added by 1.7V, and the operating power supply input voltage range only needs to be narrowed by 1.7V compared to one made using a high-voltage process.

(9) If a high voltage process is used, hyx will be lower, and the number of elements in the circuit network will inevitably increase to achieve the same function, resulting in a larger chip area and reduced functionality. , this does not happen in the case of non-invention because a process with low breakdown voltage can be used.0(10)
The present invention is a very effective means when producing an integrated circuit with a withstand voltage higher than that of a high-voltage process.

(11) As shown in FIG. 13, by utilizing the stable voltage of the constant voltage element of the present invention, it is possible to create any number of constant current sources with extremely high stability and perfect temperature characteristics close to zero.

[Brief explanation of drawings]

Fig. 1 is a basic circuit diagram of the present invention, Figs. 2 and 3 are operational characteristic diagrams of the circuit shown in Fig. 1, Figs. 4 to 10 are cross-sectional views of integrated circuit elements, and Fig. 11. Figures 13 to 13 are circuit diagrams of specific examples of the present invention, Figure 14 is a circuit diagram of a conventional example, Figure 15 is a circuit diagram of an example of an improvement plan that improves the conventional example, and Figures 16 and 17 are circuit diagrams of a conventional example. The operating characteristic diagrams of the circuits shown in FIGS. 14 and 15, and FIG. 18 is a circuit diagram of an example of a further improved improvement plan.
3... NPN transistor, 6... Impedance element, 7... PNP transistor, 9... Resistor. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
11 times 9 weeks? -4Monosui No. 3---NPNF Lanosis 7 5-Ichinoya Tamaki No. 6---U/Gone Iriki No. 7---PNP )-7n) Iri 7 Figure 1 Data scoop a Figure 2 Figure 3/17V 4θV 4th
Figure Flewaku Figure 7 η Seed Anode EE Figure 8 Figure 9 V? ξ Figure 10 EE Figure 11 /2
．． t3--, VP#-ra°7 puff Fig. 12
/6-Z air diode Figure 15 Figure 16 Inner call \ia person t,? L 4 break tJ tvl

Claims (1)

[Claims] a first constant voltage element whose one end is connected to a positive power input and whose other end is connected to a negative power input via an impedance element connected in series; a base is connected to the impedance element and the first constant voltage; a PNP transistor connected to a connection point with the element and whose emitter is connected to the positive power input via a resistor; and a second constant voltage element connected between the collector of the PNP transistor and the negative power input. and,
The base is connected to the collector of the PNP transistor and the second transistor.
an NPN transistor connected to a connection point with a constant voltage element and having a collector connected to the positive power input, the bipolar integrated circuit obtaining a bias voltage from the emitter of the NPN transistor.