JPH04256216A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To realize a practical and stable operation when a semiconductor integrated circuit is made by providing a second I<2>L circuit in the base of the NPN transistor of an interface circuit. CONSTITUTION:The second I<2>L circuit 12 is provided for the base of the NPN transistor 7 in the interface circuit 2. A lateral PNP transistor 3 and a vertical NPN transistor 4 constitute a first I<2>L circuit 1, and an output terminal 16 as against an input terminal 6 is connected to the base of the emitter ground NPN transistor in the interface circuit 2. In the circuit constitution, the output terminal 16 of the first I<2>L circuit 1 is connected to the input terminal 17 of the second I<2>L circuit 12, and the first I<2>L circuit 1 causes the injector current of the second I<2>L circuit 12 to flow as a load current. Namely, the injector current flowing into a second injector power terminal 15 flows into a first injector power source 5 as it is.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to semiconductor circuits, and in particular to I2L (Integrated Injector) circuits.
TECHNICAL FIELD The present invention relates to a semiconductor circuit having a logic circuit using integrated injection logic (on Logic) and an output interface.

0002

2. Description of the Related Art In general, an I2L is a switching transistor provided in a single island region formed on the same semiconductor substrate, and a lateral transistor whose base is grounded for injecting carriers into the switching transistor. P
It has a current source constituted by an NP transistor, and the collector output of the switching transistor is controlled by the base input to the switching transistor.

[0003] FIG. 3 shows the I2 L
It shows a basic interface circuit with peripheral circuits and I2 which operates as one inverter.
It consists of an L circuit 1 and an interface circuit 2.

The I2L circuit 1 includes a horizontal PNP transistor 3 whose base is grounded and a vertical NPN transistor 4 whose emitter is grounded. And horizontal PNP
The emitter of the transistor 3 is connected to the injector power supply terminal 5.
The collector is connected to the base of the vertical NPN transistor 4 and the input terminal 6. This I2 L circuit 1
The output terminal of is the collector of the vertical NPN transistor 4.

The interface circuit 2 consists of an NPN transistor 4 whose emitter is grounded and two resistors 8 and 9. The resistor 8 has one end connected to the high-level power supply terminal 10 and the other end connected to the base of the NPN transistor 4. Further, the resistor 9 has one end connected to the high-level power supply terminal 10 and the other end connected to the collector of the NPN transistor. Output terminal 11 of this interface circuit 2
is the collector of the NPN transistor 4.

[0006]

The circuit shown in FIG. 3 described above has the following drawbacks for the reasons described below. (1) A large resistance value is required as the resistor 8. Therefore, when integrated into a circuit, it occupies a very large area. Furthermore, it becomes impossible to obtain a sufficient drive current to make the NPN transistor 7 conductive. (2) In order to be able to drive the NPN transistor 7 at all times, the injector current (base current of the vertical NPN transistor 4) must be set to a large value with sufficient margin, resulting in an efficient and stable interface. It is difficult to realize the circuit.

The reason for this will be explained below. First, the circuit shown in FIG. 3 operates as follows.

In FIG. 3, the collector current of the horizontal PNP transistor 3 constituting the I2L circuit 1 is IC3, the base current of the vertical NPN transistor 4 is IB4, the current amplification factor is hFE4, and the NPN constituting the interface circuit 2 is The current amplification factor of transistor 7 is hFE7,
If the resistance values of the resistors 8 and 9 are R8 and R9, respectively, the voltage of the high-level power supply terminal 10 is V10, and the emitter-collector saturation voltages of the vertical NPN transistor 4 and NPN transistor 7 are VCE4 and VCE7, respectively, then the vertical NPN transistor The base current IB4 flowing to the base of 4 is IB4=IC3. Next, when the vertical NPN transistor 4 is in a conductive state, its collector current IC4 is expressed by the following equation (1). IC4=(V10-VCE4)/R8

(1) Here, in order to flow the collector current IC4, IB4×hFE4 > IC4

It is necessary to satisfy the condition (2).

Now, from equations (1) and (2), vertical NP
Given the characteristics of the N transistor 4 and the high power supply voltage, in order to satisfy the condition of equation (2), the resistance value R8
It turns out that must be large. The value is the current amplification factor hFE4 of the vertical NPN transistor 4.
The resistance value R8 increases as hFE4 decreases.

By the way, in the I2L circuit 1 and interface circuit 2 shown in FIG.
The vertical NPN transistor 4 of the L circuit 1 has an opposite relationship between the collector and emitter compared to the NPN transistor 7 of the interface circuit 2.

[0011] Such a transistor is generally called a reverse transistor, but the current amplification factor of this reverse transistor is very small compared to a normal NPN transistor, and even a transistor improved to I2L cannot be used at a practical level. 2
It's only about ~10.

For example, in equations (1) and (2), if hFE4 = 3 and IB4 = 20 μA, IC4
<60 μA. And, if V10=5V, VC
When E4 =0.1V, R8 >81.7kΩ.

[0013] In order to realize such a high resistance on a semiconductor integrated circuit, a very large area is required, which is impractical.

[0014] Furthermore, the accuracy of the absolute value of the resistance is not sufficient,
Considering manufacturing variations in IB4, hFE4, and R8, the resistance value R8 must be made even larger.

Therefore, in the conventional circuit shown in FIG. 3, it becomes impossible to obtain a sufficient drive current necessary for the NPN transistor 7 of the interface circuit 2 to conduct.

Furthermore, in order to be able to drive at all times, it is necessary to set the current value of the injector current IB4 to a large value with sufficient margin. For this reason, it is difficult to realize an efficient and stable interface circuit using conventional circuits.

The present invention has been made in view of the problems of conventional semiconductor circuits as described above, and provides an interface circuit and an I2L that are practical and operate stably when made into a semiconductor integrated circuit. The purpose of the present invention is to provide a semiconductor circuit with the following features.

[0018]

[Means for Solving the Problems] The semiconductor circuit of the present invention includes:
A first integrated implant consisting of a first NPN bipolar transistor of vertical structure and a first PNP bipolar transistor of lateral structure integrally formed with the base of this first NPN bipolar transistor as the collector and the emitter as the base. A second NPN bipolar transistor comprising a logic circuit, a second NPN bipolar transistor with a vertical structure, and a second PNP bipolar transistor with a horizontal structure integrally formed with the base of the second NPN bipolar transistor as the collector and the emitter as the base. 2 integrated injection logic circuits and a third NPN bipolar transistor at the output, the output terminal of the first integrated injection logic circuit, the input terminal of the second integrated injection logic circuit and the base of the third NPN bipolar transistor. and the first integrated injection logic circuit is connected to the second integrated injection logic circuit.
The injector current of the integrated injection logic circuit is used as the load current to drive the third NPN bipolar transistor, and the third
The output of the first integrated injection logic circuit is taken out from the collector of the NPN bipolar transistor.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. 1 and 2 are circuit diagrams showing one embodiment of the present invention.

The difference between this embodiment and the conventional circuit shown in FIG. 3 is that the NPN transistor 7 of the interface circuit 2
The point is that a second I2L circuit 12 is provided at the base of the circuit in place of the resistor R8.

As shown in FIG. 1, the second I2L circuit 12 includes a second horizontal PNP transistor 13 and a second vertical NPN transistor 14.

The second lateral PNP transistor 13 has an emitter connected to the second injector power supply terminal 15,
The collector is the first I2. The output terminal of the L circuit 1 (collector of the first vertical NPN transistor 4) 16 and the second vertical NPN
It is connected to the base of the PN transistor 14, and the base is connected to the first injector power supply terminal 5.

The second vertical NPN transistor 14 has a base connected to the output terminal of the first I2L circuit 1 and a collector of the second horizontal PNP transistor 13, and an emitter connected to the first injector power supply terminal 5. The base of the second lateral PNP transistor 13 is connected to the same potential as the base of the second lateral PNP transistor 13.

The circuit operation of this embodiment will be described below. In FIG. 1, a horizontal PNP transistor 3 and a vertical N
The PN transistor 4 constitutes the first I2L circuit 1,
The output terminal 16 for the input terminal 6 is connected to the base of a common emitter NPN transistor 7 of the interface circuit 2 . This circuit configuration is the same as the conventional circuit shown in FIG. 3, but the feature of this embodiment is that the first I2L
The output terminal 16 of the circuit 1 is connected to the input terminal 17 of the second I2 L circuit 12, and the first I2 L circuit 1 is at a point where the injector current of the second I2 L circuit 12 flows as a load current. .

That is, the first I2L circuit 1 and the second I2L circuit 12 are stacked in two stages, and the first injector power supply 5 has an inflow to the second injector power supply terminal 15. The injector current will continue to flow.

Here, as shown in FIG. 2, normally I2
In L, a plurality of gates are connected in parallel to the same injector power supply, so if the number of gates in the first stage and the second stage are the same, the injector currents of each stage will be the same.

Therefore, in this embodiment, the first
The collector currents of the horizontal PNP transistor 3 and the second horizontal PNP transistor 13 are approximately equal, and the load of the first vertical NPN transistor 4 is given a load current equal to its base current.

Now, the collector current IC3 of the first lateral PNP transistor 3 is set to IC3=20 as in the conventional case.
When μA, a collector current IC2 of the same magnitude flows through the collector of the second lateral PNP transistor 13, where IC13 = IC3 = 20 μA.

[0029] And IC3=IB4=20μA, hF
Since E=3, the first vertical NPN transistor 4 has IB
This means that a collector current of up to 4×hFE4 =60 μA can flow.

Next, if IB4×hFE4 >IC13 is satisfied, the NPN transistor of the interface circuit 2 is necessarily in a non-conductive state. In addition, if the first and second lateral PNP transistors 3 and 13 have the same shape, the relative variation between IC3 and IC13 is very small, and it can be considered that IC3=IC13 holds true in any case.

Further, the current amplification factor hFE7 of the NPN transistor 7 of the interface circuit 2 is the same as that of the first I2L
Current amplification factor hFE of vertical NPN transistor 4 of circuit 1
IC13 is very large compared to 4, so IC13 is
The base current may be sufficient to cause the NPN transistor 7 to become conductive.

From the above, the I2L interface circuit in this embodiment can operate very stably.

It should be noted that the present invention is not limited to the above-described embodiments. It is clear that the same effect can be obtained by changing the collector area of the first vertical NPN transistor 4 and increasing the drive ability of this transistor.

[0034]

[Effects of the Invention] As explained above, according to the present invention,
Not only is the connection between I2L and the peripheral circuits very stable, but it is also possible to construct a practical interface that is sufficiently usable even against fluctuations in the collector current of the lateral PNP transistor. In addition, it is possible to provide an interface circuit that combines only I2L, does not require the use of high resistance, and is very suitable for implementation into a semiconductor integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a logic circuit using the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram of an example of a conventional I2L and interface circuit.

[Explanation of symbols]

1, 12 I2 L circuit 2 Interface circuit 3, 13 Horizontal PNP transistor 4, 14
Vertical NPN transistors 5, 15 Injector power supply terminals 6, 17 Input terminal 7 NPN transistors 8, 9 Resistor 10 High-level power supply terminals 11, 16 Output terminal

Claims (1)

[Claims] 1. Consists of a first NPN bipolar transistor with a vertical structure and a first PNP bipolar transistor with a lateral structure integrally formed with the base of the first NPN bipolar transistor as the collector and the emitter as the base. A first integrated injection logic circuit, a second NPN bipolar transistor with a vertical structure, and a second PNP bipolar transistor with a horizontal structure integrally formed with the base of the second NPN bipolar transistor as the collector and the emitter as the base. a second integrated injection logic circuit consisting of a transistor, and a third NPN bipolar transistor at the output, the output terminal of the first integrated injection logic circuit, the input terminal of the second integrated injection logic circuit, and the third integrated injection logic circuit. The first integrated injection logic circuit drives the third NPN bipolar transistor using the injector current of the second integrated injection logic circuit as a load current, and the collector of the third NPN bipolar transistor is connected to the base of the NPN bipolar transistor. A semiconductor circuit, characterized in that an output of a first integrated injection logic circuit is taken from.