JPS60182817A - I2l circuit - Google Patents

I2l circuit

Info

Publication number
JPS60182817A
JPS60182817A JP3800884A JP3800884A JPS60182817A JP S60182817 A JPS60182817 A JP S60182817A JP 3800884 A JP3800884 A JP 3800884A JP 3800884 A JP3800884 A JP 3800884A JP S60182817 A JPS60182817 A JP S60182817A
Authority
JP
Japan
Prior art keywords
circuit
output
transistor
terminal
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3800884A
Other languages
Japanese (ja)
Inventor
Koji Shinohara
幸児 篠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3800884A priority Critical patent/JPS60182817A/en
Publication of JPS60182817A publication Critical patent/JPS60182817A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To set easily a desired output signal amplitude and an output operating level suitable for high frequency signal processing by providing a differential amplifier circuit as an output circuit of an I<2>L circuit. CONSTITUTION:When a level of an input 3 is at H, transistors (TR) Q5 and Q7 are turned on/off respectively, a base current is applied from an injector current supply TRQ8 to a TRQ9 of a differential amplifier circuit 11, the TRQ9 is turned on and an output 5 goes to H. A potential of nearly (V1-V2)/2 obtained by dividing a potential difference between a potential V1 at a common injector terminal and a potential V2 at a common emitter terminal with resistors is impressed to the differential amplifier 11 as a reference potential and an output signal amplified to a desired amplitude is obtained by setting properly the values of a power supply voltage, a resistor R5 and a constant current source CS. Since the reference potential at the interface is set optionally by setting values of resistors R3, R4, an output of the I<2>L circuit 6 is inputted directly to an output circuit comprising the differential amplifier 11.

Description

【発明の詳細な説明】 〔技術分野〕 本発明はIL半導体回路、特にその出力を取り出す出力
回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an IL semiconductor circuit, and particularly to an output circuit that extracts the output thereof.

〔従来技術〕[Prior art]

I”L半導体回路の出力信号を取り出して異なる素子等
で構成された信号処理回路等へ伝達する場合にはIL 
半導体回路からインタフェース回路を介して出力を取り
出し次段の信号処理回路岬に加えられる。
I''L When extracting the output signal of a semiconductor circuit and transmitting it to a signal processing circuit etc. composed of different elements, IL is used.
The output is taken out from the semiconductor circuit via the interface circuit and applied to the next stage signal processing circuit.

第1図はインタフェース回路を備えたIL 回路の従来
例であり、トランジスタQl、Q2より構成されたIL
牛渚体回路6の出力端子であるトランジスタQ2のコレ
クタは抵抗孔lを介して聾源電圧端子1に接続されると
ともにエミッタが接地されたトランジスタQ3のペース
に!され、トランジスタQ3のコレクタは、抵抗R2を
介して電源聾圧端子1に接経されるとともに、出力端子
5に接続されている。
Figure 1 shows a conventional example of an IL circuit equipped with an interface circuit, and is composed of transistors Ql and Q2.
The collector of the transistor Q2, which is the output terminal of the Ushinagi body circuit 6, is connected to the deaf source voltage terminal 1 through the resistor hole l, and the emitter is connected to the grounded transistor Q3. The collector of the transistor Q3 is connected to the power supply terminal 1 via the resistor R2, and is also connected to the output terminal 5.

前記従来回路例の第1図において、入力端子3が″′H
#レベルのとき、インジェクタ電流供給トランジスタQ
lよりトランジスタQzのベースへ電流が供給され、ト
ランジスタQ2は飽和状態とカリ、トランジスタQ3の
ペース電位社、トランジスタQ2の飽和物圧となるため
、トランジスタQ3はし中断状態と々る。従ってトラン
ジスタQ8のコレクタに接続された出力端子5の電位は
11源電圧端子1の電位まで上がる。入力端子3が”L
”レベルとなってインジェクタ電流供給トランジスタQ
lからの電流を流し込むと、トランジスタQ2はし中断
状態となりトランジスタQ3のベースには、電源電圧端
子1より抵抗R1を介して電流が供給され、トランジス
タQ3は飽和状態とカリ、出力端子5の電位はトランジ
スタQ3の飽和電圧まで下がる。
In FIG. 1 of the conventional circuit example, the input terminal 3 is
# When level, injector current supply transistor Q
A current is supplied from l to the base of the transistor Qz, and the transistor Q2 becomes saturated, the potential of the transistor Q3 becomes the saturated physical pressure of the transistor Q2, and the transistor Q3 goes into an interrupted state. Therefore, the potential of the output terminal 5 connected to the collector of the transistor Q8 rises to the potential of the 11 source voltage terminal 1. Input terminal 3 is “L”
” level and injector current supply transistor Q
When the current from l flows into the transistor Q2, the transistor Q2 becomes in an interrupted state, and current is supplied to the base of the transistor Q3 from the power supply voltage terminal 1 through the resistor R1, and the transistor Q3 is in the saturated state, and the potential of the output terminal 5 is reduced. falls to the saturation voltage of transistor Q3.

以上のようにIL 半導体回路の出力信号振幅の変化に
対して、出力端子5には、電源〜圧端子1の電位とトラ
ンジスタQ3の飽和電圧の2値をとる信号として出力さ
れる。
As described above, in response to changes in the output signal amplitude of the IL semiconductor circuit, a signal is outputted to the output terminal 5 as a signal that takes two values: the potential of the power supply to voltage terminal 1 and the saturation voltage of the transistor Q3.

しかしながら、上記従来回路例においては、トランジス
タQBが飽和した場合、トランジスタの蓄積時間によっ
てコレクタの立上りに遅延時ルjが生じ、特に高周波の
入力信号に対しては出力信号が追従できず波形左きりが
生じ次段の信号処理回路への信号伝達が可能な周波数範
囲が非常に限定される。
However, in the above conventional circuit example, when the transistor QB is saturated, a delay occurs in the rise of the collector due to the accumulation time of the transistor, and the output signal cannot follow particularly high frequency input signals, resulting in a left-handed waveform. occurs, and the frequency range in which signals can be transmitted to the next stage signal processing circuit is extremely limited.

さらに、出力端子5に出力できる信号振幅は、抵抗R2
とトランジスタQ2に流すことのできる電流との積によ
って決定されるが、トランジスタQ2に流すことのでき
る電流はIL 半導体回路6のインジェクタ電流供給ト
ランジスタQ1に流れるインジェクタ電流によって制限
されるため、出力信号振幅もインジェクタ電流に制限さ
れ所望の出力信号振幅、出力動作レベルが得られ々い。
Furthermore, the signal amplitude that can be output to the output terminal 5 is determined by the resistance R2
However, since the current that can be passed through transistor Q2 is limited by the injector current that flows through injector current supply transistor Q1 of IL semiconductor circuit 6, the output signal amplitude Also, the desired output signal amplitude and output operation level cannot be obtained because the injector current is limited.

この不具合を改善する手段としては、電源電圧端子1の
電位を上げ、負荷抵抗R2を大きくする方法がおる。し
かしながら、この場合においては、負荷抵抗kL2が大
きくなることによりて出力端子5において浮遊容量と抵
抗R2との積によって得られる時定数が大きくなり、高
周波信号伝達には適さない。
As a means to improve this problem, there is a method of increasing the potential of the power supply voltage terminal 1 and increasing the load resistance R2. However, in this case, as the load resistance kL2 becomes larger, the time constant obtained by the product of the stray capacitance and the resistance R2 at the output terminal 5 becomes larger, which is not suitable for high frequency signal transmission.

〔発明の目的〕[Purpose of the invention]

本発明の目的は高周波信号処理に適し、しかも所望の出
力信号振幅出力動作レベルが容易に設定することができ
る出力回路を備えたIL 回路を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide an IL circuit that is suitable for high frequency signal processing and that is equipped with an output circuit that allows a desired output signal amplitude output operation level to be easily set.

〔発明の構成〕[Structure of the invention]

本発明によれば、共通インジェクタ端子、共通エミッタ
端子間に、それぞれ第1の抵抗と第2の抵抗を介して電
圧が印加され、出力端子にインジェクタが接続されたI
L 半導体回路と、一方の入力端子が前記出力端子に接
続され、他方の入力端子に前記共通インジェクト端子と
前記共通エミッタ端子の電圧差を分割して発られる電圧
が即用された差動増幅回路とを具備し、該差動増幅回路
の出力端子よ炒前記I”L 半導体回路の出力を増り出
すIL 回路が得られる。
According to the present invention, a voltage is applied between the common injector terminal and the common emitter terminal via the first resistor and the second resistor, respectively, and the injector is connected to the output terminal.
L: A semiconductor circuit, and a differential amplifier in which one input terminal is connected to the output terminal, and the voltage generated by dividing the voltage difference between the common inject terminal and the common emitter terminal is immediately applied to the other input terminal. An IL circuit is obtained which increases the output of the I''L semiconductor circuit by connecting the output terminal of the differential amplifier circuit to the output terminal of the differential amplifier circuit.

〔実施例〕 ゛ 次に図面を参照して本発明を具体的に説明する。[Example]゛ Next, the present invention will be specifically described with reference to the drawings.

第2図は、本発明による出力回路を伸1えたLL回路の
実施回路例でおる。第2図において、2つの差動入力端
子9,10及び出力端子5を具備した差動増幅回路11
は、トランジスpQ・、Qzo、負荷抵抗胞、定電流源
C8より構成されている。
FIG. 2 shows an example of an implementation circuit of an LL circuit which is an extension of the output circuit according to the present invention. In FIG. 2, a differential amplifier circuit 11 comprising two differential input terminals 9 and 10 and an output terminal 5
is composed of transistors pQ., Qzo, a load resistance cell, and a constant current source C8.

トランジ:x、 p Q4 +QS、Qe pQ’ +
Q”よね構成された12L半導体回路6の共通インジェ
クタ端子2は抵抗′EL3を介して%源電圧端子1に接
続されて電圧が印加される。共通エミッタ端子7は抵抗
R4を介して接地端子8に接続される。インジェクタ電
流供給トランジスタQ8のコレクタが接続されたトラン
ジスタQ7のコレクタは、差動増幅回路11の一方の入
力端子9に接続される。差1増幅回路11の他方の入力
端子10には、抵抗R6を介して共通インジェクメ端子
2に接続されるとともに、抵抗R7を介して共通エミッ
タ端子7に接続されている。
Transition: x, p Q4 +QS, Qe pQ' +
The common injector terminal 2 of the 12L semiconductor circuit 6 having a Q" parallel configuration is connected to the % source voltage terminal 1 through a resistor 'EL3, and a voltage is applied thereto. The common emitter terminal 7 is connected to the ground terminal 8 through a resistor R4. The collector of the transistor Q7, to which the collector of the injector current supply transistor Q8 is connected, is connected to one input terminal 9 of the differential amplifier circuit 11. The collector of the transistor Q7 is connected to the collector of the injector current supply transistor Q8. is connected to the common injector terminal 2 via a resistor R6, and to the common emitter terminal 7 via a resistor R7.

入力端子3が共通エミッタ端子7の1′位を基準として
″′H″レベルの入力状態となると、トランジスタQ、
は飽和状態となり、トランジスタQsのコレクタには、
インジェクタ電流供給トランジスpQsよねインジェク
タ電流が供給され、トランジスタQ7のペース電位は、
共通エミクタ端子7の電位にトランジスタQ+の飽和電
圧を加えた電圧まで上がり、トランジスタQ7はし中断
状態と力る。したがってインジェクタ電流供給トランジ
スタQaより差動増幅回路11の入力端子9へ電流が供
給され、入力端子9において6H#レベル状態となる。
When the input terminal 3 enters the input state of ``H'' level with reference to the 1' position of the common emitter terminal 7, the transistor Q,
becomes saturated, and the collector of transistor Qs has
The injector current is supplied to the injector current supply transistor pQs, and the pace potential of the transistor Q7 is
The potential of the common emitter terminal 7 rises to a voltage equal to the saturation voltage of the transistor Q+, and the transistor Q7 is placed in an interrupted state. Therefore, a current is supplied from the injector current supply transistor Qa to the input terminal 9 of the differential amplifier circuit 11, and the input terminal 9 attains the 6H# level state.

次に、入力端子3が共通エミッタ端子7の電位を基準と
して6L″レベルの入力状態となるとトランジスタQs
はし中断状態となりインジェクタ電流供給トランジスタ
Q6よりトランジスタQ7のベースへインジェクタ!#
が供給されてトランジスタQ7は飽和状態となる。よっ
て、インジェクタ電流供給トランジスタQ8よりトラン
ジスタQ7のコレクタにインジェクタ電流が供給され、
差動・増幅回路11の入力端子9において″′L#レベ
ル状態となる。
Next, when the input terminal 3 reaches an input state of 6L'' level with reference to the potential of the common emitter terminal 7, the transistor Qs
Then, the injector is in an interrupted state and the injector current is supplied from the transistor Q6 to the base of the transistor Q7! #
is supplied, and the transistor Q7 becomes saturated. Therefore, the injector current is supplied from the injector current supply transistor Q8 to the collector of the transistor Q7,
The input terminal 9 of the differential/amplifier circuit 11 becomes ``'L# level state.

一方、差動増幅回路11においては、一方の入力端子1
0には共通インジェクタ端子の電位vl、と共通エミッ
タ端子の電位■2との電位差を抵抗Ra。
On the other hand, in the differential amplifier circuit 11, one input terminal 1
0, the potential difference between the common injector terminal potential vl and the common emitter terminal potential 2 is resistor Ra.

R7で分割して得られる。tlぼ(Vl−V2)/2に
選ばれた基準電位が与えられており、他方の入力端子9
には共通工きツタ端子の電位■2を基準として前述の2
値のIT H#、″′L”をとる信号が入力される。し
たがって、IL半導体回路6の入力端子3のH”、″L
#レベルの入力信号に応じて、差動増幅回路11の出力
端子5よ#)”H# 、 * I、 #状態の出力信号
が出力される。ここで差動増幅回路11は、前記入力信
号に対して電源電圧、抵抗Rs。
Obtained by dividing with R7. A selected reference potential is applied to tl (Vl - V2)/2, and the other input terminal 9
The above-mentioned 2.
A signal having a value of IT H#, "'L" is input. Therefore, the input terminal 3 of the IL semiconductor circuit 6 is H","L
In response to the input signal at the # level, the output terminal 5 of the differential amplifier circuit 11 outputs an output signal at the #)"H#, *I, # state. Here, the differential amplifier circuit 11 outputs an output signal at the # level input signal. With respect to the power supply voltage, the resistance Rs.

定電流源C8の値を任意に設定することによって、任意
の利得が得られ所望の出力振幅に増幅された出力信号を
得ることができる。さらにIL 半導体回路6の共通イ
ンジェクタ端子2、共通エミッタ端子7にそれぞれ接続
された抵抗R3とR4の仙を任意に設定することによっ
て、共通エミッタ端子7の電位、すなわち、工り半導体
回路6と差動増幅回路11等、信号処理回路とのインタ
フェースにおける基準電位を任意に選定することができ
る。従ってIL 半導体回路6の出力信号を直接信号処
理回路へ入力することが可能で、従来回路でみられ九I
”L 半導体回路と信号処理回路間のインタフェースに
おける抵抗等を使用したレベルシフト回路を要せず、さ
らに信号処理回路の入力トランジスタも飽和しないため
、高域での周波数特性が大幅に改善される。
By arbitrarily setting the value of the constant current source C8, an arbitrary gain can be obtained and an output signal amplified to a desired output amplitude can be obtained. Furthermore, by arbitrarily setting the resistances of resistors R3 and R4 connected to the common injector terminal 2 and common emitter terminal 7 of the IL semiconductor circuit 6, the potential of the common emitter terminal 7, that is, the difference from the fabricated semiconductor circuit 6. The reference potential at the interface with the signal processing circuit, such as the dynamic amplifier circuit 11, can be arbitrarily selected. Therefore, it is possible to directly input the output signal of the IL semiconductor circuit 6 to the signal processing circuit, and
"L" There is no need for a level shift circuit using a resistor or the like at the interface between the semiconductor circuit and the signal processing circuit, and furthermore, the input transistor of the signal processing circuit is not saturated, so the frequency characteristics in the high range are greatly improved.

以上、述べたごとく本発明によれは、高周波信号処理に
適した、しかも信号出力振幅、信号出力基準レベルを任
意に設定できるIL 回路を提供することができる。
As described above, according to the present invention, it is possible to provide an IL circuit that is suitable for high-frequency signal processing and in which the signal output amplitude and signal output reference level can be arbitrarily set.

々お、本発明は上記実施例に限定されること表く、特に
第2図に示した回路構成は本発明の範囲内において適宜
変更され得るものである。
However, the present invention is limited to the above-described embodiment, and the circuit configuration shown in FIG. 2 in particular may be modified as appropriate within the scope of the present invention.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はインタフェース回路を備えたIL 回路の従来
例を!l?明する回路図であり、第2図は、本発明によ
るインタフェース回路を備えたIL回路の一実施例を欽
明する回路図である。 1・・・・・・電源雪圧端子、2・・・・・・共通イン
ジェクタ端子、3・・・・・・入力端子、4,7・・・
・・・共通エミッタ端子、5・・・・・・出力端子、6
・・・・・・IL 半導体回路、8・・・・・・接地端
子、9.10・・・・・・差動回路入力端子、11・・
・・・・差動増幅回路、Ql 、Q* +Qs lQ4
1Q61Qs+Qt、Ql1lQ91QIO・・・・・
・トランジスタ、R1゜Rz 、R8、R14、R5、
R6、ELr−・−・・抵抗、c s 、、、 、、、
定電流源。
Figure 1 shows a conventional example of an IL circuit equipped with an interface circuit! l? FIG. 2 is a circuit diagram illustrating an embodiment of an IL circuit including an interface circuit according to the present invention. 1...Power snow pressure terminal, 2...Common injector terminal, 3...Input terminal, 4,7...
...Common emitter terminal, 5...Output terminal, 6
・・・・・・IL Semiconductor circuit, 8... Ground terminal, 9.10... Differential circuit input terminal, 11...
...Differential amplifier circuit, Ql, Q* +Qs lQ4
1Q61Qs+Qt, Ql1lQ91QIO...
・Transistor, R1゜Rz, R8, R14, R5,
R6, ELr----Resistance, cs, ,, ,,,,
Constant current source.

Claims (1)

【特許請求の範囲】[Claims] 出力トランジスタのベースにインジェクタトランジスタ
から電流が供給され、入力信号が前記出力トランジスタ
のペースに加えられ、出力信号がIII 配出カド2ン
ジスクのコレクタから取り出され、該出力トランジスタ
のコレクタに他のインジェクタトランジスタから一流が
供給されるIL 半導体回路と、一方の入力端子が前記
出力出力トランジスタのコレクタに接続され、他方の入
力端子にバイアス市、圧が印加された差動増幅回路とを
具備し、前記差動坪・幅回路の出力端子より出力を増り
出すことを特徴とするIL 回路。
A current is supplied from the injector transistor to the base of the output transistor, an input signal is applied to the base of the output transistor, an output signal is taken from the collector of the output transistor, and the output transistor is connected to the collector of the output transistor by another injector transistor. and a differential amplifier circuit having one input terminal connected to the collector of the output transistor and having a bias voltage applied to the other input terminal, An IL circuit characterized by increasing the output from the output terminal of the dynamic tsubo/width circuit.
JP3800884A 1984-02-29 1984-02-29 I2l circuit Pending JPS60182817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3800884A JPS60182817A (en) 1984-02-29 1984-02-29 I2l circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3800884A JPS60182817A (en) 1984-02-29 1984-02-29 I2l circuit

Publications (1)

Publication Number Publication Date
JPS60182817A true JPS60182817A (en) 1985-09-18

Family

ID=12513543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3800884A Pending JPS60182817A (en) 1984-02-29 1984-02-29 I2l circuit

Country Status (1)

Country Link
JP (1) JPS60182817A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04256216A (en) * 1991-02-08 1992-09-10 Nec Ic Microcomput Syst Ltd Semiconductor circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04256216A (en) * 1991-02-08 1992-09-10 Nec Ic Microcomput Syst Ltd Semiconductor circuit

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