JPS6216275A - Direct current reproducing circuit for digital signal reproducing device - Google Patents

Abstract

PURPOSE:To suppress drifting by holding the direct current level of an LPF output during the dropping-out period to the level before the dropping-out occurs, and clearing the internal data of the LPE when the dropping-out period is longer than the prescribed value. CONSTITUTION:Digital data (a) having the multi-value level reproduced from the recording media are added to an LPF 57 output (f) by an adder circuit 1, inputted to a PLL 4 and a clock (d) is generated. An identifying circuit 3 converts the adding output into an output (c) of the binary data,and the dropping-out in a signal (c) is detected by a dropping-out detecting circuit 7 and inputted into an AND gate 6. While the circuit 7 detects the dropping-out, the gate 6 prohibits the input to an LPF 5 of a clock d', and holds the direct current component level of an output (f) to the level before the occurrence of the dropping-out. A dropping-out control circuit 8, when the dropping-out period is the prescribed time or above, outputs a clearing signal (h) and clears the internal data of the LPF 5. Thus, the drifting of the direct current level can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital signal reproducing device, and particularly to a DC component reproducing circuit thereof.

[Technical background of the invention]

First, the following two documents will be cited as references for understanding the technical background of this invention.

(1) IEICE Technical Report V published on January 1985
OL, 84 No., 279 EA84-70 "Digital DC playback method for fixed head PCM recorder" (27 Proceedings of AES Tokyo Conference '85 published by AE8 Japan branch in June 1985! 456
Pages 159 to 159 "5-About DAT signal processing" Now, when recording and reproducing digital signals on magnetic tapes or disks, in order to achieve particularly high-density recording, the input data sequence must be converted into a new code sequence. So-called modulation is applied. Various modulation methods have been considered, but the minimum magnetization reversal interval is 1.5T (assuming the data rate is 1/T).
A modulation method having this is considered to be a promising method suitable for high-density recording because it allows narrowing of the band. However, in this modulation method, since the modulation signal has a low-frequency component, there is a problem that the eye aperture ratio deteriorates if this low-frequency component is lost in the recording/reproducing system. Therefore, a DC reproduction method has been adopted that improves the eye aperture ratio by extracting and compensating for the missing low-frequency components from the reproduced signal.

DC regeneration systems are broadly classified into feed-forward type and feed-pack type, and the former has a stable system but requires large hardware. For this reason, the latter method, which can be realized with a relatively simple circuit, is being studied.

However, it has the disadvantage that it leaves an element of instability in the system during dropouts, which account for a major portion of the error rate in magnetic recording and reproducing systems. That is, FIG. 3 shows a conventional example of a quantized ar feedback DC regeneration circuit, which is a type of feedback type DC regeneration circuit. An input signal (for example, 8-bit amplitude information in the amplitude direction) having a multilevel level (for example, 8-bit amplitude information in the amplitude direction) from a magnetic recording medium
In a), the low-frequency component is lost and contains a DC-like fluctuation component. ○The low-frequency component estimated by the low-pass filter (5) (
0 is added to the input signal (→) by the adder circuit (1), and as a result, a low frequency compensated multi-level reproduction signal (b) is obtained.The multi-level reproduction signal (b) is added to the PLL circuit. (4
). This PLL circuit (4) performs timing extraction on the multi-level reproduction signal (b) to generate a clock (ψ) with the optimum phase for eye putter ejection. 3), this reproduced signal (b) is compared with a predetermined slice level (for example, zero level), and based on the magnitude relationship, the reproduced signal (h) is converted into a binary signal by the clock (ψ) from the PLL circuit (4). Data output (
C). That is, when the amplitude of the input signal (a) having 8-bit amplitude information is larger than the slice level, it is converted into binary data such as "1", and when it is smaller, it is rOJ. Furthermore, the reproduction signal (b) is level detected %
(2) is input. This level detection circuit (2) outputs the digital level value of the reproduced signal (b) as two's complement data at a slow timing. In order to convert the output of the level detection circuit (2) into two's complement data, the data output (C) of the discrimination circuit (3) is used. Various well-known level detection circuits have been considered for this level detection circuit; for example, the above-mentioned "ABS Tokyo Conference '85
The level detector shown in FIG. The output (e) of the level detection circuit (2) is input to a low-pass filter f5) which is a digital filter. The output signal (f) of the low-pass filter (5) is added to the input signal (a) in the adder circuit (1). This feedback loop is for maintaining the stability of the system and maintains a constant relationship between the input signal (a) and the feedback amount f.

Here, if a dropout occurs in the input signal (→), the DC error will accumulate during the dropout period due to the offset that essentially exists in the input signal (a) or the drift based on the calculation error of the DC regeneration circuit. Due to the addition, the low-frequency component element gradually becomes a large DC level instead of the original low-frequency component.When the dropout ends and the normal input level returns, the reproduced signal (b) has a large DC level. Since the levels are added, data errors will occur continuously during the period determined by the loop time constant until the original low frequency component (f) returns to normal operation and the system enters normal operation. A DC regeneration circuit as shown in Fig. 4 has been considered.In other words, the occurrence of dropout is detected by a dropout detection circuit, and during this dropout period, the clock tM from the PLL circuit is stopped and the low-pass filter is output. This is a DC regeneration method that suppresses data errors by keeping the DC level at the level before dropout occurs.

According to this DC regeneration method, the DC level at the time when dropout occurs is estimated as the current DC level at the end of dropout, so that the loop can be brought into normal operation quickly.

[Problems with background technology]

However, it takes a certain amount of time to detect dropout. During this dropout detection period, the low frequency component (0 is the output of the low pass filter (5) is held, so the error is integrated and a DC component larger than the original low frequency component appears, and even at the end of the dropout, the reproduced signal (b) is loaded with this DC level, and data errors occur continuously until this DC level returns to normal.Therefore, this DC regeneration method cannot completely suppress the effect of dropout, and if the dropout is long, The DC level that is being held becomes meaningless.

[Purpose of the invention]

This invention has been made in consideration of the above circumstances, and is designed to minimize data errors at the time of dropout. [Summary of the Invention] This invention detects the occurrence of dropout using a dropout detection circuit, Disables the clock supplied to the filter, keeps the DC level of the low-pass filter output at the level before the dropout occurs, and clears the internal data of this low-pass filter if the dropout period in parentheses is longer than a certain value ( For example, it is set to zero.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. The DC regeneration circuit shown in FIG. 1 shows one embodiment of the present invention, and the same parts as in the conventional example are given the same numbers and detailed explanation thereof will be omitted. A dropout in the output signal (C) of the identification circuit 3 is detected by a dropout detection circuit (7), and its detection output is input to an AND gate (6). This dropout detection circuit outputs 101 if there is a code string in the data output (C) from the identification circuit (3) that exceeds the maximum magnetization reversal interval of a long code string other than a predetermined modulation pattern. This dropout detection circuit (7) detects dropout and
While outputting M, the input of clock (d) 1 to the low-pass filter (5) is prohibited, and the low-frequency component output (Qt-)' of the low-pass filter (5) is held for the dropout period. During this time, the dropout control circuit (8) measures the length of the dropout period. This dropout control circuit (8) outputs a clear signal (h) when the dropout period is longer than a predetermined value, and clears the internal data of the low-pass filter (5). At this time, the low-frequency component output (f), which is the output of the low-pass filter (5), becomes zero. In other words, if the dropout is short, the DC level at the start of the dropout is estimated as the current DC level at the end of the dropout, and if the dropout is long, the low-pass filter (
5) By clearing the internal data, the drift of the DC level is suppressed and the loop instantly enters normal operation.Another embodiment of the present invention is shown in FIG. In this embodiment, dropout detection is performed from the input signal (a). The dropout detection method in this case is to compare the input signal (a) with a certain value and determine dropout based on its magnitude.

〔Effect of the invention〕

It is possible to create the optimal DC according to the length of the dropout, and to clear the internal data of the low-pass filter when the dropout is particularly long.To suppress the drift of the DC level sufficiently to bring the loop into normal operation. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of the DC regeneration circuit of the digital signal regeneration device of the present invention, and FIG. 2 shows another embodiment of the DC regeneration circuit of the digital signal regeneration device of the present invention. FIG. 3 and FIG. 4 are circuit block diagrams of conventional DC regeneration circuits. 1...Addition circuit, 2...Level detection circuit, 3.
...Identification circuit, 4...PLL circuit, 5...Low pass filter, 7...Dropout detection circuit. 8...Dropout control circuit. Agent Patent Attorney Nori Ken Yudo Hiroshi Uji Figure 1 Pook Output No. 3m

Claims (1)

[Claims] A digital adder circuit to which digital data having multilevel levels reproduced from a recording medium is applied to one input terminal, a PLL circuit to extract timing from the output of this digital adder circuit and generate a clock signal, and this clock. an identification circuit that converts the output of the adder circuit into a binary code signal based on a signal; a level detection circuit that uses the output of the identification circuit to generate an output proportional to the output of the adder circuit; and the level detection circuit. a digital low-pass filter that extracts a low-frequency component from the output of the adder and applies it to the other input terminal of the adder circuit, a dropout detection circuit that detects dropouts in the reproduced digital data, and a dropout detection circuit that detects dropouts. means for maintaining the DC level of the output of the low-pass filter at the level before the dropout occurs when the length of the dropout period detected by the dropout detection circuit is less than or equal to a predetermined time; and the length of the dropout period detected by the dropout detection circuit. A dropout control circuit for clearing the internal data of the low-pass filter when the time is longer than a predetermined time.