JPS62162357A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To enable the easy automatic adjustment of sensitivity by changing a voltage to be applied to a transparent electrode with time in the structure in which an amorphous semiconductor layer is arranged on a signal read-out part made of an Si single crystal substrate. CONSTITUTION:On a P-type semiconductor substrate 1, an N<+> layer 2 as a signal charge transfer part of a CCD and an N<+> layer 5 connected with an amorphous semiconductor layer 3 through a metallic electrode 4 are formed. P<+> layers 6-1 and 6-2 are arranged adjacently to the layers 2 and 5. On the layer 3, a transparent electrode 7 is formed. THe signal charges photoelectrically converted in the layer 3 are transferred to the layer 2 and are read out by applying a voltage to a read-out gate electrode 8 adjacent to the layer 5. Also, the electrode 8 and a transfer electrode are surrounded with insulating films 10-1 and 10-2. In this constitution, a voltage to be applied to the electrode 7 is changed with time. Namely, a low-voltage duration after retaining a voltage at a predetermined voltage is changed according to the incident light quantity so as to perform the automatic adjustment of sensitivity.

Description

[Detailed description of the invention] The present invention relates to a solid-state imaging device.

Photoelectric conversion in solid-state imaging devices is performed using conventional silicon (Si).
) It is known that the method is not performed using a single crystal substrate, but is performed using a photoconductive layer made of, for example, an amorphous semiconductor layer. This uses a conventional Si single-crystal substrate for the signal readout section, but since the amorphous semiconductor layer is provided on the signal readout section made of this Si single-crystal substrate, it is called a two-mirror sensor and is different from the conventional one. It is distinguished from a solid-state imaging device using only a Si single crystal substrate.

An object of the present invention is to provide a solid-state imaging device called a two-mirror sensor in which automatic sensitivity adjustment can be performed.

FIG. 1 shows the basic configuration of the present invention. Here, a CCD (Charge Coupled Device) is used in the readout section.
An explanation will be given using a device using e). For example, Figure 1 (
As shown in a), a second N+M0 is formed on the P-type semiconductor substrate ω, which is connected to the first N+ layer ■, which is the signal charge transfer part of the COD, and the amorphous semiconductor layer ■ via a metal electrode. Ru. Adjacent to the first N middle layer 2 and the second N middle layer 0, there is a P+ layer (6-1,
6-2) is provided. Further, a transparent electrode (2) is formed on the amorphous semiconductor layer (2). The signal charges (electrons) photoelectrically converted in the amorphous semiconductor layer
By applying a voltage to the readout gate electrode (8) adjacent to the N middle layer (2), the data is transferred to the first N middle layer (2) and read out. Here, a COD transfer electrode (2) is formed on the first N intermediate layer (2), and an insulating film (10-1, 1O
-2) exists. Let Va be the voltage applied to the transparent electrode 1, and let VN be the surface potential of the second N+ layer. The amorphous semiconductor layer (2) sandwiched between the metal electrode (0) and the transparent electrode (2) can be described isometrically as one diode. Then, as shown in FIG. 1(b), VO is applied to both ends of this amorphous semiconductor layer
This means that VN is applied.

In FIG. 1(a), VN immediately after a voltage is applied to the read gate electrode (c) to read signal charges is VNO. Here, as shown in FIG. 1(c), the voltage Va applied to the transparent electrode (2) is changed over time. That is, in an imaging operation that constitutes one cycle from No. 18 readout period for reading signal charges and an accumulation period for accumulating signal charges, VG is set to VN during any period that is continuous to the signal readout period.
During the remaining period, a voltage lower than that of the VNO is applied.6 Then, automatic sensitivity adjustment is performed by changing this low voltage period TI according to the amount of incident light.

Here, v is a charge that does not cause the signal charge accumulated in the diode capacitance by the amorphous semiconductor layer 1 and the second N intermediate layer in FIG. 1(a] to overflow to the first N+ layer of the CCD. By adopting such a method, no voltage is applied to the diode formed by the amorphous semiconductor layer 2 during the VNO holding period within the \I product period, so no signal charge is accumulated.
Signal charges are accumulated only during the low voltage VT holding period. Also, V during the signal charge readout period. By making VNQ a negative voltage, it is ensured that the diode formed by the amorphous semiconductor layer (3) is in a reverse bias state, and the signal charge is transferred to the CCD without fail. . Here, if the voltage applied to the transparent electrode (■) is set to a lower level voltage than VNO, even though the amount of signal charge that can be accumulated during this low-level voltage period is small, in reality, signal charges can be accumulated, so some cause problems. That is, when a solid-state imaging device using this method is used as a black-and-white camera, there is almost no practical problem, but when it is used, for example, in a color camera, a problem arises in color reproducibility at the location of the subject where the amount of signal is small. This is not a fatal drawback as it does not mean that the signal itself cannot be obtained, but the biggest problem is that when the voltage applied from the VNO to the transparent electrode ■ is set to a high level voltage, the The problem is that signals in dark areas may not be obtained as output.

The operation of the solid-state imaging device shown in FIG. 1(a) will be explained using FIG. 2. Figure 2 (b), (c), (d),
(e) is a diagram for explaining the uIJ-like change in the signal ni load due to the driving constant pressure waveform when a voltage higher than VNO is applied to the transparent electrode (2) in the cell structure of FIG. 2(a). FIG. 3 is a potential distribution diagram on the surface of a semiconductor substrate.

(b) shows the potential distribution when a higher level voltage than VNO is applied to the transparent electrode (2) after the signal charge readout period. Here, the dotted line indicates the potential of the second N+M9 section after the signal charge readout operation, and its value is V
No. Here, as mentioned above, V is applied to the transparent W1 pole ■.
By applying a higher level voltage than NO, the second
Charges (electrons) in the N+ layer 1 of the second N+ layer 2 flow out to the transparent electrode 2, and the surface potential of the second N+ layer 2 is set to a higher level than the VNO.

During this high-level voltage holding period, the signal charges (electrons) generated in the amorphous semiconductor layer
Signal charges are accumulated when a voltage Vz for accumulating signal charges is applied to the primary transparent electrode (2) which flows out to the It pole (2) and no signal charges are accumulated.

During this VX holding period, as shown in FIG. Lowers the potential of the middle layer ■. Then, in order to read out the signal charge, a voltage is applied to the readout gate electrode (8) to transfer the signal charge to the first N middle layer (2) of the CCD. The potential distribution is shown in the same figure (d). Shown below. Here, the surface potential of the semiconductor substrate under the readout gate electrode (8) is V
Therefore, the signal charge (11) having a potential lower than the potential VNO determined by the voltage applied to the readout gate electrode (8) is transferred to the first N middle layer (2) of the CCD as shown in Fig. 2 ( Transferred as shown in e).

As described above, the present invention allows automatic sensitivity adjustment to be easily performed by temporally changing the voltage applied to the transparent electrode.

FIG. 3 is a diagram for explaining in detail the ψ-th invention, which is a further improvement on the one explained in FIG.

During the VNO holding period of the accumulation period in FIG. 1(c), no voltage is applied to the amorphous semiconductor layer 0, so the signal charges generated in the amorphous semiconductor layer 0 diffuse within the amorphous semiconductor layer (3). and is removed from the transparent electrode (■). In this case, the signal charge is moved by diffusion, for example by an electric field during the vr retention period of the storage period.The amorphous semiconductor layer (2) usually has many trap levels with different time constants within the layer. are doing. Since these signal charges captured by the trap level are released from the trap level with a certain time constant, those with a long time constant become an afterimage. Charges emitted with a longer time constant and reaching the metal electrode (a) cause a burn-in phenomenon that remains as an output on the reproduced image for a long time. Especially when the low voltage period TT becomes short, that is, VNO
As the retention period becomes longer, afterimages and burn-in phenomena increase, resulting in deterioration of image quality.

In view of this, as shown in FIG. 3, the voltage applied to the transparent electrode (2) is held at a voltage lower than the VNO, for example VI, for an arbitrary period following the signal readout period, and then held at the VNO.

Then, as in FIG. 1, automatic sensitivity adjustment is performed by holding VX and changing the VX holding period T in accordance with the amount of incident light.

That is, according to the present method, the first
During the V process holding period, an electric field is generated in the amorphous semiconductor layer (2), unlike the method shown in FIG.

The signal charge generated in the amorphous semiconductor WJ2 during this period by this electric field quickly travels through the amorphous semiconductor layer 0, reaches the metal electrode (a), and is accumulated.

Next, during the VNO holding period, the signal charges accumulated on the metal electrode (A) are removed from the metal type 1fi (A) through the amorphous semiconductor layer (2) and the transparent electrode (2). Then, it becomes an output signal during the second vr holding period T. Signal charges are generated in the amorphous semiconductor layer (2), travel to the metal electrode (A), and are accumulated. Here, the signal charge generated during the first V and retention period is an invalid charge with respect to the output signal, and the electric field shortens the residence period of this invalid charge in the amorphous semiconductor layer 0, which causes afterimage and burnout. The number of charges trapped at the trap level in the amorphous semiconductor layer (2), which causes the sticking phenomenon, also decreases.

Here, the voltage applied to the transparent electrode (2) following the readout period is at a lower level than VNO even if it is not VI, and is a voltage at which the accumulated signal charge does not leak into the first N intermediate layer (2) of the COD. That's fine.

Although the amorphous semiconductor layer in the above embodiment is described as a single layer, a plurality of amorphous semiconductor layers or a plurality of various photosensitive layers may be formed.

Further, although the present invention has been described using a CCD as a signal charge readout unit, for example, BBD (BucketBr
igade device). That is, the present invention is applicable to a "second-order mirror sensor" in which one cycle is constructed by signal accumulation and readout, and is not applicable to COD.

It goes without saying that the present invention can be applied to both one-dimensional and secondary sensors. Furthermore, as an example, we have explained an example in which the amorphous semiconductor layer (3) is sandwiched between a transparent electrode (1) and a metal electrode), which utilizes the characteristics in the thickness direction of the amorphous semiconductor layer (2). It goes without saying that the present invention is also applicable to those that utilize the Further, although a single transparent electrode (3) has been described, it is also possible to control the transparent electrode (2) by using a plurality of them. Then, on the actual flow side, the VX retention period for signal charge accumulation is determined by the transparent electrode ■
The voltage applied to VX may be changed over time to reach VX.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining the basic configuration of the present invention, and FIG. 3 is a diagram for explaining the present invention in detail. 1: P-type semiconductor substrate, 2: first N intermediate layer, 3: amorphous semiconductor layer, 4: metal electrode. 5: Second N middle layer, 6-1.6-2:
P middle layer, 7: transparent electrode, 8: readout gate electrode, 92 COD transfer electrode, 10-1.10-
2: Insulating film. Agent Patent Attorney Noriyuki Chika Yudo Kikuo Takehana vN”- Figure 1

Claims (1)

[Claims] a P-type silicon substrate, a pair of N-type layers provided on this substrate, a gate electrode provided between the N-type layers with an insulating film interposed therebetween; A transfer electrode provided on one of the N-type layers via an insulating film, and a P^+ type provided adjacent to the N-type layer in the P-type silicon substrate other than directly under the gate electrode. a photoelectric conversion layer made of amorphous silicon that is in direct or electrical contact with the other N-type layer of the N-type layer and provided on the gate electrode and the transfer electrode with an insulating film interposed therebetween; A solid-state imaging device comprising: an electrode layer provided between the N-type layers; and a transparent electrode that transmits light and provided on the photoelectric conversion layer.