JPS62162299A - Method for writing and reading semiconductor non-volatile memory data - Google Patents

Abstract

PURPOSE:To provide a highly reliable writing and reading method by using a check bit as an electrostatic charge injection type and invertionally writing the contents of the program data bits when the bits for injecting charge to a gate exceeds a half of the contents of the program data bits, and when the bits less than a half, reversely processing. CONSTITUTION:The number of '0' bits in the program data obtained from an 8-bit microprocessor or the like is counted up. When the number of '0' bits exceeds a half of the number of program data bits, the data obtained by inverting the ordinary program data are written in an EPROM together with a check bit '0'. Next, the written-in data processed as above are written-in to the EPROM. The programs data are read out from the EPROM, and when the check bit is '0', the contents of the read program data are inverted so as to be used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for writing and reading EPROMs and EEPROMs, and particularly relates to methods for writing and reading EPROMs and EEPROMs.
EPROM, EEPROM which provides the use of EPROM
This relates to methods of writing and reading.

[Conventional technology]

Conventionally, many EPROMs have a one-word 8-bit configuration, and original program data can be written and read as is. For this reason, a single bit error could lead to a system failure, and it was necessary to make the device itself more reliable or to pass it through expensive screening. Therefore, EPROMs having a one-word, nine-bit configuration to which a parity check bit is added have recently come into use.

Next, writing and reading to and from the EPROM having the above-mentioned I word 9-bit configuration will be explained using the flowchart shown in FIG. First, programs and data for a microcomputer, etc. are created separately. It is assumed that the program data is composed of 8 bits as shown in step 1. Next, as shown in step 2, check the contents of the program data, focus on the "1" bits, and if there is an even number of "1" bits in the program data, the parity bit is set to "0". Added word (
9-bit configuration). Conversely, if the number of "1" bits in the program data is odd, a word is obtained by adding "l" as a parity bit. Table 1 shows specific examples.

Next, as shown in step 3, the parity
The bit-added data is converted to EP using the usual method.
Write to ROM/EEPROM.

Next, when reading in step 4, once the EF
A parity check is performed on the 9-bit data read from the ROM. That is, as shown in step 5, the number of "1" bits existing in a word is counted to determine whether it is an even number or an odd number. As a result of the determination, if the number of "1" bits is an even number, the 8 bits of program data are treated as having no errors, as shown in step 6, and if the bin R of rlJ is an odd number, as shown in step 7, the 8 bits of program data are treated as having no errors. It is sufficient to handle the occurrence of an abnormality by assuming that this has occurred.

[Problem that the invention seeks to solve]

Conventional EPROM/EEPROM writing.

Since the reading method was configured as described above, there was a problem in that if a one-bit error occurred in the memory itself, the reliability of the system would be impaired.

The present invention has been made in view of these points, and its purpose is to provide a writing and reading method that can achieve high reliability against 1-bit errors.

[Means for solving problems]

In order to achieve such an object, the present invention provides at least one data bit of data bits constituting a word.
The bit is set as a check bit, the remaining data bits are set as program data, and if more than half of the pins inject charge into the gate depending on the contents of the program data bits, the check bit is set as a charge injection type and the program is programmed.・If the contents of the data bits are inverted and written, and if less than half of the bits inject charge into the gate due to the contents of the program data bits, the check bits are set to non-charge injection type and the program
Writes the contents of the data bit without inverting it, inverts and outputs the program data read from memory if the check bit when reading is a charge injection type, and outputs the program data read from the memory after inverting the check bit when reading, and if the check bit when reading is a non-charge injection type, the memory The program data read from the controller is output in a non-inverted manner.

[Effect]

In the present invention, when writing and reading program data for a microprocessor or the like into an EPROM, check bits are added to reduce the number of write bits in the EPROM.

〔Example〕

First, the configuration, operation, etc. of the EPROM will be explained. Originally, the memory cell of EPROM was a FAM as shown in Figure 2.
O3 structure, FIG. 2(a) shows the erased state, and the second
Figure (bl indicates the writing state. In Figure 2, 11
are a single crystal semiconductor substrate, 12 and 13 are source and drain diffusion layers of opposite isoelectric type to the substrate, 14 is a floating gate into which electrons are injected, and 15 is a writing layer;
A control gate for controlling readout, 16 an oxide film between the substrate and the floating gate, and 17 an oxide film on the floating gate.

In this structure, the writing state shown in FIG.
It takes a different energy state from the erased state shown in Figure (al).The erased state is considered to be in energy equilibrium, and writing is performed by floating electrons by avalanche breakdown compared to the erased state, which is the equilibrium state. Since the floating gate is injected into the gate, in the write state, surplus electrons on the floating gate tend to return to the substrate or the control gate.

In addition, our experimental results show that in floating gate programmable memory, the memory retention characteristics after proper control of manufacturing conditions and appropriate screening are determined by the degree of retention of the charge injected into the floating gate. Therefore, when operating an EPROM, it is more stable to operate it in a state with a higher percentage of erased states, that is, higher reliability can be obtained.

The present invention has been made with attention to this point.

An embodiment of the method for writing and reading data in a semiconductor non-volatile memory according to the present invention will be described below with reference to FIGS. 1 and 3.
Explain using. In Figure 1, first, step 2
For program data such as an 8-bit microprocessor as shown in step 1, as shown in step 22,
Count the number of "0" bits in the program data. Here, as shown in step 23, if the number of "0" bits exceeds half of the number of program data bits, a check bit is added as "0" and the original program data is inverted and transferred to the EPROM. write data.

If the number of "0" bits in the program data' is less than half, as shown in step 24, a check bit is added as "1" and the program data is non-inverted and transferred to the EPROM. write data. Table 2 shows the relationship between the original program data (upper row), the write data in the present invention (lower row), and the check bits.

Next, as shown in step 25, the write data subjected to the above processing is written into the EPROM in the usual manner.

Next, as shown in step 26, program data is read from the EPROM. First, in step 27, the read data is checked to see if the check bit is "0" or "
1). Here, the check bit is “
0'', as shown in step 28, the contents of the read program data are inverted and used. Choi 7
If the ri bit is rlJ, the program data is used as non-inverted, as shown in step 29.

In the above explanation, the state in which electrons are injected into the floating gate is referred to as rOJ (also referred to as r write state).
The state in which electrons are not injected into the floating gate by irradiation with ultraviolet rays was explained as rlJ (also referred to as r-erased state). This status setting is a conventional general status setting.

When configured as above, an 8-bit program
When considering data, assuming that program data is written randomly, there are 28=256 possible data numbers for one word. FIG. 3 shows the relationship between the write bit R in one data and the frequency of data that can be obtained by the number of write bits. From this, parity
If you use the conventional writing method with a 9-bit configuration that adds bits, random program data can be written in 256 bits.
When writing a word, the average number of bits written is IX1+I
X8+3X28+3X56+5X70+5X56+7X
28+7X8+9X1=1152 (bits).

On the other hand, the average number of written bits in this embodiment is OX1+IX8+2X28+3X56+4X70+4X
56+3X28+2X8+lX1=837 (bits).

Therefore, the number of write bits is clearly reduced by the write method in this embodiment.

According to our experimental results, the memory retention characteristics of EPROMs with strict control of manufacturing conditions and appropriate screening are determined by the mode in which write-state electrons are volatilized by injecting electrons into the floating gate. Therefore, using the side with a large number of erased bits contributes to improving reliability. Furthermore, when storing programs and data for a microcomputer, etc. in an EPROM, it is rare that the entire storage area is used up.
Actually, after the address where the program data ends, 8
Processing is performed with both the focus set to "1" or rOJ data as a dummy. Conventionally, in such cases, both 8 bits are
In most cases, "0" data is input, and if writing and reading are performed as in this embodiment, the actual number of written bits can be significantly reduced and high reliability can be obtained.

In addition, in the above embodiment, an EPROM was explained as an example, but
A similar effect can be achieved with EEPROM.

Further, although an example in which the bit length of the program data is 8 bits has been described, the same effect can be achieved even if the bit length is smaller or larger. In particular, 16-bit microprocessors have become mainstream, and it is only a matter of time before they shift to 32-bit, and the longer the bit length of program data, the greater the effect.

Further, although the example of the check bit being 1 bit has been shown, there is no problem if the check bit is more than 1 bit.

In general, the above embodiment has been explained using program data of a microprocessor, etc., but it may also be font data for kanji generation, digital data for speech synthesis, etc.
Needless to say, any data that is digitized information that requires repeated reading is sufficient.

〔Effect of the invention〕

As explained above, in the present invention, if more than half of the bits inject charge into the gate due to the contents of the program data bits, the check bits are set to charge injection type and the contents of the program data bits are inverted. If less than half of the bits inject charge into the gate due to the contents of the program data bits, set the check bits to non-charge injection type and write without inverting the contents of the program data bits. As a result, the number of charge injection type memory bits can be reduced and the possibility of data volatilization can be reduced, which has the effect of making it possible to obtain a highly reliable memory successive read/write system.

[Brief explanation of drawings]

FIG. 1 is a flowchart for explaining an embodiment of a semiconductor nonvolatile memory data writing/reading method according to the present invention, FIG. 2 is a cross-sectional view showing the structure of a general EFROM, and FIG. 3 is a writing FIG. 4, which is a graph showing the relationship between the number of bits and the frequency of data that can be obtained by the number of written bits, is a flowchart for explaining a conventional method for writing and reading data in a semiconductor nonvolatile memory.

Claims (1)

[Claims] In a method for writing and reading data in a nonvolatile memory formed on a single crystal semiconductor substrate, at least one of the data bits constituting a word is used as a check bit, and the remaining data bits are programmed.・If more than half of the bits inject charge into the gate due to the contents of the program data bit, the check bit is set to the charge injection type, and the contents of the program data bit are inverted and written. If less than half of the bits inject charge into the gate due to the contents of the program data bits, the check bits are set to non-charge injection type, and the contents of the program data bits are written and read without inverting them. If the check bit at the time is a charge injection type, the program data read from the memory is inverted and output; if the check bit at the time of read is a non-charge injection type, the program data read from the memory is output non-inverted. A method for writing and reading data in a semiconductor nonvolatile memory, characterized by: