JPH0636578A - Eeprom - Google Patents

Abstract

PURPOSE:To shorten a write time by providing plural serial registers for writing data in a memory array. CONSTITUTION:After data is inputted to a serial input/output register 2, the data is inputted to the serial input/output register 4 while data write is performed from the register 2 to the memory array 6, and thereafter, while the data is read out from the array 6 to the register 2 for verify, the data is written in the array 6 from the register 4. Then, the write time in the array 6 is shortened, and the write and the read of the data are performed simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a serial input / output type EE.
PROM (Electrically E-rasab)
le and Programmable Read
Only Memory).

[0002]

2. Description of the Related Art A conventional serial input / output type EEPROM chip, that is, a NAND type chip, is a serial register (i.e., shift register) for both input and output for writing and reading data to and from a memory array.
For example, the length of the serial register is 512 bytes, the number of rows of the memory array is 1024, and the chip capacity is 4 Mbits (512 kB). In the case of such a chip, it takes time of the order of 100 nS to serially input 1-byte data, and it takes about 50 μS to input 512-byte data to the serial register.
I need.

Further, the writing time of the EEPROM is N
The OR type is generally on the order of 10 μS, and the NAND type conventional example described above requires about 40 μS. Reading for verification following writing is about 6 μS in the NOR type, but 10 μS is required in the above-mentioned NAND type conventional example. Therefore, in the conventional serial input / output type EEPROM, it takes about 50 μ to write and verify data.

[0004]

FIG. 7 shows a time sequence of the operation of the conventional serial input / output type EEPR0M. As described above, since only one serial register is provided, data writing and verifying operations are not performed in the EEPROM while the host is inputting data to the serial register. Therefore, FIG.
As shown in, the host side has to wait for writing and verifying reading for about the same time after inputting data to the serial register for about 50 μS and then writing to the memory array. It takes a long time to write.

If an error is found after reading data for verifying write, data must be input again to the serial register, and data input, write to array and verify are performed. There is a problem that it takes more time for the write cycle consisting of.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an EEPROM capable of shortening the writing time to the memory array.

[0007]

An EEP according to claim 1
The ROM is characterized by including a plurality of serial registers (for example, serial registers 2 and 4 in the embodiment of FIG. 1) for writing data to the memory array.

An EEPROM according to a second aspect includes a plurality of serial registers (for example, FIG. 1) for writing and reading data to and from a memory array.
The serial registers 2 and 4) of the embodiment of FIG.

An EEPROM according to a third aspect of the present invention is a write serial register for writing data to a memory array (for example, the serial input register 12 of the embodiment of FIG. 3) and a data read from the memory array. A read serial register (for example, the serial output register 22 of the embodiment) is separately provided.

An EEPROM according to a fourth aspect of the present invention is a first register for holding data to be written in a memory array (for example, the first input / output register 51 of the embodiment of FIG. 5).
And a second register for holding the data read from the memory array (for example, the second register 5 in the embodiment of FIG. 5).
2) and a collective verify circuit (for example, the exclusive OR gates EX1 to EXn and the OR gate 53 in the embodiment of FIG. 5) that detects a write error of any bit from the outputs of the first and second registers. It is characterized by being provided.

An EEPROM according to a fifth aspect is provided with a plurality of serial registers (for example, serial registers 2 and 4 in the embodiment of FIG. 1) for writing data to the memory array, corresponding to each serial register. It is characterized in that the allocation of the write area to the memory array is determined.

[0012]

In the EEPROM having the structure of claim 1, while the data is being written from the first serial register to the memory array after the data is input to the first serial register among the plurality of serial registers. Moreover, it becomes possible to input data to the second serial register among the plurality of serial registers. Therefore, the writing time to the memory array can be shortened.

According to another aspect of the EEPROM of the present invention, while the data is being written from the first serial register to the memory array after the data is input to the first serial register among the plurality of serial registers. Data is input to the second serial register of the plurality of serial registers, and then while the data is being read from the memory array to the first serial register for verification, for example, while the data is being read from the second serial register to the memory array. You can write data to. Therefore,
Write time to the memory array can be shortened and
Data can be written and read at the same time.

In the EEPROM having the structure of the third aspect, the data is input to the write serial register,
After the data is written to the memory array from here, even if the data is read from the memory array to the read serial register for verification and an error is detected, the data is held in the write serial register. Since the data can be rewritten immediately without the need to input the data again to the write serial register, the time required for rewriting when a write error occurs can be shortened.

In the EEPROM having the structure of the fourth aspect, the first register holds the data to be written in the memory array, the second register holds the data read from the memory array, and the collective verify circuit, A write error of any bit is detected from the outputs of the first and second registers. Therefore, since a write error can be found instantly, rewriting can be done immediately.

In the EEPROM having the structure of claim 5, the data input to the plurality of serial registers is
Each is written to the allocated area of the memory array. Therefore, the writing process to the plurality of regions of the memory array can be performed in parallel, and the writing time can be shortened.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the EEPROM of the present invention. In this embodiment, two serial input / output registers 2 and 4 are provided. These serial input / output registers 2 and 4 are for performing both writing and reading of data with respect to a memory array 6 in which a large number of memory cells are arranged in a matrix. The host is the serial input / output register 2
After inputting the data for that length into EEPROM,
Input a write command to the control register of. As a result, data is written from the serial input / output register 2 to the memory array 6.

Allocation of a write area to the memory array 6 corresponding to each serial input / output register 2 and 4 is determined. That is, the data input to the serial input / output register 2 is written to the odd rows of the memory array 6, and the data input to the serial input / output register 4 is written to the even rows of the memory array 6.
Allocation of the write area of the memory array 6 is determined.

FIG. 2 shows a time sequence of an operation example of the embodiment shown in FIG. The operation of the embodiment shown in FIG. 1 will be described below with reference to FIG. After data is input to the serial input / output register 2 (for example, A1), data is being written from the serial input / output register 2 to the memory array 6 (for example, B1) while the serial input / output register 4 is input.
Data (for example, A2), and then while the serial I / O register 2 is reading data from the memory array 6 for verification (for example, C1), the serial I / O register 4 reads the memory array. Data is written in 6. Therefore, the writing time to the memory array 6 can be shortened, and the writing and reading of data can be performed simultaneously.

For example, A: time of data input (input to serial register), B: time of write (programming from serial register to memory cell), C: time of serial output (read) and verify of data are equal. Then, as is apparent from FIG. 2, since the total writing time becomes 2/3, the writing speed becomes 1.5 times.

The writing time B is shorter, for example, 10 μS
In the case of, the length of the serial input / output registers 2 and 4 is set to a length corresponding to the writing time, for example, 64B or 12
If it is 8B or the like, random access becomes easy.

FIG. 3 shows the configuration of another embodiment of the EEPROM of the present invention. In this embodiment, the serial input register 12 for writing data in the memory array 6 is used.
And a serial output register 22 for reading data from the memory array 6 are separately provided. In addition, a serial input register 14 for writing data to the memory array 6 and a serial output register 24 for reading data from the memory array 6 are separately provided.

FIG. 4 shows a time sequence of an operation example of the embodiment shown in FIG. The operation of the embodiment shown in FIG. 3 will be described below with reference to FIG. First, data is input from the host side to the serial input register 12 (for example, A in FIG.
1) Then, a write command is input from the host side to the control register, which causes the serial input register 1
Data is written from 2 to the memory array 6 (for example, B1 in FIG. 4). Next, a read command for verification is set in the control register from the host side,
As a result, the data written in the array 6 is transferred from the memory array 6 to the serial output register 22. Then, the host side reads the data transferred to the serial output register 22, compares it with the data to be written held by the host side, and checks the error (for example, C1 in FIG. 4).

When the host detects an error here,
The write command is again input to the control register, and writing is performed from the serial input register 12 to the memory array 6 (for example, B1 ′ in FIG. 4). In the prior art, when an error is detected, the data to be written to the serial register must be input again as shown in A2 ′ of FIG. 7. However, in the embodiment of FIG.
Even if an error is detected, since the data is held in the serial input register 12, the serial input register 12
Since the data can be rewritten immediately without the need to input data again, the time required for rewriting when a write error occurs can be shortened. The operations of the serial input register 14 and the serial output register 24 are similar.

FIG. 5 shows the configuration of an embodiment of the batch verify circuit of the EEPROM of the present invention. In this embodiment, a first register 51 for holding data to be written in the memory array 6, a second register 52 for holding data read from the memory array 6, and first and second registers 51 and 52, respectively. N exclusive OR gates EX1 to EXn for comparing bit outputs and these n exclusive OR gates
An OR gate 53 that receives the outputs of the R gates EX1 to EXn is provided. The first register 51 is, for example,
It can be configured by the serial input register 12 of FIG.
The register 52 can be composed of, for example, the serial output register 22 shown in FIG. For example, when the length of the first and second registers 51 and 52 is 128B, n is
128 × 8 = 1024, and the number of exclusive OR gates is 1024.

If all the bits of the first and second registers 51 and 52 match, the output of the OR gate 53 is negated (here, the output "0"), indicating that there is no error. If any bit of the first and second registers 51 and 52 does not match, OR
The output of the gate 53 is asserted (here, the output “1”), and the write error can be found instantly. As described above, in the circuit of FIG. 5, all the data held in the register can be collectively verified. EEPROM
In case of, it is not necessary to know in which bit the write error occurred, so that the rewriting can be immediately started.

At present, NOR type flash memory having a circuit having an automatic write function in a chip is available, but the circuit of FIG. 5 is a serial input type (NAND).
(Type) EEPROM is effective in realizing an automatic writing function.

FIG. 6 shows an operation example of an EEPROM having two sets of serial input registers and serial output registers as in the embodiment of FIG. 3 and having a collective verify circuit as shown in FIG. Indicates a time sequence. In this case, the writing speed is doubled.

In the above description, the first register 51 in FIG. 5 is configured by the serial input register 12 in FIG. 3, and the second register 52 in FIG. 5 is configured by the serial output register 22 in FIG. However, the first register 51 may be composed of the serial input / output register 2 of FIG. 1 and the second register 52 may be composed of a verify-only register.

[0030]

According to the EEPROM of the first aspect, since a plurality of serial registers for writing data to the memory array are provided, after inputting data to a certain serial register, writing data to the memory array from here. Since it becomes possible to input data to another serial register while performing, the writing time to the memory array can be shortened.

According to the EEPROM of claim 2, since a plurality of serial registers for writing and reading data to and from the memory array are provided, the writing time to the memory array can be shortened and the writing and writing of data can be performed. Reading can be performed simultaneously.

According to the EEPROM of the third aspect, since the write serial register for writing data to the memory array and the read serial register for reading data from the memory array are separately provided, a write error occurs. It is possible to shorten the time required for rewriting when a problem occurs.

According to the EEPROM of the fourth aspect, the collective verify circuit uses the data to be written in the memory array held in the first register and the data read from the memory array held in the second register. Since the write error of any one of the bits is detected, the write error can be found instantly, and the rewriting can be performed immediately.

According to the EEPROM of the fifth aspect, a plurality of serial registers for writing data to the memory array are provided, and the allocation of the write area to the memory array corresponding to each serial register is determined. Since the writing processing to a plurality of areas can be performed in parallel, the writing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an EEPROM of the present invention.

FIG. 2 is a diagram showing a time sequence of one operation example of the embodiment of FIG.

FIG. 3 is a block diagram showing the configuration of another embodiment of the EEPROM of the present invention.

FIG. 4 is a diagram showing a time sequence of one operation example of the embodiment of FIG.

FIG. 5 is a block diagram showing an embodiment of a batch verify circuit of the EEPROM of the present invention.

6 is a diagram showing a time sequence of an operation example when a serial input register and a serial output register are separately provided as in the embodiment of FIG. 3 and the embodiment of FIG. 5 is used.

FIG. 7 is a diagram showing a time sequence of an operation example of a conventional EEPROM.

[Explanation of symbols]

 2, 4 Serial register 6 Memory array 12, 14 Serial input register 22, 24 Serial output register 51 First register 52 Second register 53 OR gate EX1, EXn Exclusive OR gate

Claims (5)

[Claims] 1. An EEPROM comprising a plurality of serial registers for writing data to a memory array. 2. An EEPROM comprising a plurality of serial registers for writing and reading data to and from a memory array. 3. An EEPROM comprising a write serial register for writing data in a memory array and a read serial register for reading data from the memory array separately. 4. A first register for holding data to be written to a memory array, a second register for holding data read from the memory array, and one of outputs from the first and second registers. An EEPROM having a collective verify circuit for detecting a bit write error. 5. A plurality of serial registers for writing data to a memory array are provided, and a write area is assigned to the memory array corresponding to each serial register.
EPROM.