JPS62161210A - High speed digital filter - Google Patents

Abstract

PURPOSE:To increase the sampling period by dividing the constitution of an IIR type filter whose amplitude characteristic is constant into the 1st part corresponding to the denominator of a transfer function and to the 2nd part corresponding to the numerator and making at least one coefficient zero. CONSTITUTION:The transfer function H(z) of the all pass filter of the 3rd order IIR type (cyclic type) is expressed in equation I, where (z) is an operator and am (0<=m<=M) and bn (0<=n<=N) are filter coefficients. Then the filter is formed by blocks while being spit into feedback loop parts (2-10) relating to the denominator of the transfer function and output stage parts (11-19) relating to the numerator. For example, in selecting the coefficients a0 for multipliers 3, 18 and a1 for multipliers 5, 15 zero, the all pass filter is simplified, modified equivalently and the entire transfer function H(z) is expressed in equation II. Thus, the constitution is simplified and the sampling period is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed digital filter suitable for use in a HUE control circuit, a phase shifter, etc. of a VTR, etc.

Summary of the Invention The present invention is a high-speed digital filter suitable for use in HUE control circuits such as VTRs, face thicks, etc., in which a TIR type all-pass filter (all-band M-pass filter) corresponds to the denominator of a transfer function. and a part corresponding to the numerator, simplify at least one set of coefficients that have the same value as 0, and equivalently perform at most one addition and one multiplication before and after the delay circuit. By transforming the obtained low-order all-pass filters so that they only exist, and connecting the obtained low-order all-pass filters vertically to form an equivalent high-order all-pass filter, it is possible to obtain arbitrary phase characteristics without deteriorating the amplitude characteristics. However, it also enables high-speed operation.

[Conventional technology]

Conventionally, when controlling the HUE (hue) of a composite video signal using digital signal processing, the fifth
A decode/encode type HUE control circuit shown in the figure is used.

In FIG. 5, a digital composite color video signal is supplied to a Y/C separation circuit 81 from an input terminal 80. In the Y/C separation circuit 81, the color video signal is separated into an A1 degree signal Y and a chroma signal (transferred color signal) C, a luminance signal Y is supplied to an adder 93, and a chroma signal C is supplied to a demodulator 82 and 88 respectively.

A carrier signal of sin (ωL) is supplied to the modulator 82 from a terminal 83, and a carrier signal of cos (0° C.) is supplied to the demodulator 88 from a terminal 89.

In the 'tli modulator 82, the chroma signal C is demodulated to form a color difference signal RY. Further, in the demodulator 88, the chroma signal C is demodulated and the color difference signal B is
-Y is formed. The output of the demodulator 82 is passed through the low-pass filter 84 to remove unnecessary components, and the output of the low-pass filter 84 is supplied to the modulator 85. Also,
The output of the demodulator 88 is passed through a low-pass filter 90 to remove unnecessary components, and the output of the low-pass filter 90 is supplied to a modulator 911.

A carrier signal of 5 inches (ω [shiψ)] is supplied from a terminal 86 to the converter 85, which modulates the color difference signal R-Y with an aperture whose position is shifted by φ. The output of the adder 35 is supplied to the adder 87. Further, the modulator 91 is supplied with a carrier signal of cos (0° C. and φ) from a terminal 92, and the color difference signal B-Y is shifted in phase by φ and is rotated in parallel. The output of the modulator 91 is sent to the adder 87
supplied to In addition H87, the output from modulator 85 and the output from modulator 91 are added to form chroma signal C. The output of the adder 87 is supplied to the adder 93, where the brightness signal Y and the chroma signal C from the adder 87 are added together, and a composite video signal is output from the adder 93 and output from the output terminal 94. taken out.

However, in the case of the HUE control circuit of the above-mentioned method, only the chroma signal C is extracted, the phase is changed by φ, and the chroma signal C is added to the ki degree signal Y. As shown in FIG. 6A, the luminance signal Y is As shown in FIG. 6B, in a frequency band where the frequency component and the frequency component of the chroma signal C overlap (indicated by diagonal lines in the figure), the amplitude characteristic changes depending on the amount of shift tH.

Furthermore, as a method other than the above-mentioned HIJ control circuit, a method has been proposed in which HUE control is performed by shifting the composite signal for a certain period of time while keeping the amplitude characteristics constant. This method is superior to the above-mentioned methods in that there is less deterioration in image quality, and when it is implemented by analog processing, it can be implemented relatively easily by using a delay line, phase, etc.

However, it is difficult to achieve this through digital processing, especially when using an FIR type (acyclic type) digital filter, since the number of filter coefficients is finite. This is difficult to maintain and impossible to achieve without deteriorating image quality. Therefore,
HU using a TrR type (cyclic type) digital filter.
It is possible to realize an E control circuit.

The transfer function H(z>) of a conventional general IIR type (cyclic type) digital filter is expressed as ao (0
≦nl≦'1/I> and bo (0≦n≦゛〈)
f 89 and t a8. −・H(z) = □ ... It is shown by (1).

Here, when (M=N), (b,=3N-0), the above equation (1) becomes H(z) =□, and in this above equation (2), z=e- When it is 8, it becomes H(z) −. That is, the amplitude characteristic and the zero characteristic are ・H<z)i
=1 ZHCz) = β (ω) : Σ al, sin (nω) ;= -2t
an-'mi='Ia, sin (., 1-n snow〇-,
Digital all-pass filter (all-band-pass filter) whose amplitude characteristics are constant and only the phase can be changed.
becomes. That is, CM = N ), (,b
An iTR type digital filter that satisfies the condition n = a'i-n) is an all-bus filter,
- As an example, the configuration of an all-bus filter (N=3) is shown in FIG.

As shown in FIG. 7, the all-pass filter is a subtracter 10
2. Adder 112. Three delay circuits 103-105. and six coefficient multipliers 106 to 111.

In FIG. 7, 101 is an input terminal, and the digital input signal is sent from the input terminal 101 to the subtractor 1.
02. The output of the subtracter 102 is transmitted to the delay circuit 10
35 and the coefficient is ao.
0 change is supplied. The output of the delay circuit 103 has a coefficient a
The coefficient is supplied to the multiplier 108 set to 2 and the multiplier 110 set to the coefficient al, and is also supplied to the delay circuit 104.

A multiplier 10 in which the output of the delay circuit 104 has a coefficient a.
7 and a multiplier 111 with a coefficient of 32! This signal is also supplied to the delay circuit 105.

The output of the delay circuit 105 is the coefficient a. Multiplier 106
It is also supplied to the Calo calculator 112.

The output of each of the multipliers 106 to 108 is '/A multiplier 102
In the subtracter 102, the outputs of each of the multipliers 106 to 108 are subtracted from the input signal, and the result of this subtraction is used as the output of the subtracter 102. Multiplier 1
The respective outputs of 09 to Ill are supplied to the adder 112,
In the adder 112, the output of the delay circuit 105 and the output of each of the multipliers 109 to 111 are added, and the result of this addition is output as the output of the all-pass filter, and is sent to the terminal 113.
taken from.

The transfer function H(2) of the all-bus filter (N=3) shown in FIG. 7 is expressed as follows, where 2 is an operator.

However, in actual hardware, it is impossible to simultaneously perform multiple arithmetic operations in one circuit, and the multi-input subtracter 102 of the all-pass filter shown in FIG. 7 has two subtracters as shown in FIG. This is realized by two-man powered adders 102a, 102b and one two-man powered subtracter 102C. Furthermore, the multi-input adder 112 of the all-pass filter shown in FIG. 7 is realized by three two-man power adders 112a, 112b, and 112c, as shown in FIG.

That is, the filtering process of the feedback loop related to the denominator of the transfer function is performed by adding the outputs of each of the multipliers 106 to 108 by +1if (Next Iγ
1 wheat is subtracted by a two-man subtractor 102C. In addition, in the addition process of two output stages related to the numerator of the transfer function, similarly, in the two-manpower additions 112a and 112b, after sequentially adding the respective outputs of the multipliers 109 to 111, the two-manpower adder 112C It is done in

(2) Problems to be Solved by the Invention) The all-bus filter (N=3) shown in FIG. 8 requires at most one multiplication process and three addition processes, as described above. The arithmetic processing must be completed within one sampling period of the digital input signal. For this reason, when the sampling frequency is high, for example, the wave number of sampling j is 14.3
If it is as high as 11Z, the calculation speed becomes a problem and it is difficult to apply the method.

Therefore, the purpose of this invention is (*11E:rli=\H
Even in the case of a digital input signal with a sampling frequency higher than IZ, the characteristics of the original all-bus filter
can operate without compromising accuracy and accuracy.
・Providing high-speed digital filters.

Means for Solving Problem S] This invention divides the configuration of an IIR type filter having a constant amplitude characteristic into a first part corresponding to the denominator of the transfer function and a second part corresponding to the numerator, and at least This is a high-speed digital filter whose special advantage is that the configurations of the first and second parts are simplified by setting one coefficient to 0, and that they are equivalently transformed.

C action] The TTR type all-bus filter is divided into a part corresponding to the denominator of the transfer function and a part corresponding to the numerator, and the coefficients having the same value of lu are set to 0 and simplified. , a maximum of one addition and 1 before and after the delay circuit.
A delay circuit is inserted and the multiplier is transformed equidistantly so that there are only 1 multiplication, and even if the coefficient of the multiplier is 1 to a power of 2 i! If this is determined, it is possible to increase the sampling period to the time required for one round of addition processing.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment in which the present invention is applied to a third-order 11R type all-bus filter, for example, where (N=3).

Generally, the transfer function H(2) of an all-bus filter is expressed as H(z) −□, where the operator is 2 and the filter coefficient is al (0≦n≦N), and forms the denominator of the transfer function. The coefficients of each term correspond inversely to the coefficients of each term forming the numerator. Therefore, the transmission amount HH(z) of the third-order all-bus filter with (N=3) is as follows.

Figure 3 shows that speeding up to a certain extent can be achieved by dividing the transfer function into blocks based on the transfer function of a third-order all-bus filter into a feedback loop part related to the denominator of the transfer function and an output stage part related to the numerator. This figure shows the configuration of an all-bus filter, and will be explained in order to facilitate understanding of one embodiment.

In FIG. 3, the portions 2 to 10 are related to the denominator of the transfer function, and the portions 11 to 19 are related to the numerator of the transfer function.

A digital human input signal is supplied to the subtracter 2 from an input terminal l. A multiplier 3 whose coefficient is ao as the output of the subtracter 2
, are supplied to the multiplier 5 whose coefficient is set to al and the multiplier 8 whose coefficient is set to 3□. The output of the multiplier 3 is supplied to the multiplier 6 via the delay circuit 4. Multiply! :
The output of the L unit 5 is supplied to an adder 6, the output of the delay circuit 4 and the output of the multiplier 5 are added in the adder 6, and the addition result is supplied to the adder 9 via the delay circuit 7. . The output of the multiplier 8 is supplied to the adder 9, the output of the delay circuit 7 and the output of the multiplier 8 are added together in the adder 9, and the addition result is supplied to the subtracter 2 via the delay circuit 10. In the subtracter 2, the output of the delay circuit 40 is subtracted from the input signal.

The output from the subtracter 2 is sent to the adder 13 via the delay circuit 11.
a multiplier 12 whose coefficient is a2;
The multiplier 15 with the coefficient a and the multiplier 18 with the coefficient ao are respectively supplied. The output of the multiplier 12 is supplied to the adder 13, and in the adder 13, the delay circuit 1
1 and the output of the multiplier 12 are added, and the addition result is supplied to the adder 16 via the delay circuit 14. The output of the multiplier 15 is supplied to the adder 16, the output of the delay circuit 14 and the output of the multiplier 15 are added in the adder 1G, and the result of the multiplier is sent to the adder 19 via the delay circuit 17.
supplied to The output of the multiplier 18 is supplied to the adder 19, and the adder 19 combines the output of the delay circuit 17 and the multiplier 1.
The output of adder I9 is taken out from output terminal 20 as the output of the all-pass filter.

As shown in Figure 3, the third-order all-pass filter has a maximum of two addition processes and one multiplication process before and after the multiple delay circuits 4.7.10, 11, 14°17. It is configured.

For example, the coefficient of the all-pass filter shown in Fig. 3 is 3.
2, the respective coefficients of multipliers 8 and 12 are (az=0
), the all-pass filter shown in FIG. 3 is simplified and equivalently transformed into an embodiment shown in FIG. 1.

In FIG. 1, the portions 22 to 28 are related to the denominator of the transfer function, and the portions 23.29 to 38 are related to the numerator of the transfer function. Additionally, delay circuits 23.30 and 33.37 are inserted to increase speed.

A digital input signal is supplied from an input terminal 21 to a subtracter 22 . The output of the subtracter 22 is supplied via a delay circuit 23 to a multiplier 24 having a coefficient ao and a multiplier 26 having a coefficient al.

The output of multiplier 24 is supplied to adder 27 via delay circuit 25. The output of the multiplier 26 is supplied to an adder 27, and the adder 27 combines the output of the delay circuit 25 and the multiplier 2
6 is added, and the addition result is supplied to the subtracter 22 via the delay circuit 28.

In the subtracter 22, the output of the delay circuit 28 is subtracted from the input signal, and the output of the subtracter 22 is supplied to the adder 34 via the delay circuit 23 and three delay circuits 29 to 31 inserted in series. Ru. Also, along with that, subtraction 'R2
The output of 2 is passed through a delay circuit 23 to a multiplier 32 with a coefficient a, and a multiplier 32 with a coefficient a. The signal is supplied to the multiplier 36 which is set as follows.

The output of the multiplier 32 is supplied to the adder 34 via the delay circuit 33, the output of the delay circuit 3■ and the output of the delay circuit 33 are added in the adder 34, and the output of the adder 64 is supplied to the delay circuit 34. 35 to an adder 38. The output of the multiplier 36 is supplied to the adder 38 via the delay circuit 37, the output of the delay circuit 35 and the output of the delay circuit 37 are added in the adder 38, and the output of the adder 38 is supplied to the all-pass filter. It is taken out from the output terminal 39 as an output.

By setting the coefficient a2 to 0 as shown in FIG. 1, the third-order all-pass filter shown in FIG. , delay circuits 23, 30, 33, and 37 are inserted so that there is only one addition process and one multiplication process at most, and the delay circuits 33 and 37 are equivalently transformed.

That is, the transfer function H(z) for the portions 22 to 28 in FIG. 1 is represented by two bows. Furthermore, the transfer function H(z) for the portions 29 to 38 in FIG. 1 is H(z)=(ao+
a, z-'tz-").z-'. Therefore, the overall transfer function H(z) is as follows.

FIG. 2 shows another embodiment of the present invention. For example, multipliers 3 and 18 whose coefficients are ao and multipliers 5 and 15 whose coefficients are a of the all-pass filter shown in FIG. 3 described above. By setting the respective coefficients to (a.=a,=O), the all-pass filter shown in FIG. 1
1.

In FIG. 2, the portions 42 to 44 are related to the denominator of the transfer function, and the portions 45 to 49 are related to the numerator of the transfer function. Additionally, delay circuits 46 and 48 are inserted to increase speed.

A digital input signal is supplied from an input terminal 41 to a subtracter 42 . The output of the subtracter 42 is supplied to a multiplier 43 with a coefficient a2, and ! v! The output of the calculator 43 is sent to the delay circuit 4.
4, the subtractor 42 is removed. In the subtracter 42, the output of the delay circuit 44 is calculated from the input signal. It will be settled.

'tkH, the output of the device ↓2 is supplied to the adder 49 via the serially inserted delay circuits 45 and 46, and is also supplied to the multiplier 47 whose coefficient is set to a2. The output of the adder 47 is supplied to the adder 49 via the delay circuit 48, and the adder 49 adds the output of the delay circuit 46 and the output of the delay circuit 48, and the output of the adder 49 is supplied to the all-bus filter. It is taken out from the output terminal 50 as an output.

As shown in FIG. 2, the coefficient a. By setting 0 and f to 0, 2') the third-order all-pass filter shown in Figure 3 is simplified, and the addition process is performed at most once in the two delay circuits around 44°450. The delay circuits 46 and 48 are inserted so that only multiplication processing is present, and the circuit is transformed isometrically.

That is, the transfer function H(z) for the portions 42 to 44 in FIG. 1 is expressed as follows. Furthermore, the transmission amount fiH(z) regarding the portions 45 to 49 in FIG. 1 is H(z) −(a
z-hz-")-z-'. Therefore, the overall transfer function H(z) is as follows.

FIG. 4 shows a further embodiment of the present invention. In each of the above-mentioned embodiment and other embodiments, the parts that perform the same operation have a common configuration, and the obtained all bus This is a series of filters connected in series.

In FIG. 4, parts indicated by 52 to 57 correspond to other embodiments, and in FIG. It is considered common by In addition, in FIG. 4, portions 59 to 66 correspond to one embodiment, and the portions 59 to 66 correspond to the first embodiment.
In the figure, the coefficient is a. The coefficients of the multipliers 24 and 36 are a.

The multipliers 26, 32 and delay circuits 25, 37, which are configured as follows, are shared by the multipliers 67, 69, and the delay circuit 68.

Further, a delay circuit 58 for speeding up is inserted between a portion corresponding to another embodiment and a portion corresponding to one embodiment.

A digital input signal is supplied from an input terminal 51 to a subtracter 52 . The output of the subtracter 52 is supplied to an adder 155 via two delay circuits 53 and 54 inserted in series, and also to a multiplier 56 having a coefficient of 32. The output from the multiplier 56 is supplied to the adder 55 via the delay circuit 57, and the output from the delay circuit 57 is supplied to the subtracter 52, where the output from the delay circuit 57 is subtracted from the input signal.

Further, in the adder 55, the 11
The power and the output of the delay circuit, U7Gara, are added together, and the sum ′!
The output of :;55 is supplied to a compensator 59 via a delay circuit 58.

The output of the adder 59 is supplied to the delay circuit 6o, and the output of the delay circuit 60 is inserted in series and supplied to the adder 64 via the delay circuits 61, 62, and 63 of At the same time, the output of the delay circuit 60 has a coefficient a. The coefficient a is supplied to a multiplier 67 and a multiplier 69 whose coefficient is a.

The output of the multiplier 67 is supplied to the delay circuit 68, the output of the delay circuit 68 is supplied to the adder 66, and the adder 7
1. The output of multiplier 69 is supplied to adder 71 and also to adder 64 via delay circuit 70 .

In the adder 64, the output from the delay circuit 63 and the output from the delay circuit 70 are added, and the output of the adder 64 is supplied to the adder 66 via the delay circuit 65. Further, in the adder 71, the output from the delay circuit 68 and the multiplier 6
The output of the adder 71 is supplied to the subtracter 59 via the delay circuit 72.

In the five subtracters, the output of the delay circuit 72 is subtracted from the output of the adder 55 supplied via the delay circuit 58. Further, in the adder 66, the output of the delay circuit G5 and the output of the delay circuit 68 are added, and the output of the adder 66 is taken out from the output terminal 73 as the output of the all-pass filter.

The transfer function of the all-pass filter shown in FIG. 4 is H(z) 1+azZ-'+a12-" +(ao-, a+az
)Z-'+a6a2Z-'.

It should be noted that all-pass filters having the same configuration as in other embodiments of the present invention but having different coefficient values may be further connected in cascade to obtain an arbitrary phase characteristic without further impairing the amplitude characteristic.

[Effects of the Invention] In this invention, the ITR type all-pass filter is divided into a part corresponding to the denominator of the transfer function and a part corresponding to the numerator, and at least one set of coefficients having the same value is set to 0, thereby simplifying the filter. At the same time, delay circuits are inserted and transformed isometrically so that there are at most 10 additions and 1 multiplication before and after the delay circuit.

Therefore, according to the present invention, if the coefficient of the multiplier is selected to be a power of 2, for example, the sampling period can be increased to approximately the time required for one addition process, and for example, the sampling frequency can be increased to 14.3 MHz. ) (It can also be used in UE control circuits.

According to still another embodiment of the present invention, two different types of low-order all-pass filters are cascade-connected to form a high-order all-pass filter, so that the coefficient of the multiplier is a power of 2. Even in this case, it is possible to arbitrarily obtain a phase characteristic that is better than that of one embodiment and the other embodiments without impairing the oscillation $i characteristic. Furthermore, if it is desired to obtain a zero characteristic at an arbitrary level more than in the other embodiments, it is possible to achieve this by further connecting a plurality of stages of all-pass filters with the same configuration but different coefficients.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the invention, FIG. 2 is a block diagram of another embodiment of the invention, and FIG. Tsuku diagram,
FIG. 4 is a block diagram of still another embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional HUE control circuit.
Figures A and 6B are route diagrams used to explain a conventional HUE control circuit, and Figures 7 and 8 are block diagrams of conventional IrR type all-pass filters. Explanation of main symbols in the drawings 2.22.42.52. 59: Subtractor, 6,9°13
．． 16.19.27.34.38,49,5, :),6
4.71: Adder, 3. i8.24.36°67; coefficient is a. A multiplier with 5. I5, 26.32.69:
Multiplier with coefficient a, 8°12.43.47,5
Ci: the power nNH14,7,10,I where the coefficient is mixed with a2
I, 14.17.23°23.28.29 ~31.
33. 3. U, 37.4, U, 46.
48. 53. 34. 57, 58
．． 60°61-63, 6.5.68.72. Delay circuit Fig. 3 Example 8I゛ Fig. 1 It! 17) 1 formation of olfactory use ng Fig. 2 Further formation of prong row U configuration' Fig. 4 Fig. 5 Fig. 6 Fig. 8

Claims (1)

[Claims] By dividing the configuration of an IIR type filter having a constant amplitude characteristic into a first part corresponding to the denominator of the transfer function and a second part corresponding to the numerator, and setting at least one coefficient to 0, the first part is obtained. A high-speed digital filter characterized in that the configurations of the first part and the second part are simplified and equivalently modified.