JPS62160822A - Evaluation device for digital-analog converter - Google Patents

Abstract

PURPOSE:To realize the continuous evaluation of the settling characteristic by using plural binary-coding pseudo random signals so as to form an impulse response waveform and its timing pulse relating to the settling of an A/D converter of object of evaluation. CONSTITUTION:A binary-coding pseudo random signal S1 is generated (6) based on a reference clock CL1 and fed to an evaluation object D/A converter 2. Further, a binary-coding pseudo random signal S2 is generated (8) based on a clock CL2 deviated timewise slightly from the clock CL1. Then an output signal S2 of the converter 2 and a signal S2 are multiplied (10), the result is fed to an LPF 12 and an impulse response waveform relating to the settling of the converter 2 is obtained at the output. Further, the signals S1, S2 are multiplied (11), the result is fed to an LPF 14 and a timing pulse to the impulse response waveform is obtained at the output.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides D/A variation 1! i! ! The present invention relates to an apparatus for evaluating settling characteristics of high-speed D/A converters, and more specifically, to an apparatus suitable for evaluating settling characteristics of high-speed D/A converters.

(Prior Art) One of the items for evaluating the characteristics of a high-speed D/A converter is the settling characteristic, which represents the temporal response characteristic of an analog output signal to changes in the digital input signal to be converted.

FIG. 5 is a block diagram showing an example of a device for evaluating the settling characteristics of a conventional high-speed D/A converter. In FIG. 5, reference numeral 1 is an input terminal for a digital signal Vi, and the digital signal vi is applied to necessary pit input terminals of the D/A converter 2 to be evaluated and also to the variable delay circuit 3.

The output signal of the D/A converter 2 to be evaluated is applied to a sample and hold circuit 4, and sampled and held according to the output signal of the variable delay circuit 3.

(Problems to be Solved by the Invention) However, according to such a conventional combination, only one point of the settling waveform can be measured in one measurement.
It is not possible to measure a continuous settling waveform. Furthermore, a high-speed sample-and-hold circuit and a highly accurate variable delay circuit must be used, which increases the cost.

The present invention has been made with attention to these points, and its purpose is to provide a device that has a relatively simple configuration and can continuously evaluate the settling characteristics of a D/A converter. be.

(Means for Solving the Problems) The present invention that achieves the above object includes a means for adding a 111 pseudorandom signal to the D/A converter to be evaluated, and Iro issue and evaluation target D/A
a first multiplier for multiplying and subtracting a second binary pseudorandom signal having a different time relationship with respect to the first 2(a) pseudorandom signal applied to the converter; and a first binary pseudorandom signal. a second multiplier for multiplying the signal by a second 2fa pseudo-random signal; and a means for outputting an impulse response waveform related to settling of the D/A converter to be evaluated from the output signal of the first multiplier. and means for outputting a timing pulse of an impulse response waveform from the output signal of the second multiplication means.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, reference numeral 5 denotes an input terminal for a reference D-check signal CL+ having a frequency of fO, and is connected to a first 2fifl pseudo-random noise generator 6. 7, the frequency is slightly shifted from the reference clock signal OL+ (for example, fo
+δ) is an input terminal for the clock signal CL2, and is the input terminal for the second 2
It is connected to a value pseudorandom signal generator 8. 1st
2(
The zeroed pseudo random signal S1 is subjected to appropriate logic conversion in the logic circuit 9 and is applied to each pit input terminal of the D/A converter 2. In other words, the logic circuit 9 is D
For example, in the case of a 4-bit input, the digital input signal changes from the state of [0-1-1-IJ to rl-0-0-
Convert so that it changes to the OJ state. As a result, WI11i vs. Mongolia D/opposite D under the most severe digital input conditions
/A converter. 10 and 11 are multipliers, respectively. One input terminal of the first multiplier 10 has a D/A
The analog output signal S3 of the converter 2 is applied, and the output signal S2 of the second binary pseudo-random tip generator 8 is applied to the other input terminal. The output signal S of the first 2wi pseudo-run signal generator 6 is applied to one input terminal of the second multiplier 11, and the second
The output signal S2 of the binary pseudorandom signal generator 8 is added. The output signal S4 of the first multiplier 10 is applied to a low-pass filter (hereinafter referred to as LPF) 12 to remove components with a frequency of 6 or higher, and then an evaluation pair 10/A! shown in FIG. 2(a) is obtained. The impulse response waveform signal S which has been applied to the settling of the multiplier 2 is outputted to the output terminal 13, and the output signal S6 of the second multiplier 11 is outputted to the LPF1.
4 and the components with frequencies 6 and above are removed.
The output terminal 1 is used as a timing pulse signal S7 indicating time zero of the impulse response waveform signal S5 as shown in FIG.
5 is output. Note that these multipliers 10 and 11 have, for example, an analog input terminal, a digital input terminal, and an analog output terminal, and when the digital signal applied to the digital input terminal is 1-level, the analog input signal applied to the analog input terminal is is output to the analog output terminal without being inverted, and when the digital signal applied to the digital input terminal is at L level, the analog input signal applied to the analog input terminal is inverted and output to the analog output terminal. A ring modulator is used.

The operation of the device configured in this way will be explained.

In FIG. 1, the output signal S of the D/A converter 2 to be evaluated is
3 to y (t), and the output of LPFl 2 to Ss wog (
t ), m 1 (7) 21fl(t, the output signal S1 of the pseudorandom signal generator 6 is expressed as s+ (t), the second
The output signal of the binarized pseudo-endum Shintan generator 8 @S2 is S
z (t), evaluation 111Ii target D/A converter 2
If the response between the digital input signal and analog output signal of is expressed by h(τ), then V (t) = fh (τ)・5t(t−τ)dt...
・Equation (1) holds true.

Then, if the output signal s4 of the multiplier 1o is written as Go(t), then Qo (t)=82 (j) ・V(j>
-(2).

Furthermore, by making the time constant of LPFl2 sufficiently larger than 1/δ, the output signal S5 of LPFl2 becomes Qo
It is proportional to the integral of (t) over a certain period,
The following relationship holds true.

CJ=fg. (t) dt = fS2 (t)・y(t) dt = fd t Sz (t) ・ fh (τ) ・
s wealth (t-τ) dt = fdr h (r) ・fdt S+ (t-
Z')82(t>
...(3) Here, Sz (j> is Sz
It is generated by a clock with almost the same frequency as (j). Therefore, if the difference δ between the frequencies of these clocks is sufficiently small, that is, the period of the binary pseudorandom signal is 1/
If it is sufficiently large compared to δ, 82(t) becomes 51(1
) can be considered as a signal shifted by time τ0, and can be expressed by the following equation.

82 (t>=SI (t-τ.)...
-(4) Note that τ0 changes every moment due to the difference δ in the clock frequencies.

Substituting equation (4) into equation (3), Q-fdτ h(τ)・fdts+(j-τ)・S+(
i−τ0〉...(5). Here, Sl is a pseudo-random signal, and its autocorrelation is as shown in FIG.

If the randomness of Sl is ideal, /dts+(i-τ)・S, (t,-τ0)-δ(τ-
τ0) ...(6), and (5
) becomes as shown in equation (7).

Q=, /'dτ h(τ)・δ(τ−τ0)−h+ (
τ0) ... (7) This (7
) represents the impulse response waveform signal S5 related to the settling of the evaluation pair ftD/A converter 2, which is output to the output terminal 13 as shown in FIG. 2(a). Note that the time axes in FIGS. 2(a) and 2(b) are expanded by fo/δ times.

With this configuration, the settling waveform of the evaluation customer D/A converter can be continuously measured with a relatively simple configuration, and the time axis of the settling waveform can also be expanded.

In the embodiment shown in FIG. 1, in order to measure the evaluation target D/A conversion under the strictest digital input conditions,
We have shown an example in which the output signal of the pseudo random signal generator is subjected to a predetermined logic conversion using a logic circuit and then added to each bit input terminal. The logic circuit for performing this can be omitted.

Furthermore, in the above embodiment, an example was explained in which the entire settling waveform is swept by slightly different frequencies of the two systems of 21-directed pseudorandom signals, but as shown in FIG. A similar function can also be obtained by branching the binary pseudorandom signal into two systems and providing a predetermined delay time between the signals of both systems using the variable delay circuit 16. According to such a configuration, the delay time of the 21 rectified pseudo-random signal can be kept constant for the time required for measurement, so the multipliers 17 and 18 can be used instead of the LPFs 12 and 14 in FIG. Using the sample and hold circuits 19 and 20, it is possible to integrate only the period of the binary pseudorandom signal. Note that 21 is a frequency divider that divides the reference clock signal CL+ according to the period section of the binary pseudorandom signal.

(Effects of the Invention) As explained above, according to the present invention, the settling characteristics of the D/A converter can be continuously evaluated for one song with a relatively simple configuration. can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams of the operation of FIG. 1, FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. The figure shows a conventional high-speed type D/
FIG. 3 is a block diagram showing an example of a device for evaluating the settling characteristics of a Δ converter. 2... Wave meter! 11iD/A'El: Exchanger, 5.
7... Input terminal, 6.8... Binarized pseudo-random signal generator, 9... Logic circuit, 10.11... Multiplier, 12.14... Low pass filter, 13.15
Output terminal, 16...possible'! i delay circuit, 17.18・
...integrator, 19.20...ripple hold circuit,
21... Frequency divider. Figure 5

Claims (1)

[Claims] means for applying a first binary pseudorandom signal to the D/A converter to be evaluated; and a first binary pseudorandom signal applied to the output signal of the D/A converter to be evaluated and the D/A converter to be evaluated; a first multiplier that multiplies the random signal by a second binarized pseudo-random signal having a different time relationship; and a first multiplier that multiplies the first binarized pseudo-random signal and the second binarized pseudo-random signal. a second multiplication means; a means for outputting an impulse response waveform related to settling of the D/A converter to be evaluated from the output signal of the first multiplication means; 1. A D/A converter evaluation device comprising means for outputting a timing pulse.