JPS62160757A - Semiconductor substrate - Google Patents

Semiconductor substrate

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Publication number
JPS62160757A
JPS62160757A JP259786A JP259786A JPS62160757A JP S62160757 A JPS62160757 A JP S62160757A JP 259786 A JP259786 A JP 259786A JP 259786 A JP259786 A JP 259786A JP S62160757 A JPS62160757 A JP S62160757A
Authority
JP
Japan
Prior art keywords
oxide
stabilized zirconia
single crystal
substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP259786A
Other languages
Japanese (ja)
Inventor
Toshiyuki Shinozaki
敏幸 篠崎
Fumihiro Atsunushi
厚主 文弘
Tsukasa Doi
土居 司
Yoshinobu Kakihara
柿原 良亘
Shuji Enomoto
修治 榎本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP259786A priority Critical patent/JPS62160757A/en
Publication of JPS62160757A publication Critical patent/JPS62160757A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Inorganic Insulating Materials (AREA)

Abstract

PURPOSE:To form a semiconductor substrate (SOI substrate), which does not give adverse effect on the performance of a semiconductor device, by coating the entire surface of a silicon substrate with a single crystal film of stabilized zirconia. CONSTITUTION:The entire surface of a silicon substrate 1 is coated with a stabilized zirconia film made of an oxide single crystal, which is arranged by a sputtering method. For this coating, one kind of the following materials is added into zirconium oxide ZrO2 as a stabilizer within a range of 6.1mol%-12.6mol%: yttrium, oxide Y2O2, magnesium oxide MgO, calcium oxide CaO, samarium oxide Sm2O3, gadolinium oxide Gd2O3, terbium oxide Tb2O3, ytterbium oxide Yb2O3 and scandium oxide Sc2O5. Thus a single crystal in a cubic system is obtained at a growth temperature of 550-1,000 deg.C. Said stabilized zirconia film can maintain the crystal structure with respect to temperature history.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、半導体基板の改良に関するものである。[Detailed description of the invention] <Industrial application field> The present invention relates to improvements in semiconductor substrates.

〈従来の技術〉 として用いられている。SO8技術は、サファイア基板
の上にシリコン薄膜をエピタキシで成長させてMOSデ
バイスを構成し、従来問題となっていた配線容量とアイ
ソレーションとを解決し、MOSデバイスの高速化をは
かるようにしだものである。
It is used as <conventional technology>. SO8 technology is a MOS device made by growing a silicon thin film on a sapphire substrate by epitaxy, solving the conventional problems of wiring capacitance and isolation, and increasing the speed of MOS devices. It is.

〈発明が解決しようとする問題点〉 SO8技術において、サファイア基板上に高温度でシリ
コン等の半導体をエピタキシャル成長させると、原料ガ
スに使用している水素によってサファイア基板の母体表
面の一部が還元され、サファイア基板上に形成したシリ
コンのエピタキシャル層の中には還元された金属Atも
しくは酸素がドープされ、汚染されることがあり、また
半導体材料との格子ミスマツチが比較的大きいという問
題があることが知られている。したがって、サファイア
基板上にエピタキシャル成長した半導体層註 の電気的特性や結晶性が著しく低下させている。
<Problems to be solved by the invention> In SO8 technology, when a semiconductor such as silicon is epitaxially grown on a sapphire substrate at high temperature, a part of the base surface of the sapphire substrate is reduced by the hydrogen used as the raw material gas. The silicon epitaxial layer formed on the sapphire substrate may be doped with reduced metal At or oxygen and become contaminated, and there is also the problem of a relatively large lattice mismatch with the semiconductor material. Are known. Therefore, the electrical characteristics and crystallinity of the semiconductor layer epitaxially grown on the sapphire substrate are significantly deteriorated.

またこのサファイア基板自体が非常に高価であることか
らも、このサファイア基板は、実用基板としての性能が
阻害されていて、十分実用化されていないのが実情であ
る。
Furthermore, since the sapphire substrate itself is very expensive, the performance of this sapphire substrate as a practical substrate is hindered, and the reality is that it has not been fully put into practical use.

一方、酸化物の単結晶膜を直接シリコン基板上に形成す
る試みもなされているが、この試みはシリコン基板表面
に形成された自然酸化膜によって、酸化物単結晶をヘテ
ロエピタキシャル成長させることが困難であった。
On the other hand, attempts have been made to form oxide single crystal films directly on silicon substrates, but these attempts have been difficult due to the natural oxide film formed on the silicon substrate surface, making it difficult to heteroepitaxially grow oxide single crystals. there were.

本発明はこのような点にかんがみて創案されたもので、
半導体デバイスの特性に影響を及ぼさない半導体基板を
提供することを目的としている。
The present invention was devised in view of these points.
The purpose is to provide a semiconductor substrate that does not affect the characteristics of semiconductor devices.

〈問題点を解決するための手段〉 本発明に係る半導体基板は、シリコン基板全面に安定化
剤を添加した酸化ジルコニウムによって形成した安定化
ジルコニアの単結晶膜を被覆するようにしたものである
<Means for Solving the Problems> A semiconductor substrate according to the present invention is such that the entire surface of a silicon substrate is coated with a single crystal film of stabilized zirconia formed from zirconium oxide to which a stabilizer has been added.

く作 用〉 本発明に係る半導体基板の構造は、シリコン基板全面に
酸化物単結晶の安定化ジルコニア膜が覆われている。し
たがって、半導体基板として採用した場合は、たとえ高
温度(〜1200℃)に上げて、シリコン等の半導体材
料をエピタキシャル成長させても、今←→サフフイア基
板のように基板材料が分解されることもなく、また還元
反応は生じない。
Effects> In the structure of the semiconductor substrate according to the present invention, the entire surface of the silicon substrate is covered with a stabilized zirconia film made of an oxide single crystal. Therefore, when used as a semiconductor substrate, even if semiconductor materials such as silicon are epitaxially grown at high temperatures (~1200°C), the substrate material will not be decomposed as it is now with sapphire substrates. , and no reduction reaction occurs.

更に、基板表面に形成された安定化ジルコニア薄膜は活
性な水素に対して安定であるため、シリコン等の半導体
エピタキシャル成長層にジルコニウム(Zr)や酸素等
の汚染を与えることもなく、高純度のエピタキシャル膜
が得られる。
Furthermore, since the stabilized zirconia thin film formed on the substrate surface is stable against active hydrogen, it does not contaminate the epitaxial growth layer of semiconductors such as silicon with zirconium (Zr) or oxygen, resulting in high-purity epitaxial growth. A membrane is obtained.

したがって、本発明に係る構造の絶縁基板をシリコン等
の半導体デバイスに適用させることにより、素子間分離
が容易となり、しかもラッチアップフリーとなるため、
超高速で高密度、高集積化のバイポーラトランジスタや
CMO8等のVLSIの作成が可能となる。
Therefore, by applying the insulating substrate having the structure according to the present invention to a semiconductor device made of silicon or the like, isolation between elements becomes easy, and latch-up becomes free.
It becomes possible to create ultra-high-speed, high-density, highly integrated VLSIs such as bipolar transistors and CMO8.

〈実施例〉 以下、図面を参照して本発明の一実施例を詳細に説明す
る。
<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明に係る半導体基板の基本構造を図式的に
示した断面図である。
FIG. 1 is a sectional view schematically showing the basic structure of a semiconductor substrate according to the present invention.

第1図において、シリコン基板1の全面に単結晶の安定
化ジルコニア膜2 ((ZrO2)+ −n(Y20a
)nまだは(Zr 02 )、 −H(MgO) n。
In FIG. 1, a single crystal stabilized zirconia film 2 ((ZrO2)+ -n(Y20a
) n Madada (Zr 02 ), -H(MgO) n.

(Zr02)+ −n (CaO)n、 (ZrOz 
)t −n(Sm20s ) n、(ZrO2)+−n
(Gd203 )n。
(Zr02)+ -n (CaO)n, (ZrOz
)t −n(Sm20s)n, (ZrO2)+−n
(Gd203)n.

(ZrO2)+ −n (Tb203) n 、 (Z
rOz )t−yl(Yb+03)n 、(ZrO2)
+−n(SC205)n )が被覆される。ただし、n
値は0.061から0.126の間である。
(ZrO2)+ -n (Tb203) n, (Z
rOz)t-yl(Yb+03)n, (ZrO2)
+-n(SC205)n) is coated. However, n
The value is between 0.061 and 0.126.

スパッタ法を用いると、母体材料である酸化ジルコニウ
ムZrO2は、成長温度400℃でエピタキシャル成長
するが、この酸化ジルコニアZrO2の単結晶膜は、結
晶系が単斜晶であり、高温になると正方晶に結晶転移を
起こすことが知られている。そのため、温度履歴によっ
て7.4%もの体積膨張が生じ、自己破壊を起こしてし
まう。
When the sputtering method is used, the base material zirconium oxide ZrO2 grows epitaxially at a growth temperature of 400°C, but the single crystalline film of this zirconia oxide ZrO2 has a monoclinic crystal system, and crystallizes into a tetragonal system at high temperatures. It is known to cause metastasis. Therefore, a volumetric expansion of 7.4% occurs due to the temperature history, resulting in self-destruction.

しかしながら、酸化ジルコニウムZrO2の中に安定剤
として、酸化イツトリウムY20aや酸化マグネシウム
MgO、酸化カルシウムCaO、酸化サマリウムSm2
O3、酸化ガドリニウムGd2O3,酸化テルビウムT
b2O3,酸化イッテリビウムYb2O3゜酸化スカン
ジウム5c205のうち1種を6.1モル%〜12.6
モル%の範囲で添加することにより、成長温度550℃
〜1000℃で立方晶の単結晶膜が得られる。この安定
化ジルコニア膜は、温度履歴に対しても結晶構造を維持
することが判明した。
However, zirconium oxide ZrO2 contains yttrium oxide Y20a, magnesium oxide MgO, calcium oxide CaO, and samarium oxide Sm2 as stabilizers.
O3, gadolinium oxide Gd2O3, terbium oxide T
b2O3, ytterbium oxide Yb2O3゜Scandium oxide 5c205 6.1 mol% to 12.6
By adding within the range of mol%, the growth temperature can be increased to 550°C.
A cubic single crystal film is obtained at ~1000°C. It was found that this stabilized zirconia film maintains its crystal structure even under temperature history.

本発明の特徴は、安定化したジルコニア膜2をスパッタ
法により膜厚が0.2〜1.0μmの範囲でシリコン基
板1上に形成させることにある。
The feature of the present invention is that a stabilized zirconia film 2 is formed on the silicon substrate 1 by sputtering to a thickness in the range of 0.2 to 1.0 μm.

特に、単結晶の安定化ジルコニア膜2は、高温に耐え、
しかも熱衝撃に強い。また、シリコンとの格子のミスマ
ツチは、4%以内とサファイアよりも小さいため、格子
整合性が良い。
In particular, the single crystal stabilized zirconia film 2 can withstand high temperatures,
Moreover, it is resistant to thermal shock. Furthermore, the lattice mismatch with silicon is less than 4%, which is smaller than that with sapphire, so lattice matching is good.

次に、上記第1図に示した本発明に係る半導体基板の作
成過程の一例を具体的に説明する。
Next, an example of the manufacturing process of the semiconductor substrate according to the present invention shown in FIG. 1 will be specifically explained.

上記した安定化ジルコニア膜2はシリコン基板(100
)1上にAr+02の反応性マグネトロンスパッタ法に
より作製した。シリコン基板1は表面に存在する自然酸
化膜の影響を除去するため、予めHCI:H2O2”H
20=3 :1 : 1 、90〜100℃。
The stabilized zirconia film 2 described above is a silicon substrate (100
) 1 by reactive magnetron sputtering using Ar+02. The silicon substrate 1 is coated with HCI:H2O2"H in advance in order to remove the influence of the natural oxide film existing on the surface.
20=3:1:1, 90-100°C.

5〜10分間浸し、スパッタ装置内で真空中5pa (3X10    )、900℃、30分熱処理する方
法を施した。その後安定化ジルコニア膜2をスパッタ法
により作製したが、スパッタ条件は、ガス圧(Ar+0
2)0.5pa、Rf power〜4W/cn 、基
板温度900℃で行ない、安定化ジルコニア膜2を膜厚
1000A成長させた。
The sample was immersed for 5 to 10 minutes, and then heat treated in a vacuum at 900° C. for 30 minutes at 5 Pa (3×10 ) in a sputtering device. Thereafter, a stabilized zirconia film 2 was produced by sputtering, and the sputtering conditions were as follows: gas pressure (Ar+0
2) Stabilized zirconia film 2 was grown to a thickness of 1000 Å by using 0.5 pa, Rf power ~ 4 W/cn, and substrate temperature of 900°C.

上記のような条件で成長させた安定化ジルコニア膜2の
結晶評価をRHEED、X線解析等によって行なった結
果(100)面の成長が認められ、良好な単結晶膜が成
長していることが認められた。
As a result of crystal evaluation of the stabilized zirconia film 2 grown under the above conditions using RHEED, X-ray analysis, etc., growth of the (100) plane was observed, indicating that a good single crystal film had grown. Admitted.

このように従来シリコン基板(100)面上に酸化物単
結晶をヘテロエピタキシャル成長させることが、自然酸
化膜の存在により困難であったが、上記のように自然酸
化膜を除去する事前の処理を施すことにより、スパッタ
法により、容易に安定化ジルコニア膜の単結晶化が可能
となった。
Conventionally, it has been difficult to heteroepitaxially grow an oxide single crystal on the (100) surface of a silicon substrate due to the presence of a natural oxide film, but it is possible to perform a preliminary treatment to remove the natural oxide film as described above. As a result, it has become possible to easily form a stabilized zirconia film into a single crystal by sputtering.

次に、本発明に係る半導体基板を用いたシリコン半導体
基板の製造過程を第2図と共に説明する。
Next, the manufacturing process of a silicon semiconductor substrate using the semiconductor substrate according to the present invention will be explained with reference to FIG.

第2図において、シリコン等の半導体エピタキシャル膜
12は半導体基板11上にモノシラン炬 (SiH4) 、塩化硅素(SiCl2)、)リクロロ
シラン(S i HCt3)などの半導体原料ガスを使
用し、基板温度を950℃〜1250℃に加熱して、基
板全面に亘って、0.3〜20μmの範囲内の厚さに形
成する。形成したエピタキシャル膜12は、前述の如く
、サファイア基板1からのAtや酸素等の汚染の心配も
なく、良好な電気的特性や結晶性を示す。
In FIG. 2, a semiconductor epitaxial film 12 made of silicon or the like is formed on a semiconductor substrate 11 by using a semiconductor material gas such as monosilane (SiH4), silicon chloride (SiCl2), or dichlorosilane (S i HCt3) to maintain the substrate temperature. It is heated to 950° C. to 1250° C. to form a thickness in the range of 0.3 to 20 μm over the entire surface of the substrate. As described above, the formed epitaxial film 12 exhibits good electrical properties and crystallinity without worrying about contamination with At or oxygen from the sapphire substrate 1.

なお、本発明は、シリコン半導体デバイスだけでなく 
、G a A sやInPなどの化合物半導体デバイス
にも適用出来ることは言うまでもない。
Note that the present invention is applicable not only to silicon semiconductor devices.
It goes without saying that the present invention can also be applied to compound semiconductor devices such as GaAs, InP, and the like.

〈発明の効果〉 以上のように本発明によれば、シリコン基板上に良質な
酸化物の単結晶膜の形成された半導体基板が構成され、
それによって、半導体デバイスにとができる。
<Effects of the Invention> As described above, according to the present invention, a semiconductor substrate is constructed in which a single crystal film of a high-quality oxide is formed on a silicon substrate,
This results in sharpening of the semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る半導体基板の基本構造を示す断面
図、第2図は本発明に係る半導体基板を用いたシリコン
半導体基板の断面を示す図である。 1 ・・・シリコン基板、 2 ・・・単結晶安定化ジルコニア膜、11・・・半導
体用絶縁基板、 12・・・シリコンエピタキシャル膜。 代理人 弁理士 福 士 愛 彦(他2名)第1図 ンLlコシ牛講不り線鯛ω区 第2図
FIG. 1 is a cross-sectional view showing the basic structure of a semiconductor substrate according to the present invention, and FIG. 2 is a cross-sectional view showing a silicon semiconductor substrate using the semiconductor substrate according to the present invention. 1...Silicon substrate, 2...Single crystal stabilized zirconia film, 11...Insulating substrate for semiconductor, 12...Silicon epitaxial film. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1 NLL Koshi Ushiko Furi Line Tai ω Ward Figure 2

Claims (1)

【特許請求の範囲】 1、スパッタ法を用いて、成長温度550℃〜1000
℃、安定化剤の添加量6.1モル%〜12.6モル%の
範囲内で形成した安定化ジルコニアの単結晶膜をシリコ
ン基板全面に被覆してなる半導体基板。 2、前記安定化剤として酸化ジリコニウムZrO_2中
に酸化イットリウムY_2O_3、酸化マグネシウムM
gO、酸化カルシウムCaO、酸化サマリウムSm_2
O_3、酸化ガドリニウムGd_2O_3、酸化テルビ
ウムTb_2O_3、酸化イッテリビウムYb_2O_
3、酸化スカンジウムSc_2O_5のうちの1種の安
定化剤を添加してなることを特徴とする特許請求の範囲
第1項記載の半導体基板。
[Claims] 1. Using a sputtering method, growing at a temperature of 550°C to 1000°C.
C, and a stabilizer added in an amount of 6.1 mol% to 12.6 mol%, the entire surface of a silicon substrate is coated with a single crystal film of stabilized zirconia. 2. Yttrium oxide Y_2O_3 and magnesium oxide M in zirconium oxide ZrO_2 as the stabilizer.
gO, calcium oxide CaO, samarium oxide Sm_2
O_3, gadolinium oxide Gd_2O_3, terbium oxide Tb_2O_3, ytterbium oxide Yb_2O_
3. The semiconductor substrate according to claim 1, wherein one type of stabilizer selected from the group consisting of scandium oxide Sc_2O_5 is added.
JP259786A 1986-01-08 1986-01-08 Semiconductor substrate Pending JPS62160757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP259786A JPS62160757A (en) 1986-01-08 1986-01-08 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP259786A JPS62160757A (en) 1986-01-08 1986-01-08 Semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS62160757A true JPS62160757A (en) 1987-07-16

Family

ID=11533793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP259786A Pending JPS62160757A (en) 1986-01-08 1986-01-08 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS62160757A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010232379A (en) * 2009-03-26 2010-10-14 Seiko Epson Corp Method of manufacturing semiconductor substrate
CN103367392A (en) * 2012-03-27 2013-10-23 中国科学院微电子研究所 Semiconductor on insulator structure and manufacturing method thereof
US9447737B2 (en) 2013-06-14 2016-09-20 Walbro Llc Throttle cable retainer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010232379A (en) * 2009-03-26 2010-10-14 Seiko Epson Corp Method of manufacturing semiconductor substrate
CN103367392A (en) * 2012-03-27 2013-10-23 中国科学院微电子研究所 Semiconductor on insulator structure and manufacturing method thereof
US9447737B2 (en) 2013-06-14 2016-09-20 Walbro Llc Throttle cable retainer

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