JPS62159558A - Frequency modulator - Google Patents

Abstract

PURPOSE:To obtain sufficient frequency accuracy and stability by using a PLL to stabilize the frequency when no information is sent, releasing the PLL loop to fix control information to a variable frequency oscillator when the information is sent so as to prevent the fluctuation of the reference frequency. CONSTITUTION:The frequency controller is provided with the 1st and 2nd frequency dividers 15, 16 a phase comparator 17 and a phase difference information storage device 18. The 1st frequency divider 15 frequency-divides a frequency modulation signal at the non-transmission of information, stores the internal state before the start of transmission at information transmission and the 2nd frequency divider 16 frequency-divides the reference clock at non-transmission of informattion and holds the internal state before the start of transmission at transmission of information. The phase comparator 17 inputs the frequency- division outputs from the two frequency dividers 15, 16 and outputs the phase difference information between both of them. The phase difference information storage device 8 stores the phase difference information from the phase comparator 17, gives an output to the variable frequency oscillator 11 as control information and stores the control information at the transmission of information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a frequency modulator with excellent frequency stability.

[Technical background of the invention and its problems]

Frequency modulators play an extremely important role in the technology of modulating and transmitting information. Generally, a continuous phase frequency modulator is used as a frequency modulator, except when the modulation index is sufficiently large for data transmission. This is usually configured mainly using an externally controlled oscillator, such as a voltage controlled oscillator (hereinafter referred to as rVCOJ). However, VCOs have large characteristic fluctuations due to ambient temperature, power supply voltage, and aging, and the compensation circuit for obtaining sufficient frequency stability is also complex.

Therefore, as a method of frequency stabilization of vCO, PLL
(phase-locked loop) is generally used, but if the PLL continues to operate while data is being transmitted, if the data signal includes a DC offset, the PLL will
Since the operation is performed to cancel the offset, there is a problem in that the center frequency erroneously fluctuates.

This problem can be alleviated somewhat by making the frequency response of the PLL gentler, but there is no solution to this problem when transmitting long packets or the like.

On the other hand, in order to resolve the above problem, P
Frequency stability is also compensated by fixing the reference frequency during transmission by cutting the LL loop and simultaneously holding the PLL feedback control voltage in the state before the start of transmission. However, with this method, when data transmission is finished and the PLL starts operating again, the phase of the VCO output signal and the reference clock signal are out of phase, and it takes time for the PLL to re-engage. There was a problem. If it takes time to pull in the data in this way, the next data cannot be transmitted immediately.

[Purpose of the invention]

The present invention has been made based on the above-mentioned circumstances, and its purpose is to achieve high frequency stability and a PLL
An object of the present invention is to provide a frequency modulator that can immediately transmit the next data without requiring time for re-engaging.

[Summary of the invention]

The present invention provides a variable frequency oscillator to obtain a frequency modulated signal of information to be transmitted, a reference clock generating circuit to obtain a reference clock, and a frequency controller to control based on the phase difference between the frequency modulated signal and the reference clock. A frequency modulator configured with a PLL loop that obtains information and feeds it back to the variable frequency oscillator to control a reference frequency of a frequency modulation signal, characterized in that the frequency controller is configured as follows.

That is, the frequency controller includes first and second frequency dividers, a phase comparator, and a phase difference information accumulator. The first frequency divider divides the frequency of the frequency modulated signal when not transmitting information, and maintains the internal state before the start of transmission when transmitting the information. The second frequency divider divides the frequency of the reference clock when information is not being transmitted, and maintains the internal state before the start of transmission when transmitting the information. The phase comparator inputs the divided outputs from these two frequency dividers and outputs phase difference information between the two. The phase difference information accumulator accumulates the phase difference information from the phase comparator, outputs it to the variable frequency oscillator as the control information, and holds the control information when transmitting the information.

〔Effect of the invention〕

According to the present invention, when information is not being transmitted, the frequency is stabilized by the PLL, and when information is being transmitted, the PLL loop is released and the control information to the variable frequency oscillator is fixed, thereby preventing fluctuations in the reference frequency. Therefore, sufficient frequency accuracy and stability can be obtained.

Moreover, according to the present invention, instead of directly comparing the phases of the frequency modulation signal and the reference clock, both signals are frequency-divided by first and second frequency dividers, and the frequency-divided outputs of these frequency dividers are are compared in phase. The outputs of these two frequency dividers maintain the state before the start of transmission when transmitting information. Therefore, even if the phase of the frequency modulation signal and the reference clock are out of phase when the information transmission is finished, the outputs of the two frequency dividers do not change from the state before the information transmission, and the The next data can be transmitted immediately without requiring any action.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the data to be transmitted is
is input, frequency modulated, and output. The modulated output of vColl is input to the first AND gate 12.

On the other hand, the reference clock output from the reference clock generator 13 corresponds to the reference frequency of the frequency modulation signal.

This reference clock is input to the second AND gate 14. The other inputs of these two AND gates 12 and 14 have R T which becomes low level when transmitting data.
An S (request to 5end) signal is input. The output of the AND gate 12 is sent to the first frequency divider 1
5, and the output of the AND gate 14 is input to the second frequency divider 16. These frequency dividers 15 and 16 perform frequency division by 256, for example. The outputs of frequency dividers 15 and 16 are provided as two inputs of phase comparator 17. A specific configuration of this phase comparator 17 is shown in FIG. The output of the phase comparator 17 is fed to a low pass filter (LPF) 19 via an analog switch 18.

The analog switch 18 is controlled on and off by the above-mentioned signal T1. The output of the LPF 19 is fed back as a control voltage of vColl via a voltage buffer 20 with high human power impedance.

Next, the operation of the frequency modulator configured in this way will be explained.

Since the RTS signal is at a high level when data is not being transmitted, AND gates 12 and 14 are both disabled. Therefore, the first frequency divider 15
The modulation signal is input to 2S16, and the reference clock is input to the second frequency division 2S16, and the frequency is divided by 256.

The output of the first frequency divider 15 is used as the SIN input of the phase comparator 17, and the output of the second frequency divider 16 is used as the SIN input of the phase comparator 17.
are respectively given as RIN inputs.

The phase comparator 17 compares the phases of SIN and RIN, and outputs a discharge pulse if the phase of SIN is leading, and outputs a charge pulse if the phase of RIN is leading. . To explain this operation based on the block diagram in Fig. 2 and the waveform diagram in Fig. 3, first,
When both SIN and RIN are at a low level, the gate voltage of the first transistor 31a of the output buffer 7 circuit 31 is at a high level, and the gate voltage of the second transistor 31b is at a low level. Therefore, the PDOLIT terminal maintains a high impedance state. When the phase of SIN is ahead of the phase of RIN as shown in the first half of the waveform diagram in FIG. 3, SIN rises first, so the output of the gate circuit 32 changes from low level to high level, The flip-flop 33 is set and the Q output also becomes high level. As a result, the Nant gate 34 changes to a low level, the output of the inverter 35 changes to a high level, and a discharge current flows from the PDO1JT terminal via the transistor 31b. This state is maintained by the function of the gate circuit 32. Next, when the RIN signal rises, the output of the gate circuit 36 changes to a high level, and the flip-flop 37 becomes set and the Q
Output goes high. As a result, the output of the Nant gate 38 changes to low level, so the output of the Nant gate 34 becomes high level again, and the output of the Nant gate 39 does not change, so that the PD of the output buffer circuit 31 ends up
The OUT terminal returns to a high impedance state. On the other hand, R
When the phase of IN is ahead of the phase of SIN,
Due to the symmetrical operation, the gate voltages of transistors 31a and 31b of the output buffer circuit both become low level, so only transistor 31a is turned on.
Charge current will be output from the PDOUT terminal.

Analog switch 18 is turned on by the YT1 signal. For example, as shown in FIG. 4, the LPF 19 is composed of an integrating circuit including a resistor R1 and a capacitor C1, and changes the charge accumulated in the capacitor C1 in response to the charge pulse or discharge pulse, thereby changing the output voltage level. It has become. Note that the series circuit of the resistor R2 and the capacitor C2, which are connected in parallel with the resistor R1, is for ensuring the stability of the system. This LP
The output voltage of F19 is connected to VC through voltage buffer 20.
Since it is given as the control voltage of Oll, the one-order difference between the outputs of frequency dividers 15 and 16, that is, the phase difference between the modulation output and the reference clock, is made zero (the oscillation frequency of VCOII is adjusted. In this state, PL
An L-loop is formed.

On the other hand, when transmitting data, the rT lower double signal is at a low level, so the AND gates 12 and 14 are enabled. This inhibits input to frequency dividers 15, 16, and frequency dividers 15, 16 maintain their internal state before data transmission. j. Further, at this time, the analog switch 18 is also turned off.

The LPF 19 retains internal charge because the circuits connected to its input and output are in a high impedance state. As a result, the control voltage of VCOll is fixedly applied. Therefore, even if there is a DC offset in the data, the reference frequency will not fluctuate. In this embodiment, even when the analog switch 18 is in the on state, the output buffer 7 circuit 31 is in a high impedance state during the period when it is not being charged or discharged, so that the charging voltage does not fluctuate.

Next, when the data transmission is completed, the RTST signal returns to high level, the AND gates 12 and 14 are again disabled, and the analog switch 18 is also turned on. At this time, since the internal state of the PLL maintains the state before data transmission, the next data can be transmitted immediately without requiring almost any re-draw time. At this time, even if the modulation signal and the reference clock are considerably out of phase, the influence appearing on the output of the frequency divider 15, 16 is 1/256 in the case of frequency division by 256.

This effect will be more pronounced if the frequency division ratio is increased.

Note that the present invention is not limited to the embodiments described above. FIG. 5 shows an example in which the charge pump function is realized by a perfect integrator using a digital circuit and a D/A converter, and FIG. 6 is a waveform diagram thereof. Frequency dividers 41,42 have clock enable inputs, which are controlled by the RTS.

When RTS is at a high level, the frequency dividers S41 and S42 perform a frequency dividing operation, and stop the frequency dividing operation when the RTS is at a low level. The outputs of the frequency dividers 41 and 42 are input to the phase comparator 43, and the up ratio output d corresponding to charge and discharge pulses is
It is output as an own output. The OR gate 44 and the AND gate 45 enable the up/down counter 46 only when one of the up ratio outputs and the down output is output and the RTST signal is in a high state, that is, when data is not transmitted. Then, the reference clock is given as a clock signal. Whether to count up or count down depends on whether the dwon output from the phase comparator 43 is at a high level or a low level. The output of the up/down counter 46 is converted into an analog value by the D/A converter 47, and fed back to the VCOIO as a control voltage via the LPF 48.

On the other hand, when RTS goes low to perform data transmission, the frequency dividers 41, 42 and up/down counter 46 suspend their respective operations and continue to maintain their respective states. However, the correct control voltage continues to be supplied to VCOll.

Even in this case, when data transmission is completed and π1'3- returns to high level, PLL operation continues without re-pulling. In this embodiment, many parts are composed of digital circuits. Therefore, it has the advantage that it is very convenient when integrated into an LSI.

Although described in detail above, the present invention is not limited to these examples. For example, it goes without saying that the functions of the up/down counter 46 and the D/A converter 47 can be implemented using analog techniques using operational amplifiers, capacitors, and analog switches. Further, the D/A converter may use pulse width modulation, and in that case, all the frequency controllers except the LPF can be digitalized, making it very suitable for IC implementation.

It goes without saying that the present invention is applicable not only to modulation using digital signals such as FSK, but also to modulation using analog modulation signals.

In this case, it is only necessary to adjust the modulation index at one adjustment point, and it is possible not only to reduce the cost by using an IC, but also to reduce the adjustment cost by reducing the number of adjustment points.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a frequency modulator according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a phase comparator in the same modulator, and FIG. 3 is an operation of the same phase comparator. 4 is a waveform diagram for explaining the L in the same modulator.
FIG. 5 is a block diagram showing the structure of a frequency modulation circuit according to another embodiment of the present invention, and FIG. 6 is a waveform diagram for explaining the operation of the modulator. DESCRIPTION OF SYMBOLS 11... Voltage controlled oscillator, 12... First AND gate, 13... Fundamental clock generator, 14... Second
AND gate, 15.41...first frequency divider, 16
゜42...Second frequency divider, 17.43...Phase comparator, 18...Analog switch, 19.48...L
P.F. 20... Voltage buffer amplifier, 44... OR gate, 45... AND gate, 46... Up/down counter, 47... D/A converter. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Factor 2 PHA9: 0Lrr Figure 3 Figure 5

Claims (5)

[Claims] (1) A variable frequency oscillator that inputs information to be transmitted and outputs a frequency modulation signal according to the information, a reference clock generator that generates a reference clock, and a position between the frequency modulation signal and the reference clock. and a frequency controller that outputs control information based on a phase difference to the variable frequency oscillator to control a reference frequency of the frequency modulation signal, wherein the frequency controller controls the frequency when the information is not transmitted. a first frequency divider that divides the frequency of the modulated signal and maintains the internal state before the start of transmission when transmitting the information; a first frequency divider that divides the frequency of the reference clock when the information is not transmitted, and maintains the internal state before the start of transmission when transmitting the information; A second frequency divider that holds the internal state, a phase comparator that inputs the divided outputs from these two frequency dividers and outputs phase difference information between the two, and a phase comparator that receives the phase difference information from this phase comparator. A frequency modulator comprising: a phase difference information accumulator that accumulates and outputs the control information to the variable frequency oscillator and holds the control information when transmitting the information. (2) The phase difference information accumulator includes a low-pass filter equipped with a capacitor that accumulates the output charge from the phase comparator, and a voltage buffer with high input impedance inserted on the output side of the low-pass filter. circuit, and an analog switch inserted between the phase comparator and the low-pass filter, and when the analog switch is turned off by an external control signal, the charge stored in the capacitor is held. 2. The frequency modulator according to claim 1, wherein an internal state is maintained. (3) The phase difference information accumulator is a perfect integrator having an input control circuit, and the input control circuit maintains its internal state by stopping the integration operation of the perfect integrator using an external control signal. A frequency modulator according to claim 1, characterized in that: (4) The perfect integrator is composed of a circuit including a capacitor, and the input control circuit has a function of stopping charging/discharging of the capacitor by an external control signal. Frequency modulator as described in section. (5) The perfect integrator is composed of a circuit including a counter and a D/A converter, and the integration function is realized by up-counting and down-counting the counter, and the input control circuit performs the counting operation of the counter by an external control signal. 4. The frequency modulator according to claim 3, wherein the frequency modulator has a function of stopping.