JPS62159469A - Manufacture of insulated gate type field effect transistor - Google Patents

Abstract

PURPOSE:To form an oblique surface of a predetermined oblique angle by less implanting ions by ion implanting the edge of a gate, and using an arsenic as implanting ions in case of forming the oblique surface by surface etching. CONSTITUTION:A polycrystalline silicon film 1 is formed through a gate oxide film 2 on the surface of a silicon substrate 3, and its edge is plasma etched. Then, an arsenic 4 is implanted to control an oblique angle theta to a desired value. The implanting quantity is determined in response to the required oblique angle Q to be increases as the oblique angle increases. Since the arsenic which causes a large damage at implanting time as implanting ions is used in this manner, the implanting amount can be reduced. No ion punch through occurs to the substrate, and the channel length can be readily controlled by regulating the oblique angle.

Description

[Detailed description of the invention]

Technical field to which the invention pertains The present invention relates to an insulated gate field effect transistor (hereinafter referred to as MO3F) whose gate is made of polycrystalline silicon and has an inclined surface.
ET). [Prior art and its problems] It improves the step coverage of a protective film such as PSG that is coated on the gate of a MOS FET, and also improves the step coverage due to ion penetration when performing source 1 drain diffusion by ion implantation using the gate as a mask. It is known to form sloped surfaces at the edges of the gate so as to provide channel length control. To form such a sloped surface of a polycrystalline silicon gate, a method is used in which argon or phosphorus ions are implanted into the gate, and the gate is etched by a method such as plasma etching. However, with this method, the damage to the polycrystalline silicon film caused by implanted ions is small, and the diffusion coefficients of argon and phosphorus are large, making it difficult to control the tilt angle and requiring a large amount of implantation. There were drawbacks.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a MOSFET in which the tilt angle can be easily controlled when forming the sloped surface of a polycrystalline gate, and the amount of ion implantation of an impurity element can be reduced.

[Key points of the invention]

The present invention involves implanting ions into the edge of a gate made of polycrystalline silicon of a MOSFET and performing surface etching to form a sloped surface. The above purpose is achieved by implanting arsenic ions at the same acceleration because arsenic causes great damage to the polycrystalline gate even when ions are implanted at the same acceleration.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIG. FIG. 1 (fat) is a cross section after the edge of a polycrystalline silicon film 1 formed on a silicon substrate 3 via a gate oxide film 2 is plasma etched without ion implantation. The amount of arsenic implanted is l x l'Q
” / aJ, Figure 1 (cl is arsenic implantation t I
As is clear from Figure 0, which is a cross section after etching when arsenic 4 is introduced into the surface of polycrystalline silicon Ml by ion implantation of 10''/, cj, the sloped surface 5 formed on the polycrystalline silicon gate 1 is The inclination angle θ can be controlled by the amount of arsenic implanted. [Effects of the Invention] According to the present invention, large damage is caused during implantation as ions for forming an inclined surface of a polycrystalline silicon gate, and the diffusion coefficient is By using a small amount of arsenic, the amount of implantation can be reduced, there is no penetration of ions into the silicon substrate, the channel length can be easily controlled by adjusting the tilt angle, and the stent coverage of the protective film is good. The effect of forming a polycrystalline gate inclined surface can be obtained.

[Brief explanation of drawings]

FIG. 1 shows the effect of the present invention, where fa+ is when no ion implantation is performed, (bl is implantation 11 × 10 ” / ci+
(C1 is a cross-sectional view after etching when arsenic ions were implanted with an implantation rate of 311 : Inclined surface.

Claims (1)

[Claims] 1) When forming a sloped surface by performing surface etching after ion implantation into the edge of a gate made of polycrystalline silicon, the implantation amount is increased as the desired slope angle increases. A method for manufacturing an insulated gate field effect transistor characterized by implanting arsenic ions.