JPS62159459A - Semiconductor image pickup device - Google Patents

Abstract

PURPOSE:To enhance an optical sensitivity and to read out at a high speed by providing an SIT photosensor, a capacitor for storing the output signal of the photosensor and a CCD for transferring a signal stored in the capacitor. CONSTITUTION:MOSs 9, 11 are turned ON by pulses phiP, phiT, and signal storage capacitors 12 connected with line reading lines PL1-PLM are biased to a predetermined voltage VP. When the MOS 9 is turned OFF and a pulse phiG1 is applied to a first row address line GL1, the output signal of the SIT photosensor of the first row is stored in the capacitor 12. This signal is transmit ted through an input gate 13 to a vertical CCD 14. Similarly, the outputs of the photosensors of the second row and the later are sequentially transferred to the vertical CCDs 14, and these signals are output through the horizontal CCD15 and output SIT 16. Since the SIT photosensor is used, high output is obtained, and the CCD is used, the signal can be read out at a high speed in the simple circuit.

Description

[Detailed Description of the Invention] (Object of the Invention) [Field of Industrial Application] The present invention relates to a static induction transistor (3 tatic I
Transistor, hereinafter abbreviated as SIT. ) type image sensor (SIT image sensor) and charge transfer element (Charge Cou
pled[)evice, hereinafter abbreviated as CCD. ,
) is integrated. The objective is to provide a semiconductor imaging device that has excellent weak light sensitivity characteristics, features such as low noise, high speed, and wide dynamic range, as well as easy configuration of peripheral circuits. It is widely used as a capacitive solid-state image sensor.

(Conventional technology) Conventionally, solid-state image sensors include photodiodes and MO
M pixels, which are composed of S switch transistors, are arranged in a matrix and read out signals using the X-Y address method.
A CPD (Charge Prim) is a combination of an O8 type image sensor, a CC[) type image sensor in which pixels and a signal transfer section are composed of charge transfer elements, and an MO8 type image sensor and a CCD type image sensor.
In addition, a solid-state image sensor based on SIT was already proposed by the present inventor in 1978, and was published in Japanese Patent Application Laid-open No. 15229/1983.
``Semiconductor Imaging Device'', and JP-A No. 59-45781 ``
"Semiconductor Imaging Device" and others.

In addition, an example of a system using a SIT optical sensor in the photodetection section and a COD in the signal transfer circuit is published in Japanese Patent Application Laid-Open No. 59-108463.
``Solid-state imaging device''.

[Problem that the invention seeks to solve]

Most of the readout methods for S■T image sensors that have been proposed so far are the X-Y address method, so
In order to operate an SI image sensor configured in an NXM matrix, a shift register with N-stage and M-stage outputs is required. In particular, when high-speed readout is required or for large-scale sensor matrices, a large-scale pulse generation circuit that outputs high-speed pulses is required, making circuit design difficult and requiring more advanced process technology.

On the other hand, although a CCD type image sensor can have a relatively simple drive circuit, it has a drawback of low light sensitivity.

The MO8 type image sensor and the CPD type image sensor also have a light sensitivity of 1 or less.

In the method shown in the above-mentioned Japanese Patent Laid-Open No. 59-108463, which uses an SIT photosensor for the photodetection section and uses a COD for the signal transfer circuit, a load resistor and a video power supply are respectively connected to all signal readout lines, and the gate address Parallel signal outputs on each signal readout line read in are input to the COD, and the readout portion is made into one line of CCO. In this signal@readout method, it is necessary to connect a load resistance of the same value and a video power supply voltage to each signal readout line, and the structure and operation are compound pyramidal. Also,
Since the COD for the transfer circuit is a 1-line COD, 1
The next gate line cannot be addressed until the reading of the seven cells on the gate line is completed. That is, in terms of high-speed reading, there is a limit to the reading speed.

(Means for Solving the Problems) In order to solve the above-mentioned problems, in the present invention, the photodetection section is constituted by an SIT photocell having excellent photosensitivity characteristics, and the signal transfer section is configured by a two-phase or three-phase SIT photocell. Frame transfer type or interline type COD that can be driven by pulses
The signal output circuit is COD or SI.
We propose a semiconductor imaging device consisting of a T amplifier.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of the present invention in which the photodetection section is composed of a gate accumulation type SIT optical sensor whose source is grounded, the signal transfer section is composed of a frame transfer type COD, and the output circuit is composed of an SIT amplifier. A circuit diagram of an example is shown.

Each SIT photocell consists of a static induction phototransistor and a gate capacitor connected to the gate of a D''R induction phototransistor. The drains of the SIT photocells are connected to readout lines RLI...1, RL2...2, common to each row.
The gate capacitors of the SIT photocells connected to RL3...3,..., RLM...4 and arranged in the same column are connected to the common gate address line GL.
1...5, GL2...6, GL3...7,...
..., GLN...8 is connected. Each read line is connected to a precharge power source V, . . . , 10 via a precharge MOS transistor 9. Furthermore, each readout line has a transformer 77M08)
- connected via a transistor 11 to a diode 12 forming a signal storage capacitor and further via an input gate 13 to a signal transfer vertical CCD 14; A horizontal CCD 15 is connected to the final stage of the vertical CCD 14. The final stage of the horizontal CCD 15 is connected to an SIT amplifier 16. At the gate of the SIT amplifier,
A refresh MO8 transistor 17 and a signal storage diode 18 are connected. The vertical CCD 14 and the horizontal CCD 15 are each driven by a two-phase clock.Next, the operation of the embodiment shown in FIG. 1 will be explained. During the photoaccumulation time, light incident from the surface of each SIT photocell generates electron-hole pairs in the depleted high-resistance region between the source and train of the SIT photocell, of which electrons are connected to the drain. However, the holes accumulate in the gate region of the gate capacitor, which is left floating in the M flow. When reading a signal, first transfer pulse φ
Transfer MOS transistor 1 by 1...19
1 is turned on, then the precharge MOS transistor 9 is turned on by the precharge pulse φ, . Ru. Precharge pulse φ work... After 20 is cut off, the first
The gate address φCT1...21 is applied,
Optical information from each SIT photocell in the first row is stored in the signal storage diode 12. At this time, the current flowing between the source and drain of the SIT photocell is a current obtained by amplifying the optical information accumulated in the gate region of the SIT photocell. The optical gain of SIT, that is, the ratio of the number of electrons in the output current to the number of incident photons, is extremely large, and data has been obtained in which it exceeds 10 2 in direct current terms. For this reason, the weak light intensity of the SIT photocell is very high and a large output current can be obtained. First gate address pulse φ, 1...2
1, the transfer pulse φA...19 is also turned off. Next, input gate pulses φ1...25 and vertical CCD driving two-phase clocks φ...26, φ2A
...2A 7 transfers optical information to the vertical COD. continuation,
Transfer pulses φa...19 and precharge pulses φ2...20 are applied again, the readout line and signal storage diode 12 are biased, and after the precharge pulses φ,...20 are cut off, the second Gate address pulse φ. 2...22 is applied, and each S in the second column
The optical information of the IT photocell is stored in a signal storage diode. After turning off the second gate address pulses φ, 2...22, the transfer pulses φ7...19 are also turned off and the optical information is sent to the vertical COD. In this way, all S
The optical information of the IT photocell is sent to the vertical COD. The optical information sent to the vertical COD is sequentially sent to the horizontal COD,
Two-phase clock for driving horizontal CCD from horizontal CCD φ18
...28, φ28 ...29, S of the output circuit
It is sent to the IT amplifier 16. The gate of the SIT amplifier 16 is biased to a constant value by the refresh power supply VR...31 by applying a refresh pulse φ8...30 to the refresh MOS transistor 17 before optical information is sent. At this time, signal storage diode 1
8 is also biased.

In this state, optical information is sent to the gate of the SIT amplifier,
The amplified current is available at the output. Signal transfer section C
By configuring with OD, the configuration of peripheral circuits for outputting drive pulses becomes simple. In the SITI image sensor using the X-Y address method, the sensor matrix is NX
If the photocell is composed of M photocells, an N-stage output shift register for gate address and an M-stage output shift register for read line selection are required. When the scale of the sensor matrix increases or in the case of high-speed readout operations, the shift register also increases in scale and is required to increase in speed. In particular, the read line selection shift register needs to operate at high speed. On the other hand, in the circuit system shown in FIG. 1, all the CODs in the signal transfer section are driven by two-phase clocks, so the configuration of the peripheral circuits is simplified. especially,
Two-phase clock for horizontal CCD that operates at the highest speed φ...
・28, φB 2B...Two configurations become simpler. SITI photocell has extremely high photosensitivity (excellent weak light sensitivity characteristics,
It also has a wide dynamic range. In order to make full use of the characteristics of this SITI photosensor, the charge capacity of the diode 12 constituting the signal storage capacitor must be
It is necessary to design the photocell to a size that can accommodate a sufficient amount of saturation output current. The SI lower width transducer has low distortion and a large output of 1q, making it suitable for output circuits. The output circuit uses the FDA method (Floating[) 1ffu, which is conventionally used in CCD image sensors.
sion Amplifier method), FGA method (F
floating Qate Amplifier
r method), DFGA method (Q1tributed F
! oating Gate△1plifier method)
But that's fine.

FIG. 2 shows another embodiment of the present invention in which the photodetection section is composed of a source follower mode SIT optical sensor, the signal transfer section is composed of a frame transfer type COD, and the output circuit is composed of an SITI width transducer. The circuit diagram is shown.

Each SITI photocell consists of a static induction phototransistor with a capacitor at its gate. In the SITI sensor configured with NXM matrix,
The drain of the StT photocell is formed by the n-type buried region or the 0-type substrate common to all cells and is connected to the drain bias voltage ivD...101, and the sources of the iT photocells arranged in the same row are Read lines common to each row RL1...102, RL2...103,
RL3...104,..., RLM...1
The gate address lines GL1...106, GL2...107, which are common to each column, are connected to the gate address lines GL1...106, GL2...107,
GL3...108,...,GLN...1
Connected to 09. Each read line is grounded via a preset MOS transistor 110. The other circuit configurations are the same as the embodiment shown in FIG. In FIG. 2, 111 is a transfer MOS transistor, 112 is a diode forming a signal storage capacitor, 113 is an input gate, and 114 is a vertical CO for signal transfer.
D, 115 is horizontal CCD for signal transfer, 116 is SITI
117 is a refresh MO8 transistor, 11
8 is a signal storage diode, φ...119 is a transfer pulse, φ8...120 is a preset pulse, φ
, 1...121, φe2...122, φ. 3 ・
・・・123, φGN ・・・124
are gate address pulses, φ□...125 are input gate pulses, φ1A...126, φ2A-127 are two-phase pulses for signal transfer vertical CCD driving, φ1. ...1
28, φ2. . . . 129 is a two-phase pulse for signal transfer horizontal COD driving, φ, . The static induction phototransistor constituting each SITI photocell consists of a high-resistance region formed by an epitaxial growth layer on the n+ region common to all SIT photocells formed by an n-type buried region or an n-type substrate, and a high-resistance region It has a surface gate structure consisting of an n+ region formed in stripes on the surface of the region and p+ gate regions formed in stripes across an n region on the surface. As a surface n+ region source, the buried region or the n+ region of the substrate
Since the electrostatic induction phototransistor is operated in the upright mode with the + region drain, the source follower mode S
The IT optical sensor can obtain a larger output than the SIT optical sensor shown in the embodiment of FIG. The timing of the drive pulses is the same as in the embodiment of FIG. The diode 112 constituting the signal storage capacitor is preset to zero potential before receiving or receiving optical information from the SIT photorel. When the lower photocell 81 is not exposed to light, the signal storage diode 112 remains at zero potential, and when light is incident on the SIT photocell, the signal storage diode 112 changes its potential to the SIT photocell in response to the light intensity. The signal storage diode 112 is discharged by the amount of current flowing and is reverse biased to a positive potential. COD
The amount of charge transferred is the saturated charge amount when the light intensity is zero, and decreases as the light intensity becomes stronger.
The operation is opposite to that of the illustrated embodiment.

In Fig. 3, the photodetection section is composed of a gate storage type SIT optical sensor in which the source of each cell is grounded, the signal transfer section is composed of an interline type COD, and the output circuit is a SIT
1 shows a circuit diagram of an embodiment of the invention, which is comprised of an amplifier; FIG.

Each SIT photocell consists of a static induction phototransistor with a capacitor at its gate. The source of each cell is grounded, and the gate capacitor is connected to a gate address terminal GT...201 common to all cells. A precharge MOS transistor 202 and a signal storage diode 203 are connected to the drain terminal of each SIT photocell, and further connected to an input gate 204. Precharge MOS transistor 20
2 drains are connected to a common precharge power supply V,...2
It is connected to 05. The optical information is transferred through the input gate to the vertical C0D206 and roughly to the horizontal C0D2'0
Sent to 7. The final stage of the horizontal C0D 207 is connected to the SrT multiplier 208 . 209 is a refresh MOS transistor, and 210 is a signal storage diode. When reading signals, all precharge MOS transistors 202 receive a common precharge pulse φ2...
・Driven by 211, all signal storage diodes 203
is biased to a constant value by a precharge power supply vP...205. After φ2 expires, the gate address pulse φ. ... 212, the optical information of all SIT photocells is stored in the signal storage diode 203. Next, the optical information is copied to the vertical C0D 206 by the input gate pulse φ 213, the vertical CCD driving two-phase clock φ1A 214, φ2A 215, and then the horizontal CCD
Transferred to 0D207. The optical information transferred to the horizontal C0D 207 is sent to the output SIT amplifier 208. The horizontal COD 207 is a horizontal COD driving two-phase clock φ,
8...216 and φ2B...217. The embodiment shown in FIG. 3 is an interline system,
All SIT photocells receive the same gate address pulse φ.

. . 212 are simultaneously addressed. For this reason,
Even when increasing the scale, it can be operated using two sets of two-phase pulses for COD driving and four other pulses.

There is also a configuration using source follower mode and interline type COD.

FIG. 4(a) is a schematic circuit diagram of the connecting portion between the SIT photocell and the signal transfer COD in the embodiment of the present invention, and FIG. This is an example of a cross-sectional structure corresponding to a circuit. In FIG. 4(a), 301 is a static induction phototransistor constituting one photocell, 302 is a gate capacitor, 303 is a signal storage diode, 304 is a COD cell, 305 is an input gate, φ, . . . 306 is the gate address pulse, vP
. . 307 is a precharge power supply, φ, . . . 308 is a precharge pulse, and φ1 . . . 309 is an input gate pulse. In FIG. 4(b), the SIT photocell, signal storage diode and COD have a common n+
It is made on a substrate 310. The SIT photocell is n
A static induction phototransistor consisting of an n+ source region and an n+ drain region 311 composed of a + substrate 310, a p+ gate region 312, an n'' high resistance layer 313, and a polysilicon electrode 314, and a silicon nitride film etc. Insulating film 3
Transparent conductive materials such as 15 and Sn0! 1,316 gate capacitors. one S
The IT photocell removes silicon dioxide St from the surrounding area.
It is electrically insulated by an isolation region 317 made of O2 or the like. The diode that makes up the signal storage capacitor is
p-well 318 and n-well provided in p-well 318
+diffusion region 319. n+ diffusion region 3
An input gate consisting of 5iOzlI 320, an electrode region 321, and a p-well 318 is provided adjacent to 19. Further, a COD is configured next to the input gate. 322 is an electrode area of the CCD. A p+ region 323 is a diffusion region for making ohmic contact with the p well, 324 is an aluminum electrode constituting a gate address line, 325 and 326 are aluminum electrodes, and 327 is S+ O2. The SIT photocell train and the signal storage diode are electrically connected. In addition, n + B plate 31
0 and p-well 318 are grounded. 328 is a precharge amount 0S transistor, which can be provided on the same substrate by a known method.

FIG. 5(a) is a circuit diagram of the connection portion between the signal transfer COD and the output circuit in the embodiment of the present invention.
b) is an example of a cross-sectional structure corresponding to the circuit in FIG. 5(a). In FIG.
3 is an SIT amplifier, 404 is a refresh MOS transistor, 405 is an output gate, φ8...406 is a refresh pulse, φ0...407 is an output gate pulse, and ■8...408 is a refresh power supply.

In FIG. 5(b), the COD, output gate, refresh MoS transistor, and SIT amplifier are fabricated on a common n+ substrate 409. 410 is COD for signal transfer
The final stage electrode, 411, is the output gate electrode;
MIS structure CO with 12 SiO2 and p well 413
It forms D. The refresh MOS transistor includes an n+ drain region 414, an n+ source region 415, a gate oxide film 416, a gate electrode 417, and a drain electrode 4.
18 and a source electrode 419. The SIT amplifier has a p" source\A region 420 and a p+ drain region 421.
and n+ gate region 422, p- high resistance region 423, source electrode 424, gate electrode 425, and drain electrode 426
It is composed of. 427 is the separation area, 428 is S
+ O2.

The structures of FIGS. 4(b) and 5(b) can be easily manufactured using conventional process techniques.

In the embodiment of the present invention shown in FIGS. 1 to 3, the output circuit may be formed using the FDA method, FGA method, or DFGA method conventionally used in CCD type image sensors. It is also effective to use an SIT amplifier in the output circuit of a conventional COD image sensor. The present invention can be applied not only to area sensors configured in a matrix but also to line sensors.

〔Effect of the invention〕

According to the present invention, it is possible to realize a solid-state imaging device that has extremely high photosensitivity compared to conventional solid-state imaging devices, has particularly high weak light detection ability, and can relatively easily configure a drive pulse circuit.

The present invention is particularly effective in applications where the sensor matrix is large-scale and high-speed readout is required. In particular, the configuration in which the SIT, which has high photodetection ability, is used as a photocell, and the COD, which simplifies the configuration of peripheral drivers, is used as the information transfer unit, takes out only the advantages of each, and easily realizes a large-capacity image sensor. .

[Brief explanation of drawings]

In Fig. 1, the photodetection section is composed of a gate storage type SIT optical sensor whose source is grounded, the signal transfer section is composed of a frame transfer 1 type CCD, and the output circuit is roughly composed of SIT optical sensors.
FIG. 2 is a circuit diagram of an embodiment of the present invention composed of an IT amplifier, in which the photodetection section is composed of a source follower mode SIT optical sensor, and the signal transfer section is a frame transfer type CO.
FIG. 3 is a circuit diagram of another embodiment of the present invention in which the output circuit is composed of a SIT amplifier and the output circuit is a SIT amplifier.
Consists of an optical sensor, and the signal transfer section is interline type C.
A circuit diagram of an embodiment of the present invention composed of an OD and an output circuit composed of an SIT amplifier, FIG. An example of a circuit diagram, Fig. 4(b) is as shown in Fig. 4(
An example of a cross-sectional M4 structure corresponding to the circuit shown in Fig. 5 (a).
) is an example of a circuit diagram of the connection part between the signal transfer COD and the output circuit in the embodiment of the present invention, and FIG.
It is an example of the cross-sectional structure corresponding to the circuit of a). 1.2.3.4.102.103.104.105...
- Readout line, 5.6.7.8.106.107.
108.109.201...Gate address line,
9.202.328...Precharge MO8t-transistor, 10.205.307...Precharge power supply, 11,111...Transfer MOS transistor, 12.18.112, 118, 203, 210.30
3.402...Signal storage diode, 13.113.
204.305...Input gate, 14.114.20
6... Vertical CC0115, 115, 207 for signal transfer
...Horizontal CCD for signal transfer, 16.116.208.
403...SIT amplifier, 17.117.209.4
04...Refresh IMO8t-ransistor, 19,
119...Transfer pulse, 20.211.30
B...Precharge pulse, 21.22.23.24
．． 121.122.123.124.212.306・
...Gate address pulse, 25.125.213.3
09...Inkage, - Tobalus, 26.27.28.2
9.126.127.128.129.214.215
．． 216.217... Two-phase clock pulse for COD drive, 30.130, 218.406... Refresh pulse, 101... Drain 'F11G! , 110
...Preset MO8t-ransistor, 120...
Preset pulse, 31.131.219.408...
·refresh? ! ! Source, 301... Electrostatic corrosion phototransistor, 302... Gate capacitor, 304
．． 401...CCD cell, 310.409...n+
Substrate, 311...n+drain w4 region, 312...
p+ gate region, 313...n- high resistance layer, 314...
... Polysilicon electrode, 315 ... Insulating film, 316.
... Transparent electrode, 317.427 ... Separation region, 318
．． 413・l）tsuIru, 319・n1 diffusion region, 320
．． 327.412.416.428...St O, membrane, 321.322.410.411-CCD17) Electrode ffi area, 323-p '' expansion r!ltnm, 324.3
25.326.417.418.419.423.42
4.425...Aluminum electrode, 405...Output gate, 407...Output gate pulse, 414...MO3
n↑drain region of t-transistor, 415...MO
S transistor n+ source region, 420...p+ source fti region, 421...p1 drain region, 422
...n"gate region, 423...p-high resistance ffi
Area (a) ■ 1G (I No. 4-@ 87 (a) (shi) No. 5 @

Claims (4)

[Claims] (1) A photodetector section in which photocells having an electrostatic induction phototransistor and a capacitor connected to a control electrode of the electrostatic induction phototransistor are arranged in a line or matrix, and the electrostatic induction phototransistor. a capacitor for accumulating an output signal obtained by amplifying the optical input incident on the photocell flowing between main electrodes of the photocell; a charge transfer element for transferring the signal accumulated in the capacitor; and a charge transfer element for transferring from the charge transfer element. an output circuit for amplifying and detecting a signal, the photodetector, a capacitor for accumulating the output signal, the charge transfer element, and the output circuit are configured on the same semiconductor substrate. A semiconductor imaging device characterized by: (2) The semiconductor imaging device according to claim 1, wherein the output circuit is composed of a static induction transistor. (3) The semiconductor imaging device according to claim 1, wherein the output circuit is comprised of a charge transfer element. (4) a photodetection section composed of first charge transfer elements arranged in a line or matrix; a second charge transfer element for transferring the output signal of the photodetection section; and an output circuit configured of a static induction transistor for amplifying and detecting a signal transferred from the second charge transfer element, wherein the photodetector, the second charge transfer element, and the output circuit are connected to each other. A semiconductor imaging device characterized in that it is configured on the same semiconductor substrate.