JPS62156801A - Manufacture of thin film chip resistor - Google Patents

Manufacture of thin film chip resistor

Info

Publication number
JPS62156801A
JPS62156801A JP60297336A JP29733685A JPS62156801A JP S62156801 A JPS62156801 A JP S62156801A JP 60297336 A JP60297336 A JP 60297336A JP 29733685 A JP29733685 A JP 29733685A JP S62156801 A JPS62156801 A JP S62156801A
Authority
JP
Japan
Prior art keywords
thin film
film
chip resistor
resistor
film chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60297336A
Other languages
Japanese (ja)
Inventor
保元 宇ノ木
岡内 肇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tama Electric Co Ltd
Original Assignee
Tama Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tama Electric Co Ltd filed Critical Tama Electric Co Ltd
Priority to JP60297336A priority Critical patent/JPS62156801A/en
Publication of JPS62156801A publication Critical patent/JPS62156801A/en
Pending legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子機器に使用することのできる薄膜チップ
抵抗体に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film chip resistor that can be used in electronic equipment.

〔発明の概要〕[Summary of the invention]

本発明は、薄膜チップ抵抗体に関し、その抵抗−膜に対
する保護膜を、高温硬化のポリイミド前駆体形とは異な
る既にイミド化された骨格を有するポリイミドをもって
構成し、この場合、その厚味を0.5μm〜3μmでコ
ーティングし、これを200℃〜300℃で焼付けて構
成したものである。
The present invention relates to a thin film chip resistor in which the protective film for the resistor film is constructed of a polyimide having an already imidized backbone, different from the high temperature curing polyimide precursor form, in which case the thickness is reduced to 0. It is constructed by coating with a thickness of 5 μm to 3 μm and baking this at 200° C. to 300° C.

〔実施例〕〔Example〕

以下本発明による薄膜チップ抵抗体の製法を、図面を用
いて順次説明する。
Hereinafter, a method for manufacturing a thin film chip resistor according to the present invention will be sequentially explained using the drawings.

先ず第1図に示すように、アルミナ等の耐熱性及び電気
的絶縁性を有する基板(1)を設けてその下面に縦横に
延長してそれぞれ複数のV字状の溝(2a)及び(2b
)を形成する。6溝(2a)の間隔は抵抗体の長手方向
の長さとなるもので例えば3.21であり、又6溝(2
b)の間隔は抵抗体の横幅となるもので例えば1.6曙
である。
First, as shown in FIG. 1, a heat-resistant and electrically insulating substrate (1) made of alumina or the like is provided, and a plurality of V-shaped grooves (2a) and (2b) extending vertically and horizontally are formed on the bottom surface of the substrate (1).
) to form. The interval between the 6 grooves (2a) is the length in the longitudinal direction of the resistor, for example, 3.21 mm, and the interval between the 6 grooves (2a) is the length in the longitudinal direction of the resistor.
The interval b) corresponds to the width of the resistor, and is, for example, 1.6 mm.

このような基板(1)の上面の全面に、 NlCrやT
aN等の抵抗膜(金属膜)(3)を蒸着ヌはス・!ツタ
等により被着し、続いて電極となる金属膜(4)も被着
する。
The entire upper surface of such a substrate (1) is coated with NlCr or T.
Deposit a resistive film (metal film) (3) such as aN! It is deposited by ivy or the like, and then a metal film (4) which becomes an electrode is also deposited.

次に@2図に示すように、置溝(2r)と(2a)との
中間部に対応する部分の電極金属膜(4)を、溝(2a
)の延長方向に沿ってエツチング除去し、よって電極金
属膜(4)を、溝(2a)に対応した部分のみに、この
溝(2a)の延長方向に沿って延長するように、帯状に
残す。
Next, as shown in Figure @2, the electrode metal film (4) in the part corresponding to the intermediate part between the grooves (2r) and (2a) is removed from the groove (2a).
) is removed by etching along the extending direction of the groove (2a), thereby leaving the electrode metal film (4) in a band shape only in the portion corresponding to the groove (2a) so as to extend along the extending direction of this groove (2a). .

その後1図示しないが抵抗膜(3)をエツチングして又
はトリハングによりこれを必要な形状に残す。
Thereafter, although not shown, the resistive film (3) is left in the required shape by etching or trihanging.

即ち必要な抵抗値となす。この工程としてはレーデ−光
線を使用したトリピング法等が用いられる。
That is, the required resistance value is set. As this step, a tripping method using a radar beam or the like is used.

次に第3図に示すように、抵抗膜(3)及び電極金属膜
(4)上を含み、基板(1)上の全面上に保護膜(5)
をコーティングする。
Next, as shown in FIG.
Coating.

この場合の保護膜(5)の材料として、高温硬化のポリ
イミド前駆体形とは異なる既にイばド化された骨格を有
する感光性ボリイばド(例えば宇部興産株式会社調のP
I−400)′f、使用し、これを0.5μm〜3μm
の範囲で被着する。この場合、いわゆるスピンコード法
を利用することにより、このポリイミドを均一な面とな
すことができる。かかる保護膜(5)に対して60℃の
温度をもって30分間予備乾燥をなし、その後マスクを
使用して保護膜(5)のほぼ電極金属膜(4)と対応す
る部分以外の部分を0.2〜0.5恰の光の強さで露光
させて、この部分を硬化させ。
In this case, as a material for the protective film (5), a photosensitive polyimide having an already iridized skeleton (for example, Ube Industries Co., Ltd.'s P
I-400)'f is used, and this is 0.5 μm to 3 μm.
Covers within the range of . In this case, the polyimide can be made into a uniform surface by using the so-called spin code method. The protective film (5) is pre-dried at a temperature of 60° C. for 30 minutes, and then a mask is used to dry the protective film (5) except for the portion that corresponds to the electrode metal film (4). Expose to light at a light intensity of 2 to 0.5 to harden this area.

その後30秒〜2分間にわたシ現像して保護膜(5)の
未露光部分を除去する。第4図はこの状態を示すもので
、これにより上述した2極金属膜(4)が露出される。
Thereafter, it is developed for 30 seconds to 2 minutes to remove the unexposed portion of the protective film (5). FIG. 4 shows this state, whereby the above-mentioned bipolar metal film (4) is exposed.

このようにして電極金属膜(4)の露出後、全体をアル
コールにより洗浄し、その後250”Cの温度中におい
て、はぼ1時間にわたり保護膜(5)を・暁付ける。
After exposing the electrode metal film (4) in this way, the entire structure is cleaned with alcohol, and then a protective film (5) is applied at a temperature of 250''C for about 1 hour.

次に、基板(1)’t 、その溝(2a) t−利用し
て折シ、複数の短冊片(6)を得る。第5図はこのうち
の1個の短冊片(6)を示したものである。これより明
らかなように、電極金属膜(4)が両端に対となって形
成されることになり、第5図以下においてはこれをt 
W (4a)及び(4b)と称することにする。
Next, the substrate (1)'t is folded using its groove (2a) to obtain a plurality of strips (6). FIG. 5 shows one of these strips (6). As is clear from this, the electrode metal films (4) are formed in pairs on both ends, and in FIGS.
They will be referred to as W (4a) and (4b).

上述した短冊片(6)の延長方向に沿う左右両端縁に対
して、第6図に示すように、N1等の金属全短冊片(6
)の延長方向に沿って被着し、端子(7a)及び(7b
)となす。これらの形成に際しては、かかる端子(7色
)及び(7b) 1に形成する以外の部分を予めメッキ
レノストを施して先ずNiの無電解メッキをなし、その
上に更に電気メッキによりCuやNiその他の金属を被
着する。この工程は従来周知であるので、その詳細な説
明を省略する。これによシ端子(7a)は′電極(4m
)と、又端子(7b)は電極(4b)とそれぞれ電気的
に接続される。
As shown in FIG. 6, a full metal strip such as N1 (6
), and the terminals (7a) and (7b
) and eggplant. When forming these terminals (7 colors) and (7b) 1, the parts other than those to be formed should be plated in advance to electroless plate Ni, and then electroplated with Cu, Ni, and other metals by electroplating. Deposit metal. Since this process is conventionally well known, detailed explanation thereof will be omitted. With this, the terminal (7a) is connected to the 'electrode (4m
) and the terminal (7b) are electrically connected to the electrode (4b), respectively.

このようにして端子(7a)及び(7b)が形成された
後、これを、基板(1)の下面に予め形成されている溝
(2b)に沿って折り曲げて切断し、個々の薄膜チップ
抵抗体を得る。
After the terminals (7a) and (7b) are formed in this way, they are bent and cut along the grooves (2b) previously formed on the bottom surface of the substrate (1) to form individual thin film chip resistors. Get a body.

このようにして製造された抵抗体の耐湿負荷寿命を、温
度40℃、湿度95チの試験槽中で、定格直流電圧を9
0分間加え、30分間1を流を切断する工程をくり返し
行ない乍ら、その抵抗値の変化を測定したところ、第7
図に示す結果を得た。図においては横軸に時間を目盛り
、縦軸に抵抗値の変化率(ΔV幻チを目盛っており、上
述した保護膜(5)の膜厚を0.1 、0.8 、1.
5 、2.0 (各#l)に選んでそれぞれテストをし
九。第7図において、曲iaはこの膜厚が0.1amの
場合、曲線すが0.8 、1.5 、2.0 (各μm
)の場合である。
The humidity-resistant load life of the resistor manufactured in this way was determined in a test chamber at a temperature of 40°C and a humidity of 95°C, at a rated DC voltage of 95°C.
While repeating the process of adding flow for 0 minutes and cutting flow 1 for 30 minutes, we measured the change in resistance value.
The results shown in the figure were obtained. In the figure, the horizontal axis is a scale of time, and the vertical axis is a scale of change rate of resistance value (ΔV illusion).
Select 5, 2.0 (each #l) and test each. In Fig. 7, when the film thickness is 0.1 am, the curve ia is 0.8, 1.5, 2.0 (each μm
).

この結果、保護膜(5)の膜厚が0.1μmのものでは
比較的大きな経時変化が見られたが、0,8〜2.0μ
mのものでは、はとんど経時変化が見られず、又抵抗値
も、はとんど変化せず、きわめて安定していることが確
められた。
As a result, a relatively large change over time was observed when the protective film (5) had a film thickness of 0.1 μm, but
In the case of No. m, there was hardly any change in resistance over time, and the resistance value also hardly changed, and it was confirmed that the resistance value was extremely stable.

〔発明の効果〕〔Effect of the invention〕

以上説明した本発明によれば、抵抗値及び抵抗値の変化
率のそれぞれについて、きわめて安定した薄膜チップ抵
抗体を得ることができる特徴を有するものである。
According to the present invention described above, it is possible to obtain a thin film chip resistor with extremely stable resistance value and rate of change in resistance value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第6図は本発明による薄膜チップ抵抗体の製造
工程の一例を示すもので、第1図は基板に抵抗値及びT
ltl全極膜を被着した状態の一部分の斜視図、第2図
は電極金属膜の一部分を除去した状態の断面図、第3図
は全面に保護膜を被着した状態の断面図、第4図は保護
膜の一部分を除去した状態の断面図、第5図は溝(2&
)に沿って折って得られた短冊片の一例を示す斜視図、
第6図は完成された抵抗体の断面図、第7図はかくして
得られた抵抗体の耐湿負荷寿命テストの特性図である。 (1)は基板、(3)は抵抗膜、(5)は保tI膜、 
(7m) (7b)は端子である。
1 to 6 show an example of the manufacturing process of the thin film chip resistor according to the present invention, and FIG. 1 shows the resistance value and T
FIG. 2 is a perspective view of a portion of the electrode metal film with a part of it covered, FIG. 3 is a cross-sectional view of the entire surface with a protective film coated, and FIG. Figure 4 is a cross-sectional view with a portion of the protective film removed, and Figure 5 is a cross-sectional view of the groove (2&
) A perspective view showing an example of a strip obtained by folding along
FIG. 6 is a sectional view of the completed resistor, and FIG. 7 is a characteristic diagram of the humidity resistance load life test of the resistor thus obtained. (1) is the substrate, (3) is the resistive film, (5) is the retention tI film,
(7m) (7b) is a terminal.

Claims (1)

【特許請求の範囲】[Claims]  絶縁基板上に、抵抗膜を付着させ、該抵抗膜を所定の
形状となるようにエッチング又はトリミングした後、抵
抗値及び温度特性の安定化のための熱処理をなし、その
後、上記抵抗膜上を含み上記絶縁基板上に、高温硬化の
ポリイミド前駆体形とは異なる既にイミド化された骨格
を有する感光性ポリイミドよりなる保護膜を0.5μm
〜3μmの厚味でコーティングし、これをポストベーク
温度200℃〜300℃で硬化することを特徴とする薄
膜チツプ抵抗体の製法。
A resistive film is attached onto an insulating substrate, and after etching or trimming the resistive film into a predetermined shape, heat treatment is performed to stabilize the resistance value and temperature characteristics. A protective film of 0.5 μm made of a photosensitive polyimide having an already imidized skeleton, which is different from the high-temperature curing polyimide precursor type, is applied on the insulating substrate.
A method for producing a thin film chip resistor, characterized by coating the resistor with a thickness of ~3 μm and curing it at a post-baking temperature of 200°C to 300°C.
JP60297336A 1985-12-28 1985-12-28 Manufacture of thin film chip resistor Pending JPS62156801A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60297336A JPS62156801A (en) 1985-12-28 1985-12-28 Manufacture of thin film chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60297336A JPS62156801A (en) 1985-12-28 1985-12-28 Manufacture of thin film chip resistor

Publications (1)

Publication Number Publication Date
JPS62156801A true JPS62156801A (en) 1987-07-11

Family

ID=17845198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60297336A Pending JPS62156801A (en) 1985-12-28 1985-12-28 Manufacture of thin film chip resistor

Country Status (1)

Country Link
JP (1) JPS62156801A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132804A (en) * 1988-11-12 1990-05-22 Tdk Corp Chip type resistance network and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132804A (en) * 1988-11-12 1990-05-22 Tdk Corp Chip type resistance network and manufacture thereof
JP2640767B2 (en) * 1988-11-12 1997-08-13 ティーディーケイ株式会社 Method of manufacturing chip-type resistor network

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